Searched refs:pin_reg (Results 1 – 2 of 2) sorted by relevance
46 u32 pin_reg; in amd_gpio_direction_input() local50 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()55 if ((pin_reg & DB_TMR_OUT_MASK) == 0) { in amd_gpio_direction_input()56 pin_reg |= 0xf; in amd_gpio_direction_input()57 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_direction_input()58 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_direction_input()59 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_direction_input()62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()63 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()72 u32 pin_reg; in amd_gpio_direction_output() local[all …]
187 const struct imx_pin_reg *pin_reg; in imx_pmx_set() local205 pin_reg = &info->pin_regs[pin_id]; in imx_pmx_set()207 if (pin_reg->mux_reg == -1) { in imx_pmx_set()215 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set()218 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()220 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()223 pin_reg->mux_reg, pin->mux_mode); in imx_pmx_set()302 const struct imx_pin_reg *pin_reg; in imx_pmx_gpio_request_enable() local312 pin_reg = &info->pin_regs[offset]; in imx_pmx_gpio_request_enable()313 if (pin_reg->mux_reg == -1) in imx_pmx_gpio_request_enable()[all …]