| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | clk.h | 7 extern spinlock_t imx_ccm_lock;
47 shift, 0, &imx_ccm_lock, NULL); imx_clk_gate2()
55 shift, 0, &imx_ccm_lock, share_count); imx_clk_gate2_shared()
86 reg, shift, width, 0, &imx_ccm_lock); imx_clk_divider()
94 reg, shift, width, 0, &imx_ccm_lock); imx_clk_divider_flags()
101 shift, 0, &imx_ccm_lock); imx_clk_gate()
108 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); imx_clk_gate_dis()
116 width, 0, &imx_ccm_lock); imx_clk_mux()
125 &imx_ccm_lock); imx_clk_mux_flags()
|
| H A D | clk.c | 8 DEFINE_SPINLOCK(imx_ccm_lock); variable
|
| H A D | clk-busy.c | 99 busy->div.lock = &imx_ccm_lock; imx_clk_busy_divider()
173 busy->mux.lock = &imx_ccm_lock; imx_clk_busy_mux()
|
| H A D | clk-fixup-mux.c | 98 fixup_mux->mux.lock = &imx_ccm_lock; imx_clk_fixup_mux()
|
| H A D | clk-gate-exclusive.c | 85 gate->lock = &imx_ccm_lock; imx_clk_gate_exclusive()
|
| H A D | clk-fixup-div.c | 119 fixup_div->divider.lock = &imx_ccm_lock; imx_clk_fixup_divider()
|
| H A D | clk-imx6sl.c | 265 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
266 clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6sl_clocks_init()
267 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
268 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6sl_clocks_init()
269 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); imx6sl_clocks_init()
|
| H A D | clk-imx6sx.c | 228 &imx_ccm_lock); imx6sx_clocks_init()
231 &imx_ccm_lock); imx6sx_clocks_init()
256 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sx_clocks_init()
258 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6sx_clocks_init()
260 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sx_clocks_init()
262 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6sx_clocks_init()
|
| H A D | clk-imx6q.c | 217 &imx_ccm_lock); imx6q_clocks_init()
256 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
257 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6q_clocks_init()
258 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
259 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6q_clocks_init()
|
| H A D | clk-vf610.c | 232 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); vf610_clocks_init()
|