| H A D | hifn_795x.c | 688 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) hifn_write_1() function
718 hifn_write_1(dev, HIFN_1_DMA_CSR, hifn_stop_device()
722 hifn_write_1(dev, HIFN_1_DMA_IER, 0); hifn_stop_device()
732 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | hifn_reset_dma()
740 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); hifn_reset_dma()
743 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE | hifn_reset_dma()
748 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | hifn_reset_dma()
848 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) | hifn_init_pubrng()
862 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); hifn_init_pubrng()
864 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); hifn_init_pubrng()
874 hifn_write_1(dev, HIFN_1_RNG_CONFIG, hifn_init_pubrng()
908 hifn_write_1(dev, HIFN_1_DMA_CNFG, hifn_enable_crypto()
914 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0); hifn_enable_crypto()
919 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr); hifn_enable_crypto()
923 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg); hifn_enable_crypto()
1003 hifn_write_1(dev, HIFN_1_PLL, pllcfg | hifn_init_pll()
1010 hifn_write_1(dev, HIFN_1_PLL, pllcfg | hifn_init_pll()
1014 hifn_write_1(dev, HIFN_1_PLL, pllcfg | hifn_init_pll()
1036 hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr + hifn_init_registers()
1038 hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr + hifn_init_registers()
1040 hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr + hifn_init_registers()
1042 hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr + hifn_init_registers()
1047 hifn_write_1(dev, HIFN_1_DMA_CSR, hifn_init_registers()
1061 hifn_write_1(dev, HIFN_1_DMA_CSR, hifn_init_registers()
1083 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); hifn_init_registers()
1096 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | hifn_init_registers()
1148 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); hifn_setup_crypto_command()
1274 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); hifn_setup_cmd_desc()
1309 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); hifn_setup_src_desc()
1336 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); hifn_setup_res_desc()
1365 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); hifn_setup_dst_desc()
1912 hifn_write_1(dev, HIFN_1_DMA_CSR, r); hifn_work()
1971 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); hifn_interrupt()
1976 hifn_write_1(dev, HIFN_1_PUB_STATUS, hifn_interrupt()
1989 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | hifn_interrupt()
2009 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); hifn_interrupt()
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