Searched refs:dpll_hw_state (Results 1 – 5 of 5) sorted by relevance
1589 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll()1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()1678 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll()1710 crtc->config->dpll_hw_state.dpll_md); in i9xx_enable_pll()4138 if (memcmp(&crtc_state->dpll_hw_state, in intel_get_shared_dpll()4163 pll->new_config->hw_state = crtc_state->dpll_hw_state; in intel_get_shared_dpll()5343 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()5344 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()[all …]
974 crtc_state->dpll_hw_state.wrpll = val; in hsw_ddi_pll_select()1196 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_pll_select()1197 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_pll_select()1198 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_pll_select()1552 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); in intel_ddi_pre_enable()
425 intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | in intel_dsi_pre_enable()633 pipe_config->dpll_hw_state.dpll_md = 0; in intel_dsi_get_config()
347 struct intel_dpll_hw_state dpll_hw_state; member
1087 pipe_config->dpll_hw_state.cfgcr1 = 0; in skl_edp_set_pll_config()1088 pipe_config->dpll_hw_state.cfgcr2 = 0; in skl_edp_set_pll_config()1121 pipe_config->dpll_hw_state.ctrl1 = ctrl1; in skl_edp_set_pll_config()