| H A D | dib0090.c | 216 static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) dib0090_read_reg() function
349 v = dib0090_read_reg(state, 0x1a); dib0090_identify()
546 PllCfg = dib0090_read_reg(state, 0x21); dib0090_reset_digital()
571 v = !!(dib0090_read_reg(state, 0x1a) & 0x800); dib0090_reset_digital()
672 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_wakeup()
1047 dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a)); dib0090_set_rframp_pwm()
1066 dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33)); dib0090_set_bbramp_pwm()
1148 u16 adc_val = dib0090_read_reg(state, 0x1d); dib0090_get_slow_adc_val()
1382 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) dib0090_set_switch()
1393 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) dib0090_set_vga()
1511 e2 = dib0090_read_reg(state, 0x26); dib0090_set_EFUSE()
1512 e4 = dib0090_read_reg(state, 0x28); dib0090_set_EFUSE()
1518 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff; dib0090_set_EFUSE()
1563 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2) dib0090_reset()
1589 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); dib0090_reset()
1610 state->adc_diff = dib0090_read_reg(state, 0x1d); dib0090_get_offset()
1618 state->adc_diff -= dib0090_read_reg(state, 0x1d); dib0090_get_offset()
1688 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ dib0090_dc_offset_calibration()
1691 state->wbdmux = dib0090_read_reg(state, 0x10); dib0090_dc_offset_calibration()
1693 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); dib0090_dc_offset_calibration()
2069 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) dib0090_update_tuning_table_7090()
2071 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) dib0090_update_tuning_table_7090()
2105 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f; dib0090_captrim_search()
2116 dib0090_read_reg(state, 0x40); dib0090_captrim_search()
2130 dib0090_read_reg(state, 0x40); dib0090_captrim_search()
2132 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F; dib0090_captrim_search()
2189 state->wbdmux = dib0090_read_reg(state, 0x10); dib0090_get_temperature()
2192 state->bias = dib0090_read_reg(state, 0x13); dib0090_get_temperature()
2221 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_get_temperature()
2254 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); dib0090_tune()
2258 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); dib0090_tune()
2275 tmp = dib0090_read_reg(state, 0x39); dib0090_tune()
2476 dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17)); dib0090_tune()
2477 dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8), dib0090_tune()
2478 (u32) dib0090_read_reg(state, 0x1c) & 0x3); dib0090_tune()
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