Searched refs:basereg (Results 1 - 6 of 6) sorted by relevance

/linux-4.1.27/drivers/ide/
H A Dcs5530.c55 unsigned long basereg = CS5530_BASEREG(hwif); cs5530_set_pio_mode() local
56 unsigned int format = (inl(basereg + 4) >> 31) & 1; cs5530_set_pio_mode()
59 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3)); cs5530_set_pio_mode()
105 unsigned long basereg; cs5530_set_dma_mode() local
116 basereg = CS5530_BASEREG(hwif); cs5530_set_dma_mode()
117 reg = inl(basereg + 4); /* get drive0 config register */ cs5530_set_dma_mode()
120 outl(timings, basereg + 4); /* write drive0 config register */ cs5530_set_dma_mode()
126 outl(reg, basereg + 4); /* write drive0 config register */ cs5530_set_dma_mode()
127 outl(timings, basereg + 12); /* write drive1 config register */ cs5530_set_dma_mode()
231 unsigned long basereg; init_hwif_cs5530() local
234 basereg = CS5530_BASEREG(hwif); init_hwif_cs5530()
235 d0_timings = inl(basereg + 0); init_hwif_cs5530()
237 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0); init_hwif_cs5530()
238 if (CS5530_BAD_PIO(inl(basereg + 8))) init_hwif_cs5530()
239 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8); init_hwif_cs5530()
H A Dsc1200.c85 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; sc1200_tunepio() local
87 pci_read_config_dword(pdev, basereg + 4, &format); sc1200_tunepio()
91 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), sc1200_tunepio()
131 unsigned int basereg = hwif->channel ? 0x50 : 0x40; sc1200_set_dma_mode() local
159 pci_read_config_dword(dev, basereg + 4, &reg); sc1200_set_dma_mode()
161 pci_write_config_dword(dev, basereg + 4, timings); sc1200_set_dma_mode()
163 pci_write_config_dword(dev, basereg + 12, timings); sc1200_set_dma_mode()
H A Dtrm290.c278 * for the control basereg, so this kludge ensures that we use only init_hwif_trm290()
295 printk(KERN_INFO "%s: control basereg workaround: " init_hwif_trm290()
/linux-4.1.27/drivers/bus/
H A Dmvebu-mbus.c180 u32 basereg = readl(addr + WIN_BASE_OFF); mvebu_mbus_read_window() local
189 *base = ((u64)basereg & WIN_BASE_HIGH) << 32; mvebu_mbus_read_window()
190 *base |= (basereg & WIN_BASE_LOW); mvebu_mbus_read_window()
390 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); mvebu_sdram_debug_show_orion() local
400 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32; mvebu_sdram_debug_show_orion()
401 base |= basereg & DDR_BASE_CS_LOW_MASK; mvebu_sdram_debug_show_orion()
/linux-4.1.27/arch/sh/kernel/
H A Dtraps_64.c90 int basereg; generate_and_check_address() local
99 basereg = (opcode >> 20) & 0x3f; generate_and_check_address()
100 base_address = regs->regs[basereg]; generate_and_check_address()
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_dp_mst_topology.c2168 int basereg = up ? DP_SIDEBAND_MSG_UP_REQ_BASE : DP_SIDEBAND_MSG_DOWN_REP_BASE; drm_dp_get_one_sb_msg() local
2172 ret = drm_dp_dpcd_read(mgr->aux, basereg, drm_dp_get_one_sb_msg()
2190 ret = drm_dp_dpcd_read(mgr->aux, basereg + curreply, drm_dp_get_one_sb_msg()

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