Searched refs:ae (Results 1 - 53 of 53) sorted by relevance

/linux-4.1.27/drivers/crypto/qat/qat_common/
H A Dqat_hal.c78 #define AE(handle, ae) handle->hal_handle->aes[ae]
112 unsigned char ae, unsigned int ctx_mask) qat_hal_set_live_ctx()
114 AE(handle, ae).live_ctx_mask = ctx_mask; qat_hal_set_live_ctx()
119 unsigned char ae, unsigned int csr, qat_hal_rd_ae_csr()
125 *value = GET_AE_CSR(handle, ae, csr); qat_hal_rd_ae_csr()
126 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) qat_hal_rd_ae_csr()
135 unsigned char ae, unsigned int csr, qat_hal_wr_ae_csr()
141 SET_AE_CSR(handle, ae, csr, value); qat_hal_wr_ae_csr()
142 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) qat_hal_wr_ae_csr()
151 unsigned char ae, unsigned char ctx, qat_hal_get_wakeup_event()
156 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); qat_hal_get_wakeup_event()
157 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); qat_hal_get_wakeup_event()
158 qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, events); qat_hal_get_wakeup_event()
159 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); qat_hal_get_wakeup_event()
163 unsigned char ae, unsigned int cycles, qat_hal_wait_cycles()
171 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &base_cnt); qat_hal_wait_cycles()
175 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr); qat_hal_wait_cycles()
177 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &cur_cnt); qat_hal_wait_cycles()
199 unsigned char ae, unsigned char mode) qat_hal_set_ae_ctx_mode()
209 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); qat_hal_set_ae_ctx_mode()
214 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); qat_hal_set_ae_ctx_mode()
219 unsigned char ae, unsigned char mode) qat_hal_set_ae_nn_mode()
223 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); qat_hal_set_ae_nn_mode()
231 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); qat_hal_set_ae_nn_mode()
237 unsigned char ae, enum icp_qat_uof_regtype lm_type, qat_hal_set_ae_lm_mode()
242 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); qat_hal_set_ae_lm_mode()
261 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); qat_hal_set_ae_lm_mode()
325 unsigned char ae, unsigned int ctx_mask, qat_hal_wr_indr_csr()
330 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); qat_hal_wr_indr_csr()
335 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); qat_hal_wr_indr_csr()
336 qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val); qat_hal_wr_indr_csr()
339 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); qat_hal_wr_indr_csr()
343 unsigned char ae, unsigned char ctx, qat_hal_rd_indr_csr()
348 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); qat_hal_rd_indr_csr()
349 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); qat_hal_rd_indr_csr()
350 qat_hal_rd_ae_csr(handle, ae, ae_csr, csr_val); qat_hal_rd_indr_csr()
351 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); qat_hal_rd_indr_csr()
355 unsigned char ae, unsigned int ctx_mask, qat_hal_put_sig_event()
360 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); qat_hal_put_sig_event()
364 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); qat_hal_put_sig_event()
365 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_INDIRECT, events); qat_hal_put_sig_event()
367 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); qat_hal_put_sig_event()
371 unsigned char ae, unsigned int ctx_mask, qat_hal_put_wakeup_event()
376 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); qat_hal_put_wakeup_event()
380 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); qat_hal_put_wakeup_event()
381 qat_hal_wr_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, qat_hal_put_wakeup_event()
384 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); qat_hal_put_wakeup_event()
390 unsigned char ae; qat_hal_check_ae_alive() local
393 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_hal_check_ae_alive()
394 if (!(handle->hal_handle->ae_mask & (1 << ae))) qat_hal_check_ae_alive()
397 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, qat_hal_check_ae_alive()
402 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, qat_hal_check_ae_alive()
408 pr_err("QAT: AE%d is inactive!!\n", ae); qat_hal_check_ae_alive()
419 unsigned char ae; qat_hal_reset_timestamp() local
427 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_hal_reset_timestamp()
428 if (!(handle->hal_handle->ae_mask & (1 << ae))) qat_hal_reset_timestamp()
430 qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); qat_hal_reset_timestamp()
431 qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0); qat_hal_reset_timestamp()
470 unsigned char ae; qat_hal_clr_reset() local
495 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_hal_clr_reset()
496 if (!(handle->hal_handle->ae_mask & (1 << ae))) qat_hal_clr_reset()
498 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, qat_hal_clr_reset()
500 qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX, qat_hal_clr_reset()
504 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE); qat_hal_clr_reset()
505 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE); qat_hal_clr_reset()
506 qat_hal_put_wakeup_event(handle, ae, qat_hal_clr_reset()
509 qat_hal_put_sig_event(handle, ae, qat_hal_clr_reset()
526 unsigned char ae, unsigned int ctx_mask) qat_hal_disable_ctx()
530 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); qat_hal_disable_ctx()
533 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); qat_hal_disable_ctx()
567 unsigned char ae, unsigned int uaddr, qat_hal_wr_uwords()
573 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); qat_hal_wr_uwords()
575 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); qat_hal_wr_uwords()
583 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); qat_hal_wr_uwords()
584 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); qat_hal_wr_uwords()
586 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); qat_hal_wr_uwords()
590 unsigned char ae, unsigned int ctx_mask) qat_hal_enable_ctx()
594 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); qat_hal_enable_ctx()
598 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); qat_hal_enable_ctx()
603 unsigned char ae; qat_hal_clear_gpr() local
611 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_hal_clear_gpr()
612 if (!(handle->hal_handle->ae_mask & (1 << ae))) qat_hal_clear_gpr()
615 qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS, qat_hal_clear_gpr()
617 qat_hal_init_rd_xfer(handle, ae, 0, ICP_DR_RD_ABS, qat_hal_clear_gpr()
620 qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val); qat_hal_clear_gpr()
622 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); qat_hal_clear_gpr()
623 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr_val); qat_hal_clear_gpr()
626 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val); qat_hal_clear_gpr()
627 qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst), qat_hal_clear_gpr()
629 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, qat_hal_clear_gpr()
632 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); qat_hal_clear_gpr()
633 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0); qat_hal_clear_gpr()
634 qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY); qat_hal_clear_gpr()
635 qat_hal_wr_indr_csr(handle, ae, ctx_mask, qat_hal_clear_gpr()
637 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); qat_hal_clear_gpr()
638 qat_hal_enable_ctx(handle, ae, ctx_mask); qat_hal_clear_gpr()
640 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_hal_clear_gpr()
641 if (!(handle->hal_handle->ae_mask & (1 << ae))) qat_hal_clear_gpr()
645 ret = qat_hal_wait_cycles(handle, ae, 20, 1); qat_hal_clear_gpr()
649 pr_err("QAT: clear GPR of AE %d failed", ae); qat_hal_clear_gpr()
652 qat_hal_disable_ctx(handle, ae, ctx_mask); qat_hal_clear_gpr()
653 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, qat_hal_clear_gpr()
655 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, qat_hal_clear_gpr()
657 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, qat_hal_clear_gpr()
660 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE); qat_hal_clear_gpr()
661 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE); qat_hal_clear_gpr()
662 qat_hal_put_wakeup_event(handle, ae, ctx_mask, qat_hal_clear_gpr()
664 qat_hal_put_sig_event(handle, ae, ctx_mask, qat_hal_clear_gpr()
677 unsigned char ae; qat_hal_init() local
706 for (ae = 0; ae < ICP_QAT_UCLO_MAX_AE; ae++) { qat_hal_init()
707 if (!(hw_data->ae_mask & (1 << ae))) qat_hal_init()
709 handle->hal_handle->aes[ae].free_addr = 0; qat_hal_init()
710 handle->hal_handle->aes[ae].free_size = qat_hal_init()
712 handle->hal_handle->aes[ae].ustore_size = qat_hal_init()
714 handle->hal_handle->aes[ae].live_ctx_mask = qat_hal_init()
716 max_en_ae_id = ae; qat_hal_init()
727 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_hal_init()
730 if (!(hw_data->ae_mask & (1 << ae))) qat_hal_init()
732 qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val); qat_hal_init()
734 qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); qat_hal_init()
754 void qat_hal_start(struct icp_qat_fw_loader_handle *handle, unsigned char ae, qat_hal_start() argument
757 qat_hal_put_wakeup_event(handle, ae, (~ctx_mask) & qat_hal_start()
759 qat_hal_enable_ctx(handle, ae, ctx_mask); qat_hal_start()
762 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae, qat_hal_stop() argument
765 qat_hal_disable_ctx(handle, ae, ctx_mask); qat_hal_stop()
769 unsigned char ae, unsigned int ctx_mask, unsigned int upc) qat_hal_set_pc()
771 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, qat_hal_set_pc()
776 unsigned char ae, unsigned int uaddr, qat_hal_get_uwords()
782 qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &misc_control); qat_hal_get_uwords()
783 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, qat_hal_get_uwords()
785 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); qat_hal_get_uwords()
788 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); qat_hal_get_uwords()
790 qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER, &uwrd_lo); qat_hal_get_uwords()
791 qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER, &uwrd_hi); qat_hal_get_uwords()
795 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, misc_control); qat_hal_get_uwords()
796 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); qat_hal_get_uwords()
800 unsigned char ae, unsigned int uaddr, qat_hal_wr_umem()
805 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); qat_hal_wr_umem()
807 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); qat_hal_wr_umem()
818 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); qat_hal_wr_umem()
819 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); qat_hal_wr_umem()
821 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); qat_hal_wr_umem()
826 unsigned char ae, unsigned char ctx, qat_hal_exec_micro_inst()
846 qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT, &ind_lm_addr0); qat_hal_exec_micro_inst()
847 qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT, &ind_lm_addr1); qat_hal_exec_micro_inst()
848 qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_0_BYTE_INDEX, qat_hal_exec_micro_inst()
850 qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_1_BYTE_INDEX, qat_hal_exec_micro_inst()
853 qat_hal_get_uwords(handle, ae, 0, inst_num, savuwords); qat_hal_exec_micro_inst()
854 qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events); qat_hal_exec_micro_inst()
855 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, &savpc); qat_hal_exec_micro_inst()
857 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); qat_hal_exec_micro_inst()
859 qat_hal_rd_ae_csr(handle, ae, CC_ENABLE, &savcc); qat_hal_exec_micro_inst()
860 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); qat_hal_exec_micro_inst()
861 qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_ctl); qat_hal_exec_micro_inst()
862 qat_hal_rd_indr_csr(handle, ae, ctx, FUTURE_COUNT_SIGNAL_INDIRECT, qat_hal_exec_micro_inst()
864 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_SIG_EVENTS_INDIRECT, &ind_sig); qat_hal_exec_micro_inst()
865 qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, &act_sig); qat_hal_exec_micro_inst()
867 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); qat_hal_exec_micro_inst()
868 qat_hal_wr_uwords(handle, ae, 0, inst_num, micro_inst); qat_hal_exec_micro_inst()
869 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 0); qat_hal_exec_micro_inst()
870 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO); qat_hal_exec_micro_inst()
872 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc & 0xffffdfff); qat_hal_exec_micro_inst()
873 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), XCWE_VOLUNTARY); qat_hal_exec_micro_inst()
874 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, 0); qat_hal_exec_micro_inst()
875 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); qat_hal_exec_micro_inst()
876 qat_hal_enable_ctx(handle, ae, (1 << ctx)); qat_hal_exec_micro_inst()
878 if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0) qat_hal_exec_micro_inst()
883 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, qat_hal_exec_micro_inst()
888 qat_hal_disable_ctx(handle, ae, (1 << ctx)); qat_hal_exec_micro_inst()
890 qat_hal_wr_uwords(handle, ae, 0, inst_num, savuwords); qat_hal_exec_micro_inst()
891 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events); qat_hal_exec_micro_inst()
892 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, qat_hal_exec_micro_inst()
894 qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val); qat_hal_exec_micro_inst()
896 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val); qat_hal_exec_micro_inst()
897 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc); qat_hal_exec_micro_inst()
898 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, savctx & ACS_ACNO); qat_hal_exec_micro_inst()
899 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_ctl); qat_hal_exec_micro_inst()
900 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), qat_hal_exec_micro_inst()
902 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), qat_hal_exec_micro_inst()
904 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), qat_hal_exec_micro_inst()
906 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), qat_hal_exec_micro_inst()
908 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), qat_hal_exec_micro_inst()
910 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), qat_hal_exec_micro_inst()
912 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig); qat_hal_exec_micro_inst()
913 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); qat_hal_exec_micro_inst()
919 unsigned char ae, unsigned char ctx, qat_hal_rd_rel_reg()
942 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); qat_hal_rd_rel_reg()
943 qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_cntl); qat_hal_rd_rel_reg()
944 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); qat_hal_rd_rel_reg()
947 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, qat_hal_rd_rel_reg()
949 qat_hal_get_uwords(handle, ae, 0, 1, &savuword); qat_hal_rd_rel_reg()
950 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); qat_hal_rd_rel_reg()
951 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); qat_hal_rd_rel_reg()
953 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); qat_hal_rd_rel_reg()
957 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); qat_hal_rd_rel_reg()
958 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); qat_hal_rd_rel_reg()
959 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); qat_hal_rd_rel_reg()
961 qat_hal_wait_cycles(handle, ae, 0x8, 0); qat_hal_rd_rel_reg()
967 qat_hal_rd_ae_csr(handle, ae, ALU_OUT, data); qat_hal_rd_rel_reg()
968 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); qat_hal_rd_rel_reg()
969 qat_hal_wr_uwords(handle, ae, 0, 1, &savuword); qat_hal_rd_rel_reg()
971 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, qat_hal_rd_rel_reg()
973 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_cntl); qat_hal_rd_rel_reg()
974 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); qat_hal_rd_rel_reg()
980 unsigned char ae, unsigned char ctx, qat_hal_wr_rel_reg()
1022 return qat_hal_exec_micro_inst(handle, ae, ctx, insts, num_inst, qat_hal_wr_rel_reg()
1062 unsigned char ae, unsigned char ctx, qat_hal_exec_micro_init_lm()
1071 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, &gpra0); qat_hal_exec_micro_init_lm()
1072 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, &gpra1); qat_hal_exec_micro_init_lm()
1073 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, &gpra2); qat_hal_exec_micro_init_lm()
1074 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, &gprb0); qat_hal_exec_micro_init_lm()
1075 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, &gprb1); qat_hal_exec_micro_init_lm()
1078 stat = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, inst_num, 1, qat_hal_exec_micro_init_lm()
1082 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, gpra0); qat_hal_exec_micro_init_lm()
1083 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, gpra1); qat_hal_exec_micro_init_lm()
1084 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, gpra2); qat_hal_exec_micro_init_lm()
1085 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, gprb0); qat_hal_exec_micro_init_lm()
1086 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, gprb1); qat_hal_exec_micro_init_lm()
1092 unsigned char ae, qat_hal_batch_wr_lm()
1114 ae = plm_init->ae; qat_hal_batch_wr_lm()
1126 stat = qat_hal_exec_micro_init_lm(handle, ae, 0, &first_exec, qat_hal_batch_wr_lm()
1135 unsigned char ae, unsigned char ctx, qat_hal_put_rel_rd_xfer()
1145 status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); qat_hal_put_rel_rd_xfer()
1162 SET_AE_XFER(handle, ae, reg_addr, val); qat_hal_put_rel_rd_xfer()
1166 SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val); qat_hal_put_rel_rd_xfer()
1176 unsigned char ae, unsigned char ctx, qat_hal_put_rel_wr_xfer()
1195 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); qat_hal_put_rel_wr_xfer()
1212 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, &gprval); qat_hal_put_rel_wr_xfer()
1226 status = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, num_inst, qat_hal_put_rel_wr_xfer()
1228 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, gprval); qat_hal_put_rel_wr_xfer()
1233 unsigned char ae, unsigned char ctx, qat_hal_put_rel_nn()
1239 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); qat_hal_put_rel_nn()
1241 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE); qat_hal_put_rel_nn()
1243 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val); qat_hal_put_rel_nn()
1244 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); qat_hal_put_rel_nn()
1249 *handle, unsigned char ae, qat_hal_convert_abs_to_rel()
1256 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); qat_hal_convert_abs_to_rel()
1270 unsigned char ae, unsigned char ctx_mask, qat_hal_init_gpr()
1284 qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg, qat_hal_init_gpr()
1293 stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata); qat_hal_init_gpr()
1304 unsigned char ae, unsigned char ctx_mask, qat_hal_init_wr_xfer()
1318 qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg, qat_hal_init_wr_xfer()
1327 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg, qat_hal_init_wr_xfer()
1339 unsigned char ae, unsigned char ctx_mask, qat_hal_init_rd_xfer()
1353 qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg, qat_hal_init_rd_xfer()
1362 stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg, qat_hal_init_rd_xfer()
1374 unsigned char ae, unsigned char ctx_mask, qat_hal_init_nn()
1386 stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata); qat_hal_init_nn()
111 qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask) qat_hal_set_live_ctx() argument
118 qat_hal_rd_ae_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int csr, unsigned int *value) qat_hal_rd_ae_csr() argument
134 qat_hal_wr_ae_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int csr, unsigned int value) qat_hal_wr_ae_csr() argument
150 qat_hal_get_wakeup_event(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, unsigned int *events) qat_hal_get_wakeup_event() argument
162 qat_hal_wait_cycles(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int cycles, int chk_inactive) qat_hal_wait_cycles() argument
198 qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char mode) qat_hal_set_ae_ctx_mode() argument
218 qat_hal_set_ae_nn_mode(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char mode) qat_hal_set_ae_nn_mode() argument
236 qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle, unsigned char ae, enum icp_qat_uof_regtype lm_type, unsigned char mode) qat_hal_set_ae_lm_mode() argument
324 qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask, unsigned int ae_csr, unsigned int csr_val) qat_hal_wr_indr_csr() argument
342 qat_hal_rd_indr_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, unsigned int ae_csr, unsigned int *csr_val) qat_hal_rd_indr_csr() argument
354 qat_hal_put_sig_event(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask, unsigned int events) qat_hal_put_sig_event() argument
370 qat_hal_put_wakeup_event(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask, unsigned int events) qat_hal_put_wakeup_event() argument
525 qat_hal_disable_ctx(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask) qat_hal_disable_ctx() argument
566 qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int uaddr, unsigned int words_num, uint64_t *uword) qat_hal_wr_uwords() argument
589 qat_hal_enable_ctx(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask) qat_hal_enable_ctx() argument
768 qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int ctx_mask, unsigned int upc) qat_hal_set_pc() argument
775 qat_hal_get_uwords(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int uaddr, unsigned int words_num, uint64_t *uword) qat_hal_get_uwords() argument
799 qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int uaddr, unsigned int words_num, unsigned int *data) qat_hal_wr_umem() argument
825 qat_hal_exec_micro_inst(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, uint64_t *micro_inst, unsigned int inst_num, int code_off, unsigned int max_cycle, unsigned int *endpc) qat_hal_exec_micro_inst() argument
918 qat_hal_rd_rel_reg(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int *data) qat_hal_rd_rel_reg() argument
979 qat_hal_wr_rel_reg(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int data) qat_hal_wr_rel_reg() argument
1061 qat_hal_exec_micro_init_lm(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, int *pfirst_exec, uint64_t *micro_inst, unsigned int inst_num) qat_hal_exec_micro_init_lm() argument
1091 qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle, unsigned char ae, struct icp_qat_uof_batch_init *lm_init_header) qat_hal_batch_wr_lm() argument
1134 qat_hal_put_rel_rd_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int val) qat_hal_put_rel_rd_xfer() argument
1175 qat_hal_put_rel_wr_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int data) qat_hal_put_rel_wr_xfer() argument
1232 qat_hal_put_rel_nn(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx, unsigned short nn, unsigned int val) qat_hal_put_rel_nn() argument
1248 qat_hal_convert_abs_to_rel(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned short absreg_num, unsigned short *relreg, unsigned char *ctx) qat_hal_convert_abs_to_rel() argument
1269 qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int regdata) qat_hal_init_gpr() argument
1303 qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int regdata) qat_hal_init_wr_xfer() argument
1338 qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_num, unsigned int regdata) qat_hal_init_rd_xfer() argument
1373 qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx_mask, unsigned short reg_num, unsigned int regdata) qat_hal_init_nn() argument
H A Dqat_uclo.c63 unsigned int ae, unsigned int image_num) qat_uclo_init_ae_data()
70 ae_data = &obj_handle->ae_data[ae]; qat_uclo_init_ae_data()
159 unsigned char ae, unsigned int addr, qat_uclo_wr_umem_by_words()
170 qat_hal_wr_umem(handle, ae, addr++, 1, &outval); qat_uclo_wr_umem_by_words()
177 unsigned char ae, qat_uclo_batch_wr_umem()
189 ae = umem_init->ae; qat_uclo_batch_wr_umem()
193 qat_uclo_wr_umem_by_words(handle, ae, addr, value, size); qat_uclo_batch_wr_umem()
218 unsigned long ae = 0; qat_uclo_parse_num() local
228 if ((kstrtoul(buf, 10, &ae))) qat_uclo_parse_num()
231 *num = (unsigned int)ae; qat_uclo_parse_num()
237 unsigned int size_range, unsigned int *ae) qat_uclo_fetch_initmem_ae()
255 if (qat_uclo_parse_num(str, ae)) { qat_uclo_fetch_initmem_ae()
259 if (*ae >= ICP_QAT_UCLO_MAX_AE) { qat_uclo_fetch_initmem_ae()
260 pr_err("QAT: ae %d out of range\n", *ae); qat_uclo_fetch_initmem_ae()
268 *init_mem, unsigned int ae, qat_uclo_create_batch_init_list()
298 mem_init->ae = ae; qat_uclo_create_batch_init_list()
324 unsigned int ae; qat_uclo_init_lmem_seg() local
327 ICP_QAT_UCLO_MAX_LMEM_REG, &ae)) qat_uclo_init_lmem_seg()
329 if (qat_uclo_create_batch_init_list(handle, init_mem, ae, qat_uclo_init_lmem_seg()
330 &obj_handle->lm_init_tab[ae])) qat_uclo_init_lmem_seg()
339 unsigned int ae, ustore_size, uaddr, i; qat_uclo_init_umem_seg() local
342 if (qat_uclo_fetch_initmem_ae(handle, init_mem, ustore_size, &ae)) qat_uclo_init_umem_seg()
344 if (qat_uclo_create_batch_init_list(handle, init_mem, ae, qat_uclo_init_umem_seg()
345 &obj_handle->umem_init_tab[ae])) qat_uclo_init_umem_seg()
349 for (i = 0; i < obj_handle->ae_data[ae].slice_num; i++) { qat_uclo_init_umem_seg()
350 if (obj_handle->ae_data[ae].ae_slices[i]. qat_uclo_init_umem_seg()
352 obj_handle->ae_data[ae].ae_slices[i]. qat_uclo_init_umem_seg()
406 unsigned char ae; qat_uclo_init_ustore() local
422 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_uclo_init_ustore()
423 if (!test_bit(ae, (unsigned long *)&uof_image->ae_assigned)) qat_uclo_init_ustore()
425 ustore_size = obj_handle->ae_data[ae].eff_ustore_size; qat_uclo_init_ustore()
428 qat_hal_wr_uwords(handle, (unsigned char)ae, 0, qat_uclo_init_ustore()
430 qat_hal_wr_uwords(handle, (unsigned char)ae, patt_pos, qat_uclo_init_ustore()
440 int i, ae; qat_uclo_init_memory() local
455 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_uclo_init_memory()
456 if (qat_hal_batch_wr_lm(handle, ae, qat_uclo_init_memory()
457 obj_handle->lm_init_tab[ae])) { qat_uclo_init_memory()
458 pr_err("QAT: fail to batch init lmem for AE %d\n", ae); qat_uclo_init_memory()
462 &obj_handle->lm_init_tab[ae]); qat_uclo_init_memory()
463 qat_uclo_batch_wr_umem(handle, ae, qat_uclo_init_memory()
464 obj_handle->umem_init_tab[ae]); qat_uclo_init_memory()
467 umem_init_tab[ae]); qat_uclo_init_memory()
683 int i, ae; qat_uclo_map_ae() local
687 for (ae = 0; ae <= max_ae; ae++) { qat_uclo_map_ae()
688 if (!test_bit(ae, qat_uclo_map_ae()
692 if (!test_bit(ae, (unsigned long *) qat_uclo_map_ae()
696 if (qat_uclo_init_ae_data(obj_handle, ae, i)) qat_uclo_map_ae()
764 unsigned char ae, unsigned char ctx_mask, qat_uclo_init_reg()
774 return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type, qat_uclo_init_reg()
785 return qat_hal_init_rd_xfer(handle, ae, ctx_mask, reg_type, qat_uclo_init_reg()
792 return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type, qat_uclo_init_reg()
795 return qat_hal_init_nn(handle, ae, ctx_mask, reg_addr, value); qat_uclo_init_reg()
804 unsigned int ae, qat_uclo_init_reg_sym()
824 qat_uclo_init_reg(handle, ae, ctx_mask, qat_uclo_init_reg_sym()
837 qat_uclo_init_reg(handle, ae, qat_uclo_init_reg_sym()
861 unsigned int s, ae; qat_uclo_init_globals() local
871 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_uclo_init_globals()
872 for (s = 0; s < obj_handle->ae_data[ae].slice_num; s++) { qat_uclo_init_globals()
873 if (!obj_handle->ae_data[ae].ae_slices[s].encap_image) qat_uclo_init_globals()
875 if (qat_uclo_init_reg_sym(handle, ae, qat_uclo_init_globals()
876 obj_handle->ae_data[ae]. qat_uclo_init_globals()
887 unsigned char ae, nn_mode, s; qat_uclo_set_ae_mode() local
892 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_uclo_set_ae_mode()
893 if (!test_bit(ae, qat_uclo_set_ae_mode()
896 ae_data = &obj_handle->ae_data[ae]; qat_uclo_set_ae_mode()
899 if (!obj_handle->ae_data[ae].ae_slices[s].encap_image) qat_uclo_set_ae_mode()
902 if (qat_hal_set_ae_ctx_mode(handle, ae, qat_uclo_set_ae_mode()
909 if (qat_hal_set_ae_nn_mode(handle, ae, nn_mode)) { qat_uclo_set_ae_mode()
913 if (qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, qat_uclo_set_ae_mode()
919 if (qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM1, qat_uclo_set_ae_mode()
946 unsigned int ae; qat_uclo_parse_uof_obj() local
986 for (ae = 0; ae < obj_handle->uimage_num; ae++) qat_uclo_parse_uof_obj()
987 kfree(obj_handle->ae_uimage[ae].page); qat_uclo_parse_uof_obj()
1086 *encap_page, unsigned int ae) qat_uclo_wr_uimage_raw_page()
1113 qat_hal_wr_uwords(handle, (unsigned char)ae, qat_uclo_wr_uimage_raw_page()
1129 unsigned char ae; qat_uclo_wr_uimage_page() local
1138 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { qat_uclo_wr_uimage_page()
1139 if (!test_bit(ae, (unsigned long *)&image->ae_assigned)) qat_uclo_wr_uimage_page()
1142 for (s = 0; s < obj_handle->ae_data[ae].slice_num; s++) { qat_uclo_wr_uimage_page()
1143 if (image->ctx_assigned & obj_handle->ae_data[ae]. qat_uclo_wr_uimage_page()
1147 if (s >= obj_handle->ae_data[ae].slice_num) qat_uclo_wr_uimage_page()
1149 page = obj_handle->ae_data[ae].ae_slices[s].page; qat_uclo_wr_uimage_page()
1152 qat_uclo_wr_uimage_raw_page(handle, page->encap_page, ae); qat_uclo_wr_uimage_page()
1154 page = obj_handle->ae_data[ae].ae_slices[s].page; qat_uclo_wr_uimage_page()
1156 obj_handle->ae_data[ae].ae_slices[s].cur_page[ctx] = qat_uclo_wr_uimage_page()
1158 qat_hal_set_live_ctx(handle, (unsigned char)ae, qat_uclo_wr_uimage_page()
1160 qat_hal_set_pc(handle, (unsigned char)ae, image->ctx_assigned, qat_uclo_wr_uimage_page()
62 qat_uclo_init_ae_data(struct icp_qat_uclo_objhandle *obj_handle, unsigned int ae, unsigned int image_num) qat_uclo_init_ae_data() argument
158 qat_uclo_wr_umem_by_words(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int addr, unsigned int *val, unsigned int num_in_bytes) qat_uclo_wr_umem_by_words() argument
176 qat_uclo_batch_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae, struct icp_qat_uof_batch_init *umem_init_header) qat_uclo_batch_wr_umem() argument
235 qat_uclo_fetch_initmem_ae(struct icp_qat_fw_loader_handle *handle, struct icp_qat_uof_initmem *init_mem, unsigned int size_range, unsigned int *ae) qat_uclo_fetch_initmem_ae() argument
266 qat_uclo_create_batch_init_list(struct icp_qat_fw_loader_handle *handle, struct icp_qat_uof_initmem *init_mem, unsigned int ae, struct icp_qat_uof_batch_init **init_tab_base) qat_uclo_create_batch_init_list() argument
763 qat_uclo_init_reg(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned char ctx_mask, enum icp_qat_uof_regtype reg_type, unsigned short reg_addr, unsigned int value) qat_uclo_init_reg() argument
803 qat_uclo_init_reg_sym(struct icp_qat_fw_loader_handle *handle, unsigned int ae, struct icp_qat_uclo_encapme *encap_ae) qat_uclo_init_reg_sym() argument
1084 qat_uclo_wr_uimage_raw_page(struct icp_qat_fw_loader_handle *handle, struct icp_qat_uclo_encap_page *encap_page, unsigned int ae) qat_uclo_wr_uimage_raw_page() argument
H A Dicp_qat_hal.h108 #define AE_CSR(handle, ae) \
110 ((ae & handle->hal_handle->ae_mask) << 12))
111 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
112 #define SET_AE_CSR(handle, ae, csr, val) \
113 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
114 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
115 #define AE_XFER(handle, ae) \
117 ((ae & handle->hal_handle->ae_mask) << 12))
118 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
120 #define SET_AE_XFER(handle, ae, reg, val) \
121 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
H A Dadf_accel_engine.c103 uint32_t ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev); adf_ae_start() local
105 for (ae = 0, ae_ctr = 0; ae < max_aes; ae++) { adf_ae_start()
106 if (hw_data->ae_mask & (1 << ae)) { adf_ae_start()
107 qat_hal_start(loader_data->fw_loader, ae, 0xFF); adf_ae_start()
121 uint32_t ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev); adf_ae_stop() local
123 for (ae = 0, ae_ctr = 0; ae < max_aes; ae++) { adf_ae_stop()
124 if (hw_data->ae_mask & (1 << ae)) { adf_ae_stop()
125 qat_hal_stop(loader_data->fw_loader, ae, 0xFF); adf_ae_stop()
135 static int adf_ae_reset(struct adf_accel_dev *accel_dev, int ae) adf_ae_reset() argument
H A Dadf_common_drv.h144 void qat_hal_start(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
146 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
151 unsigned char ae, unsigned int ctx_mask);
153 unsigned char ae, enum icp_qat_uof_regtype lm_type,
156 unsigned char ae, unsigned char mode);
158 unsigned char ae, unsigned char mode);
160 unsigned char ae, unsigned int ctx_mask, unsigned int upc);
162 unsigned char ae, unsigned int uaddr,
164 void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
169 unsigned char ae,
172 unsigned char ae, unsigned char ctx_mask,
176 unsigned char ae, unsigned char ctx_mask,
180 unsigned char ae, unsigned char ctx_mask,
184 unsigned char ae, unsigned char ctx_mask,
187 unsigned char ae, unsigned short lm_addr, unsigned int value);
H A Dicp_qat_uclo.h371 unsigned int ae; member in struct:icp_qat_uof_batch_init
/linux-4.1.27/drivers/scsi/lpfc/
H A Dlpfc_ct.c1416 struct lpfc_fdmi_attr_entry *ae; lpfc_fdmi_cmd() local
1508 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1509 memset(ae, 0, sizeof(struct lpfc_name)); lpfc_fdmi_cmd()
1513 memcpy(&ae->un.NodeName, &vport->fc_sparam.nodeName, lpfc_fdmi_cmd()
1524 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1525 memset(ae, 0, sizeof(ae->un.Manufacturer)); lpfc_fdmi_cmd()
1527 strncpy(ae->un.Manufacturer, "Emulex Corporation", lpfc_fdmi_cmd()
1528 sizeof(ae->un.Manufacturer)); lpfc_fdmi_cmd()
1529 len = strnlen(ae->un.Manufacturer, lpfc_fdmi_cmd()
1530 sizeof(ae->un.Manufacturer)); lpfc_fdmi_cmd()
1542 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1543 memset(ae, 0, sizeof(ae->un.SerialNumber)); lpfc_fdmi_cmd()
1545 strncpy(ae->un.SerialNumber, phba->SerialNumber, lpfc_fdmi_cmd()
1546 sizeof(ae->un.SerialNumber)); lpfc_fdmi_cmd()
1547 len = strnlen(ae->un.SerialNumber, lpfc_fdmi_cmd()
1548 sizeof(ae->un.SerialNumber)); lpfc_fdmi_cmd()
1560 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1561 memset(ae, 0, sizeof(ae->un.Model)); lpfc_fdmi_cmd()
1563 strncpy(ae->un.Model, phba->ModelName, lpfc_fdmi_cmd()
1564 sizeof(ae->un.Model)); lpfc_fdmi_cmd()
1565 len = strnlen(ae->un.Model, sizeof(ae->un.Model)); lpfc_fdmi_cmd()
1577 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1578 memset(ae, 0, sizeof(ae->un.ModelDescription)); lpfc_fdmi_cmd()
1580 strncpy(ae->un.ModelDescription, phba->ModelDesc, lpfc_fdmi_cmd()
1581 sizeof(ae->un.ModelDescription)); lpfc_fdmi_cmd()
1582 len = strnlen(ae->un.ModelDescription, lpfc_fdmi_cmd()
1583 sizeof(ae->un.ModelDescription)); lpfc_fdmi_cmd()
1594 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1595 memset(ae, 0, 8); lpfc_fdmi_cmd()
1603 ae->un.HardwareVersion[7 - i] = lpfc_fdmi_cmd()
1607 ae->un.HardwareVersion[7 - i] = lpfc_fdmi_cmd()
1621 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1622 memset(ae, 0, sizeof(ae->un.DriverVersion)); lpfc_fdmi_cmd()
1624 strncpy(ae->un.DriverVersion, lpfc_release_version, lpfc_fdmi_cmd()
1625 sizeof(ae->un.DriverVersion)); lpfc_fdmi_cmd()
1626 len = strnlen(ae->un.DriverVersion, lpfc_fdmi_cmd()
1627 sizeof(ae->un.DriverVersion)); lpfc_fdmi_cmd()
1639 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1640 memset(ae, 0, sizeof(ae->un.OptionROMVersion)); lpfc_fdmi_cmd()
1642 strncpy(ae->un.OptionROMVersion, phba->OptionROMVersion, lpfc_fdmi_cmd()
1643 sizeof(ae->un.OptionROMVersion)); lpfc_fdmi_cmd()
1644 len = strnlen(ae->un.OptionROMVersion, lpfc_fdmi_cmd()
1645 sizeof(ae->un.OptionROMVersion)); lpfc_fdmi_cmd()
1657 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1658 memset(ae, 0, sizeof(ae->un.FirmwareVersion)); lpfc_fdmi_cmd()
1660 lpfc_decode_firmware_rev(phba, ae->un.FirmwareVersion, lpfc_fdmi_cmd()
1662 len = strnlen(ae->un.FirmwareVersion, lpfc_fdmi_cmd()
1663 sizeof(ae->un.FirmwareVersion)); lpfc_fdmi_cmd()
1675 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1676 memset(ae, 0, sizeof(ae->un.OsNameVersion)); lpfc_fdmi_cmd()
1678 snprintf(ae->un.OsNameVersion, lpfc_fdmi_cmd()
1679 sizeof(ae->un.OsNameVersion), lpfc_fdmi_cmd()
1684 len = strnlen(ae->un.OsNameVersion, lpfc_fdmi_cmd()
1685 sizeof(ae->un.OsNameVersion)); lpfc_fdmi_cmd()
1696 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1700 ae->un.MaxCTPayloadLen = cpu_to_be32(LPFC_MAX_CT_SIZE); lpfc_fdmi_cmd()
1717 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1718 memset(ae, 0, sizeof(ae->un.NodeSymName)); lpfc_fdmi_cmd()
1721 ae->un.NodeSymName, sizeof(ae->un.NodeSymName)); lpfc_fdmi_cmd()
1763 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1764 memset(ae, 0, sizeof(ae->un.FC4Types)); lpfc_fdmi_cmd()
1768 ae->un.FC4Types[0] = 0x40; /* Type 1 - ELS */ lpfc_fdmi_cmd()
1769 ae->un.FC4Types[1] = 0x80; /* Type 8 - FCP */ lpfc_fdmi_cmd()
1770 ae->un.FC4Types[4] = 0x80; /* Type 32 - CT */ lpfc_fdmi_cmd()
1777 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1780 ae->un.SupportSpeed = 0; lpfc_fdmi_cmd()
1782 ae->un.SupportSpeed |= HBA_PORTSPEED_16GBIT; lpfc_fdmi_cmd()
1784 ae->un.SupportSpeed |= HBA_PORTSPEED_10GBIT; lpfc_fdmi_cmd()
1786 ae->un.SupportSpeed |= HBA_PORTSPEED_8GBIT; lpfc_fdmi_cmd()
1788 ae->un.SupportSpeed |= HBA_PORTSPEED_4GBIT; lpfc_fdmi_cmd()
1790 ae->un.SupportSpeed |= HBA_PORTSPEED_2GBIT; lpfc_fdmi_cmd()
1792 ae->un.SupportSpeed |= HBA_PORTSPEED_1GBIT; lpfc_fdmi_cmd()
1793 ae->un.SupportSpeed = lpfc_fdmi_cmd()
1794 cpu_to_be32(ae->un.SupportSpeed); lpfc_fdmi_cmd()
1802 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1807 ae->un.PortSpeed = HBA_PORTSPEED_1GBIT; lpfc_fdmi_cmd()
1810 ae->un.PortSpeed = HBA_PORTSPEED_2GBIT; lpfc_fdmi_cmd()
1813 ae->un.PortSpeed = HBA_PORTSPEED_4GBIT; lpfc_fdmi_cmd()
1816 ae->un.PortSpeed = HBA_PORTSPEED_8GBIT; lpfc_fdmi_cmd()
1819 ae->un.PortSpeed = HBA_PORTSPEED_10GBIT; lpfc_fdmi_cmd()
1822 ae->un.PortSpeed = HBA_PORTSPEED_16GBIT; lpfc_fdmi_cmd()
1825 ae->un.PortSpeed = HBA_PORTSPEED_UNKNOWN; lpfc_fdmi_cmd()
1828 ae->un.PortSpeed = cpu_to_be32(ae->un.PortSpeed); lpfc_fdmi_cmd()
1835 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1839 ae->un.MaxFrameSize = lpfc_fdmi_cmd()
1843 ae->un.MaxFrameSize = lpfc_fdmi_cmd()
1844 cpu_to_be32(ae->un.MaxFrameSize); lpfc_fdmi_cmd()
1854 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1855 memset(ae, 0, sizeof(ae->un.OsDeviceName)); lpfc_fdmi_cmd()
1857 strncpy((char *)ae->un.OsDeviceName, LPFC_DRIVER_NAME, lpfc_fdmi_cmd()
1858 sizeof(ae->un.OsDeviceName)); lpfc_fdmi_cmd()
1859 len = strnlen((char *)ae->un.OsDeviceName, lpfc_fdmi_cmd()
1860 sizeof(ae->un.OsDeviceName)); lpfc_fdmi_cmd()
1872 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1873 memset(ae, 0, sizeof(ae->un.HostName)); lpfc_fdmi_cmd()
1874 snprintf(ae->un.HostName, sizeof(ae->un.HostName), "%s", lpfc_fdmi_cmd()
1877 len = strnlen(ae->un.HostName, lpfc_fdmi_cmd()
1878 sizeof(ae->un.HostName)); lpfc_fdmi_cmd()
1898 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1899 memset(ae, 0, sizeof(struct lpfc_name)); lpfc_fdmi_cmd()
1903 memcpy(&ae->un.NodeName, &vport->fc_sparam.nodeName, lpfc_fdmi_cmd()
1914 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1915 memset(ae, 0, sizeof(struct lpfc_name)); lpfc_fdmi_cmd()
1919 memcpy(&ae->un.PortName, &vport->fc_sparam.portName, lpfc_fdmi_cmd()
1930 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1931 memset(ae, 0, sizeof(ae->un.NodeSymName)); lpfc_fdmi_cmd()
1934 ae->un.NodeSymName, sizeof(ae->un.NodeSymName)); lpfc_fdmi_cmd()
1945 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1947 ae->un.PortState = 0; lpfc_fdmi_cmd()
1957 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1959 ae->un.SupportClass = lpfc_fdmi_cmd()
1971 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1972 memset(ae, 0, sizeof(struct lpfc_name)); lpfc_fdmi_cmd()
1976 memcpy(&ae->un.FabricName, &vport->fabric_nodename, lpfc_fdmi_cmd()
1987 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
1988 memset(ae, 0, sizeof(ae->un.FC4Types)); lpfc_fdmi_cmd()
1992 ae->un.FC4Types[0] = 0x40; /* Type 1 - ELS */ lpfc_fdmi_cmd()
1993 ae->un.FC4Types[1] = 0x80; /* Type 8 - FCP */ lpfc_fdmi_cmd()
1994 ae->un.FC4Types[4] = 0x80; /* Type 32 - CT */ lpfc_fdmi_cmd()
2003 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
2005 ae->un.PortState = 0; lpfc_fdmi_cmd()
2015 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
2017 ae->un.PortState = lpfc_find_map_node(vport); lpfc_fdmi_cmd()
2018 ae->un.PortState = cpu_to_be32(ae->un.PortState); lpfc_fdmi_cmd()
2028 ae = (struct lpfc_fdmi_attr_entry *)&ad->AttrValue; lpfc_fdmi_cmd()
2030 ae->un.PortId = cpu_to_be32(vport->fc_myDID); lpfc_fdmi_cmd()
/linux-4.1.27/drivers/scsi/esas2r/
H A Desas2r_int.c702 static void esas2r_lun_event(struct esas2r_adapter *a, union atto_vda_ae *ae, esas2r_lun_event() argument
712 esas2r_trace("ae->lu.dwevent: %x", ae->lu.dwevent); esas2r_lun_event()
713 esas2r_trace("ae->lu.bystate: %x", ae->lu.bystate); esas2r_lun_event()
719 if (ae->lu.dwevent & VDAAE_LU_LOST) { esas2r_lun_event()
722 switch (ae->lu.bystate) { esas2r_lun_event()
738 memcpy(&t->lu_event, &ae->lu, cplen); esas2r_lun_event()
750 union atto_vda_ae *ae = esas2r_ae_complete() local
770 last = ae; esas2r_ae_complete()
773 while (ae < last) { esas2r_ae_complete()
776 esas2r_trace("ae: %p", ae); esas2r_ae_complete()
777 esas2r_trace("ae->hdr: %p", &(ae->hdr)); esas2r_ae_complete()
779 length = ae->hdr.bylength; esas2r_ae_complete()
781 if (length > (u32)((u8 *)last - (u8 *)ae) esas2r_ae_complete()
786 ae, length); esas2r_ae_complete()
788 esas2r_hdebug("ae->hdr.length (0x%x) invalid", length); esas2r_ae_complete()
794 esas2r_nuxi_ae_data(ae); esas2r_ae_complete()
796 esas2r_queue_fw_event(a, fw_event_vda_ae, ae, esas2r_ae_complete()
799 switch (ae->hdr.bytype) { esas2r_ae_complete()
802 if (ae->raid.dwflags & (VDAAE_GROUP_STATE esas2r_ae_complete()
808 ae->raid.acname, esas2r_ae_complete()
809 ae->raid.byrebuild_state, esas2r_ae_complete()
810 ae->raid.bygroup_state); esas2r_ae_complete()
818 ae->lu.dwevent, esas2r_ae_complete()
819 ae->lu.id.tgtlun.wtarget_id, esas2r_ae_complete()
820 ae->lu.id.tgtlun.bylun, esas2r_ae_complete()
821 ae->lu.bystate); esas2r_ae_complete()
823 target = ae->lu.id.tgtlun.wtarget_id; esas2r_ae_complete()
826 esas2r_lun_event(a, ae, target, length); esas2r_ae_complete()
843 ae = (union atto_vda_ae *)((u8 *)ae + length); esas2r_ae_complete()
854 struct atto_vda_ae_hdr ae; esas2r_send_reset_ae() local
857 ae.bytype = VDAAE_HDR_TYPE_PWRMGT; esas2r_send_reset_ae()
859 ae.bytype = VDAAE_HDR_TYPE_RESET; esas2r_send_reset_ae()
861 ae.byversion = VDAAE_HDR_VER_0; esas2r_send_reset_ae()
862 ae.byflags = 0; esas2r_send_reset_ae()
863 ae.bylength = (u8)sizeof(struct atto_vda_ae_hdr); esas2r_send_reset_ae()
870 esas2r_queue_fw_event(a, fw_event_vda_ae, &ae, esas2r_send_reset_ae()
H A Desas2r_main.c1512 void esas2r_nuxi_ae_data(union atto_vda_ae *ae) esas2r_nuxi_ae_data() argument
1514 struct atto_vda_ae_raid *r = &ae->raid; esas2r_nuxi_ae_data()
1515 struct atto_vda_ae_lu *l = &ae->lu; esas2r_nuxi_ae_data()
1517 switch (ae->hdr.bytype) { esas2r_nuxi_ae_data()
1772 struct esas2r_vda_ae *ae = (struct esas2r_vda_ae *)fw_event->data; esas2r_send_ae_event() local
1775 switch (ae->vda_ae.hdr.bytype) { esas2r_send_ae_event()
1844 esas2r_log_hexdump(ESAS2R_LOG_WARN, &ae->vda_ae, esas2r_send_ae_event()
1845 ae->vda_ae.hdr.bylength); esas2r_send_ae_event()
1904 struct esas2r_vda_ae *ae = esas2r_queue_fw_event() local
1907 ae->signature = ESAS2R_VDA_EVENT_SIG; esas2r_queue_fw_event()
1908 ae->bus_number = a->pcid->bus->number; esas2r_queue_fw_event()
1909 ae->devfn = a->pcid->devfn; esas2r_queue_fw_event()
1910 memcpy(&ae->vda_ae, data, sizeof(ae->vda_ae)); esas2r_queue_fw_event()
H A Desas2r_vda.c422 struct atto_vda_ae_req *vrq = &rq->vrq->ae; esas2r_build_ae_req()
H A Datvda.h1221 struct atto_vda_ae_req ae; member in union:atto_vda_req
H A Desas2r.h1099 void esas2r_nuxi_ae_data(union atto_vda_ae *ae);
/linux-4.1.27/security/selinux/
H A Davc.c54 struct avc_entry ae; member in struct:avc_node
290 node->ae.ssid = ssid; avc_node_populate()
291 node->ae.tsid = tsid; avc_node_populate()
292 node->ae.tclass = tclass; avc_node_populate()
293 memcpy(&node->ae.avd, avd, sizeof(node->ae.avd)); avc_node_populate()
305 if (ssid == node->ae.ssid && hlist_for_each_entry_rcu()
306 tclass == node->ae.tclass && hlist_for_each_entry_rcu()
307 tsid == node->ae.tsid) { hlist_for_each_entry_rcu()
403 if (pos->ae.ssid == ssid && hlist_for_each_entry()
404 pos->ae.tsid == tsid && hlist_for_each_entry()
405 pos->ae.tclass == tclass) { hlist_for_each_entry()
556 if (ssid == pos->ae.ssid && hlist_for_each_entry()
557 tsid == pos->ae.tsid && hlist_for_each_entry()
558 tclass == pos->ae.tclass && hlist_for_each_entry()
559 seqno == pos->ae.avd.seqno){ hlist_for_each_entry()
575 avc_node_populate(node, ssid, tsid, tclass, &orig->ae.avd);
579 node->ae.avd.allowed |= perms;
583 node->ae.avd.allowed &= ~perms;
586 node->ae.avd.auditallow |= perms;
589 node->ae.avd.auditallow &= ~perms;
592 node->ae.avd.auditdeny |= perms;
595 node->ae.avd.auditdeny &= ~perms;
730 memcpy(avd, &node->ae.avd, sizeof(*avd)); avc_has_perm_noaudit()
/linux-4.1.27/drivers/infiniband/hw/amso1100/
H A Dc2_ae.c172 resource_indicator = be32_to_cpu(wr->ae.ae_generic.resource_type); c2_ae_event()
174 (void *) (unsigned long) wr->ae.ae_generic.user_context; c2_ae_event()
200 (unsigned long long) wr->ae.ae_generic.user_context, c2_ae_event()
201 be32_to_cpu(wr->ae.ae_generic.resource_type), c2_ae_event()
202 be32_to_cpu(wr->ae.ae_generic.resource), c2_ae_event()
203 to_qp_state_str(be32_to_cpu(wr->ae.ae_generic.qp_state))); c2_ae_event()
205 c2_set_qp_state(qp, be32_to_cpu(wr->ae.ae_generic.qp_state)); c2_ae_event()
209 res = &wr->ae.ae_active_connect_results; c2_ae_event()
274 &wr->ae.ae_connection_request; c2_ae_event()
H A Dc2_wr.h1458 union c2wr_ae ae; member in union:c2wr
/linux-4.1.27/arch/powerpc/perf/
H A Dpower7-pmu.c163 s64 ae; power7_get_alternatives() local
170 ae = event_alternatives[i][j]; power7_get_alternatives()
171 if (ae && ae != event) power7_get_alternatives()
172 alt[nalt++] = ae; power7_get_alternatives()
175 ae = find_alternative_decode(event); power7_get_alternatives()
176 if (ae > 0) power7_get_alternatives()
177 alt[nalt++] = ae; power7_get_alternatives()
H A Dpower5+-pmu.c280 s64 ae; power5p_get_alternatives() local
288 ae = event_alternatives[i][j]; power5p_get_alternatives()
289 if (ae && ae != event) power5p_get_alternatives()
290 alt[nalt++] = ae; power5p_get_alternatives()
291 nlim += power5p_limited_pmc_event(ae); power5p_get_alternatives()
294 ae = find_alternative_bdecode(event); power5p_get_alternatives()
295 if (ae > 0) power5p_get_alternatives()
296 alt[nalt++] = ae; power5p_get_alternatives()
H A Dmpc7450-pmu.c229 u32 ae; mpc7450_get_alternatives() local
236 ae = event_alternatives[i][j]; mpc7450_get_alternatives()
237 if (ae && ae != (u32)event) mpc7450_get_alternatives()
238 alt[nalt++] = ae; mpc7450_get_alternatives()
H A Dpower5-pmu.c275 s64 ae; power5_get_alternatives() local
282 ae = event_alternatives[i][j]; power5_get_alternatives()
283 if (ae && ae != event) power5_get_alternatives()
284 alt[nalt++] = ae; power5_get_alternatives()
287 ae = find_alternative_bdecode(event); power5_get_alternatives()
288 if (ae > 0) power5_get_alternatives()
289 alt[nalt++] = ae; power5_get_alternatives()
/linux-4.1.27/tools/perf/tests/
H A Dkmod-path.c37 #define T(path, an, ae, k, c, n, e) \
38 TEST_ASSERT_VAL("failed", !test(path, an, ae, k, c, n, e))
/linux-4.1.27/arch/ia64/kernel/
H A Defi.c976 u64 as = 0, ae; find_memmap_space() local
1019 ae = min(contig_high, efi_md_end(md)); find_memmap_space()
1023 ae = min(ae, max_addr); find_memmap_space()
1024 if (ae <= as) find_memmap_space()
1028 if (total_mem + (ae - as) > mem_limit) find_memmap_space()
1029 ae -= total_mem + (ae - as) - mem_limit; find_memmap_space()
1031 if (ae <= as) find_memmap_space()
1034 if (ae - as > space_needed) find_memmap_space()
1053 u64 as, ae, lim; efi_memmap_init() local
1136 ae = contig_high; efi_memmap_init()
1138 ae = efi_md_end(md); efi_memmap_init()
1142 ae = min(ae, max_addr); efi_memmap_init()
1143 if (ae <= as) efi_memmap_init()
1147 if (total_mem + (ae - as) > mem_limit) efi_memmap_init()
1148 ae -= total_mem + (ae - as) - mem_limit; efi_memmap_init()
1150 if (ae <= as) efi_memmap_init()
1153 prev->num_pages += (ae - as) >> EFI_PAGE_SHIFT; efi_memmap_init()
1154 total_mem += ae - as; efi_memmap_init()
1159 k->num_pages = (ae - as) >> EFI_PAGE_SHIFT; efi_memmap_init()
1160 total_mem += ae - as; efi_memmap_init()
/linux-4.1.27/drivers/crypto/qat/qat_dh895xcc/
H A Dadf_admin.c67 uint32_t ae, void *in, void *out) adf_put_admin_msg_sync()
70 int offset = ae * ADF_ADMINMSG_LEN * 2; adf_put_admin_msg_sync()
72 int mb_offset = ae * ADF_DH895XCC_MAILBOX_STRIDE; adf_put_admin_msg_sync()
66 adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev, uint32_t ae, void *in, void *out) adf_put_admin_msg_sync() argument
H A Dadf_drv.h62 uint32_t ae, void *in, void *out);
H A Dadf_isr.c138 "qat%d-ae-cluster", accel_dev->accel_id); adf_request_irqs()
/linux-4.1.27/drivers/misc/mic/host/
H A Dmic_smpt.c103 int ae = 0; mic_smpt_op() local
115 ae++; mic_smpt_op()
117 } else if (ae) /* cannot find contiguous entries */ mic_smpt_op()
120 if (ae == entries) mic_smpt_op()
125 for (ae = 0, i = 0; i < smpt_info->info.num_reg; i++) { mic_smpt_op()
126 ae = (smpt_info->entry[i].ref_count == 0) ? ae + 1 : 0; mic_smpt_op()
127 if (ae == entries) mic_smpt_op()
/linux-4.1.27/arch/powerpc/crypto/
H A Daes-tab-4k.S55 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
133 .long R(47, ae, ae, e9), R(10, 08, 08, 18)
147 .long R(ae, 57, 57, f9), R(69, b9, b9, d0)
191 .long R(b1, 64, 77, e0), R(bb, 6b, ae, 84)
210 .long R(dd, 3e, 05, ae), R(4d, e6, bd, 46)
222 .long R(3d, ae, d5, 1e), R(36, 2d, 39, 27)
242 .long R(ae, f9, 32, 11), R(c7, 29, a1, 6d)
/linux-4.1.27/drivers/staging/lustre/lustre/obdclass/
H A Dacl.c304 ext_acl_xattr_entry *ee, ae; lustre_acl_xattr_merge2posix() local
318 lustre_ext_acl_le_to_cpu(&ae, lustre_acl_xattr_merge2posix()
320 switch (ae.e_tag) { lustre_acl_xattr_merge2posix()
324 if (ae.e_id != ACL_UNDEFINED_ID) { lustre_acl_xattr_merge2posix()
329 if (ae.e_stat != ES_DEL) { lustre_acl_xattr_merge2posix()
341 if (ae.e_stat == ES_DEL) lustre_acl_xattr_merge2posix()
/linux-4.1.27/drivers/net/wireless/rtlwifi/
H A Dpci.h113 #define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
114 #define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
/linux-4.1.27/drivers/power/
H A Dbq27x00_battery.c338 int ae; bq27x00_battery_read_energy() local
340 ae = bq27x00_read(di, BQ27x00_REG_AE, false); bq27x00_battery_read_energy()
341 if (ae < 0) { bq27x00_battery_read_energy()
343 return ae; bq27x00_battery_read_energy()
347 ae *= 1000; bq27x00_battery_read_energy()
349 ae = ae * 29200 / BQ27000_RS; bq27x00_battery_read_energy()
351 return ae; bq27x00_battery_read_energy()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/
H A Ddma.c728 u32 ae; dma64_dd_upd() local
730 ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; dma64_dd_upd()
733 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE; dma64_dd_upd()
798 u32 ae; _dma_ddtable_init() local
800 /* shift the high bit(s) from pa to ae */ _dma_ddtable_init()
801 ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; _dma_ddtable_init()
810 D64_XC_AE, (ae << D64_XC_AE_SHIFT)); _dma_ddtable_init()
817 D64_RC_AE, (ae << D64_RC_AE_SHIFT)); _dma_ddtable_init()
/linux-4.1.27/lib/
H A Dbch.c653 /* first, eliminate cX by using z=X+e with ae^2+c=0 */ find_poly_deg4_roots()
663 * z^4 + az^3 + (ae+b)z^2 + (ae^2+c)z+e^4+be^2+ae^3+ce+d find_poly_deg4_roots()
664 * z^4 + az^3 + (ae+b)z^2 + e^4+be^2+d find_poly_deg4_roots()
H A Dglob.c241 "1" "*ac*ae*ag*\0" "abacadaeafag\0"
/linux-4.1.27/net/mac80211/
H A Dmesh_hwmp.c33 static inline u32 u32_field_get(const u8 *preq_elem, int offset, bool ae) u32_field_get() argument
35 if (ae) u32_field_get()
40 static inline u16 u16_field_get(const u8 *preq_elem, int offset, bool ae) u16_field_get() argument
42 if (ae) u16_field_get()
H A Dmesh.c539 * @addr4or5: 1st address in the ae header, which may correspond to address 4
542 * @addr6: 2nd address in the ae header, which corresponds to addr6 of the
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Dsw.c432 MODULE_DESCRIPTION("Realtek 8821ae 802.11ac PCI wireless");
H A Ddm.c2528 "Trigger 8821ae Thermal Meter!!\n"); rtl8821ae_dm_check_txpower_tracking_thermalmeter()
H A Dhw.c3850 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only");*/ rtl8821ae_update_hal_rate_tbl()
/linux-4.1.27/arch/powerpc/include/asm/
H A Dsfp-machine.h233 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
/linux-4.1.27/scripts/
H A Dget_maintainer.pl104 'GitAuthor: %an <%ae>%n' .
113 'GitAuthor: %an <%ae>%n' .
122 'GitAuthor: %an <%ae>%n' .
/linux-4.1.27/drivers/scsi/csiostor/
H A Dcsio_lnode.c243 struct fc_fdmi_attr_entry *ae = (struct fc_fdmi_attr_entry *)*ptr; csio_append_attrib() local
244 ae->type = htons(type); csio_append_attrib()
247 ae->len = htons(len); csio_append_attrib()
248 memcpy(ae->value, val, len); csio_append_attrib()
/linux-4.1.27/drivers/scsi/ibmvscsi/
H A Dibmvfc.h547 enum ibmvfc_async_event ae; member in struct:ibmvfc_async_desc
H A Dibmvfc.c2586 * @ae: async event
2589 static const struct ibmvfc_async_desc *ibmvfc_get_ae_desc(u64 ae) ibmvfc_get_ae_desc() argument
2594 if (ae_desc[i].ae == ae) ibmvfc_get_ae_desc()
/linux-4.1.27/lib/mpi/
H A Dlonglong.h756 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
894 "ae %0,%3" \
/linux-4.1.27/net/wireless/
H A Dutil.c398 int ae = meshhdr->flags & MESH_FLAGS_AE; ieee80211_get_mesh_hdrlen() local
400 switch (ae) { ieee80211_get_mesh_hdrlen()
/linux-4.1.27/drivers/infiniband/hw/nes/
H A Dnes_verbs.c3163 " need ae to finish up, original_last_aeq = 0x%04X." nes_modify_qp()
3173 " need ae to finish up, original_last_aeq = 0x%04X." nes_modify_qp()
3180 nes_debug(NES_DBG_MOD_QP, "QP%u Decrementing QP refcount (%d), No ae to finish up," nes_modify_qp()
3186 nes_debug(NES_DBG_MOD_QP, "QP%u Decrementing QP refcount (%d), No ae to finish up," nes_modify_qp()
H A Dnes_hw.c3608 " need ae to finish up, original_last_aeq = 0x%04X." nes_process_iwarp_aeqe()
/linux-4.1.27/arch/x86/kernel/
H A Duprobes.c206 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
/linux-4.1.27/include/linux/
H A Dphy.h145 IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
/linux-4.1.27/drivers/scsi/
H A Dconstants.c93 /* aa-ae */ "Write(12)", NULL, "Erase(12), Get Performance",
/linux-4.1.27/drivers/staging/speakup/
H A Dmain.c185 /*230*/ "ae", "c cidella", "e grave", "e acute",
/linux-4.1.27/arch/s390/kernel/
H A Ddis.c639 { "ae", 0x7a, INSTR_RX_FRRD },
/linux-4.1.27/arch/powerpc/xmon/
H A Dppc-opc.c3543 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3545 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
/linux-4.1.27/drivers/media/usb/gspca/
H A Dzc3xx.c5036 {0xa0, 0xae, ZC3XX_R191_EXPOSURELIMITMID}, /* 01,91,ae,cc */

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