Searched refs:VF610_CLK_PLL4_MAIN_DIV (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dvf610-clock.h43 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dvf610-clock.h43 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dvf610-clock.h43 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dvf610-clock.h43 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dvf610-clock.h43 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dvf610-clock.h43 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-vf610.c232 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); vf610_clocks_init()

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