Searched refs:TSC (Results 1 - 101 of 101) sorted by relevance

/linux-4.1.27/arch/x86/kernel/
H A Dtsc_sync.c2 * check TSC synchronization.
6 * We check whether all boot CPUs have their TSC's synchronized,
7 * print a warning if not and turn off the TSC clock-source.
33 * of a critical section, to be able to prove TSC time-warps:
42 * TSC-warp measurement loop running on both CPUs:
60 * We take the global lock, measure TSC, save the check_tsc_warp()
61 * previous TSC that was measured (possibly on check_tsc_warp()
62 * another CPU) and update the previous TSC timestamp. check_tsc_warp()
76 * TSC readout is totally broken]): check_tsc_warp()
86 * we saw a time-warp of the TSC going backwards: check_tsc_warp()
102 * online, a timeout of 20msec will be used for the TSC-warp measurement
107 * Ideally we should be able to skip the TSC sync check on the other
109 * But as the TSC is per-logical CPU and can potentially be modified wrongly
110 * by the bios, TSC sync test for smaller duration should be able
128 * No need to check if we already know that the TSC is not check_tsc_sync_source()
137 "Skipped synchronization checks as TSC is reliable.\n"); check_tsc_sync_source()
162 pr_warning("TSC synchronization [CPU#%d -> CPU#%d]:\n", check_tsc_sync_source()
164 pr_warning("Measured %Ld cycles TSC warp between CPUs, " check_tsc_sync_source()
165 "turning off TSC clock.\n", max_warp); check_tsc_sync_source()
168 pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n", check_tsc_sync_source()
H A Dtsc_msr.c2 * tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms.
4 * TSC in Intel Atom SoC runs at a constant rate which can be figured
114 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ try_msr_calibrate_tsc()
116 pr_info("TSC runs at %lu KHz\n", res); try_msr_calibrate_tsc()
125 pr_warn("Fast TSC calibration using MSR failed\n"); try_msr_calibrate_tsc()
H A Dtsc.c26 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
33 * TSC can be unstable due to cpufreq or due to unsynced TSCs
38 we must start with the TSC soft disabled to prevent
59 * (assuming the TSC was that to begin with), because while we compute the
281 * Fall back to jiffies if there's no TSC available: native_sched_clock()
282 * ( But note that we still use it if the TSC is marked native_sched_clock()
333 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); notsc_setup()
339 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
368 * Read TSC and the reference counters. Take care of SMI disturbance
389 * Calculate the TSC frequency from HPET reference
406 * Calculate the TSC frequency from PMTimer reference
435 * Try to calibrate the TSC against the Programmable
436 * Interrupt Timer and return the frequency of the TSC
509 * see the same MSB (and overhead like doing a single TSC
525 * use the TSC value at the transitions to calculate a pretty
526 * good value for the TSC frequencty.
551 * will be based on the error terms on the TSC values. pit_expect_msb()
611 * all TSC reads were stable wrt the PIT. quick_pit_calibrate()
621 pr_info("Fast TSC calibration failed\n"); quick_pit_calibrate()
631 * any odd delays anywhere, and the TSC reads are quick_pit_calibrate()
640 pr_info("Fast TSC calibration using PIT\n"); quick_pit_calibrate()
654 /* Calibrate TSC using MSR for Intel Atom SoCs */ native_calibrate_tsc()
675 * zero. In each wait loop iteration we read the TSC and check native_calibrate_tsc()
685 * We use separate TSC readouts and check inside of the native_calibrate_tsc()
712 /* Pick the lowest PIT TSC calibration so far */ native_calibrate_tsc()
767 /* We don't have an alternative source, disable TSC */ native_calibrate_tsc()
773 /* The alternative source failed as well, disable TSC */ native_calibrate_tsc()
842 * Even on processors with invariant TSC, TSC gets reset in some the
843 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
881 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
954 * We used to compare the TSC to the cycle_last value in the clocksource
957 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
958 * is smaller than the cycle_last reference value due to a TSC which
993 pr_info("Marking TSC unstable due to %s\n", reason); mark_tsc_unstable()
1015 /* Geode_LX - the OLPC CPU has a very reliable TSC */ check_system_tsc_reliable()
1025 * Make an educated guess if the TSC is trustworthy and synchronized
1045 * Exceptions must mark TSC as unstable: unsynchronized_tsc()
1064 * second to further refine the TSC freq value. Since this is
1080 /* Don't bother refining TSC on unstable systems */ tsc_refine_calibration_work()
1122 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", tsc_refine_calibration_work()
1149 * exporting a reliable TSC. init_tsc_clocksource()
1181 mark_tsc_unstable("could not calculate TSC khz"); tsc_init()
1226 * If we have a constant TSC and are using the TSC for the delay loop,
H A Dtime.c91 * Initialize TSC and delay the periodic timer init to
H A Dapb_timer.c273 * We don't know the TSC frequency yet, but waiting for apbt_clocksource_register()
274 * 200000 TSC cycles is safe: apbt_clocksource_register()
408 "APBT TSC calibration failed, not enough resolution\n"); apbt_quick_calibrate()
413 printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); apbt_quick_calibrate()
H A Dprocess.c385 * way as C3 power states (local apic timer and TSC stop)
397 mark_tsc_unstable("TSC halt in AMD C1E"); amd_e400_idle()
H A Dhpet.c767 * We don't know the TSC frequency yet, but waiting for hpet_clocksource_register()
768 * 200000 TSC cycles is safe: hpet_clocksource_register()
H A Dsmpboot.c238 * Check TSC synchronization with the BP: start_secondary()
971 * Check TSC synchronization with the AP (keep irqs disabled native_cpu_up()
/linux-4.1.27/tools/power/cpupower/utils/idle_monitor/
H A Dmperf_monitor.c64 * 1) calculated after measurements if we know TSC ticks at mperf/P0 frequency
85 dprint("Reading TSC MSR failed, returning %llu\n", *tsc); mperf_get_tsc()
135 dprint("%s: TSC Ref - mperf_diff: %llu, tsc_diff: %llu\n", mperf_get_count_percent()
169 /* Calculate max_freq from TSC count */ mperf_get_count_freq()
178 (max_freq_mode == MAX_FREQ_TSC_REF) ? "TSC calculated" : "sysfs read"); mperf_get_count_freq()
198 dprint("TSC diff: %llu\n", dbg - tsc_at_measure_start); mperf_start()
214 dprint("TSC diff: %llu\n", dbg - tsc_at_measure_end); mperf_stop()
223 * we use TSC counter if it reliably ticks at P0/mperf frequency.
227 * on older Intel HW without invariant TSC feature.
228 * Or on AMD machines where TSC does not tick at P0 (do not exist yet, but
244 /* MSR_AMD_HWCR tells us whether TSC runs at P0/mperf init_maxfreq_mode()
257 * not explicitly provide access to it and assume TSC works init_maxfreq_mode()
260 dprint("TSC read 0x%x failed - assume TSC working\n", init_maxfreq_mode()
270 * rate than TSC init_maxfreq_mode()
335 .overflow_s = 922000000 /* 922337203 seconds TSC overflow
H A Dnhm_idle.c28 enum intel_nhm_id { C3 = 0, C6, PC3, PC6, TSC = 0xFFFF }; enumerator in enum:intel_nhm_id
90 case TSC: nhm_get_count()
132 nhm_get_count(TSC, &tsc_at_measure_start, 0); nhm_start()
140 nhm_get_count(TSC, &dbg, 0); nhm_start()
141 dprint("TSC diff: %llu\n", dbg - tsc_at_measure_start); nhm_start()
151 nhm_get_count(TSC, &tsc_at_measure_end, 0); nhm_stop()
159 nhm_get_count(TSC, &dbg, 0); nhm_stop()
160 dprint("TSC diff: %llu\n", dbg - tsc_at_measure_end); nhm_stop()
213 .overflow_s = 922000000 /* 922337203 seconds TSC overflow
H A Dhsw_ext_idle.c27 TSC = 0xFFFF }; enumerator in enum:intel_hsw_ext_id
79 case TSC: hsw_ext_get_count()
126 hsw_ext_get_count(TSC, &tsc_at_measure_start, 0); hsw_ext_start()
135 hsw_ext_get_count(TSC, &tsc_at_measure_end, 0); hsw_ext_stop()
193 .overflow_s = 922000000 /* 922337203 seconds TSC overflow
H A Dsnb_idle.c25 enum intel_snb_id { C7 = 0, PC2, PC7, SNB_CSTATE_COUNT, TSC = 0xFFFF }; enumerator in enum:intel_snb_id
76 case TSC: snb_get_count()
123 snb_get_count(TSC, &tsc_at_measure_start, 0); snb_start()
132 snb_get_count(TSC, &tsc_at_measure_end, 0); snb_stop()
197 .overflow_s = 922000000 /* 922337203 seconds TSC overflow
/linux-4.1.27/arch/x86/include/asm/
H A Dtsc.h2 * x86 TSC related functions
38 * We only do VDSOs on TSC capable CPUs, so this shouldn't vget_cycles()
68 /* MSR based TSC calibration for Intel Atom SoC platforms */
H A Dmach_timer.h5 /* ------ Calibrate the TSC -------
6 * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
H A Dmodule.h13 #define MODULE_PROC_FAMILY "586TSC "
H A Dstackprotector.h67 * We both use the random pool and the current TSC as a source boot_init_stack_canary()
68 * of randomness. The TSC only matters for very early init, boot_init_stack_canary()
H A Dbarrier.h96 * (or get_cycles or vread that possibly accesses the TSC) in a defined
H A Dcpufeature.h86 #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
101 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
102 #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
108 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
210 #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
221 #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
H A Dx86_init.h86 * @tsc_pre_init: platform function called before TSC init
149 * @calibrate_tsc: calibrate TSC
H A Dthread_info.h100 #define TIF_NOTSC 16 /* TSC is not accessible in userland */
/linux-4.1.27/arch/x86/kernel/cpu/
H A Dvmware.c65 printk(KERN_INFO "TSC freq read from hypervisor : %lu.%03lu MHz\n", vmware_get_tsc_khz()
88 "Failed to get TSC freq from the hypervisor\n"); vmware_platform_setup()
114 * VMware hypervisor takes care of exporting a reliable TSC to the guest.
115 * Still, due to timing difference when running on virtual cpus, the TSC can
116 * be marked as unstable in some cases. For example, the TSC sync check at
123 * reliable virtual TSC that is suitable for timekeeping.
H A Dbugs.c78 * - In order to run on anything without a TSC, we need to be check_bugs()
H A Dtransmeta.c88 /* All Transmeta CPUs have a constant TSC */ init_transmeta()
H A Dcentaur.c133 printk(KERN_NOTICE "Disabling bugged TSC.\n"); init_centaur()
H A Damd.c477 printk(KERN_WARNING FW_BUG "TSC doesn't count " bsp_init_amd()
503 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate early_init_amd()
H A Dintel.c82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate early_init_intel()
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ early_init_intel()
/linux-4.1.27/drivers/input/touchscreen/
H A Dtsc40.c2 * TSC-40 serial touchscreen driver. It should be compatible with
3 * TSC-10 and 25.
97 input_dev->name = "TSC-10/25/40 Serial TouchScreen"; tsc_connect()
155 #define DRIVER_DESC "TSC-10/25/40 serial touchscreen driver"
H A Dlpc32xx_ts.c153 /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */ lpc32xx_setup_tsc()
240 dev_err(&pdev->dev, "TSC registers are not free\n"); lpc32xx_ts_probe()
341 * avoid calling the TSC stop and start functions as the TSC lpc32xx_ts_suspend()
406 MODULE_DESCRIPTION("LPC32XX TSC Driver");
H A Dtps6507x-ts.c79 dev_err(tsc->dev, "TSC mode read failed\n"); tps6507x_adc_conversion()
117 dev_dbg(tsc->dev, "TSC channel %d = 0x%X\n", tsc_mode, *value); tps6507x_adc_conversion()
H A Dusbtouchscreen.c11 * - DMC TSC-10/25
43 * - DMC TSC 10/25 are from Holger Schurig, with ideas from an unmerged
586 * DMC TSC-10/25 Part
630 /* TSC-25 data sheet specifies a delay after the RESET command */ dmc_tsc10_init()
H A Dstmpe-ts.c141 * the manufacture. As a workaround we disable the TSC while we are stmpe_ts_handler()
H A Dti_am335x_tsc.c78 * Get the order in which TSC wires are attached titsc_config_wires()
/linux-4.1.27/arch/mn10300/kernel/
H A Dcsrc-mn10300.c22 .name = "TSC",
H A Dtime.c57 /* scale the 64-bit TSC value to a nanosecond value via a 96-bit sched_clock()
H A Drtc.c118 * calibrate the TSC clock against the RTC
/linux-4.1.27/net/mac80211/
H A Devent.c14 * Indicate a failed Michael MIC to userspace. If the caller knows the TSC of
H A Dkey.h71 /* last used TSC */
H A Dtkip.c78 * P1K := Phase1(TA, TK, TSC)
81 * TSC = TKIP sequence counter (48 bits, only 32 msb bits used)
/linux-4.1.27/arch/x86/platform/intel-mid/
H A Dmrfl.c25 /* Compute TSC:Ratio * FSB */ tangier_calibrate_tsc()
69 /* TSC = FSB Freq * Resolved HFM Ratio */ tangier_calibrate_tsc()
/linux-4.1.27/tools/perf/tests/
H A Dperf-time-to-tsc.c29 * test__perf_time_to_tsc - test converting perf time to TSC.
32 * to and from TSC is consistent with the order of events. If the test passes
33 * %0 is returned, otherwise %-1 is returned. If TSC conversion is not
H A Dbuiltin-test.c109 .desc = "Test converting perf time to TSC",
/linux-4.1.27/tools/power/cpupower/debug/kernel/
H A Dcpufreq-test_tsc.c2 * test module to check whether the TSC-based delay routine continues
19 * TSC-based delay routine on the Linux kernel does not correctly
109 MODULE_DESCRIPTION("Verify the TSC cpufreq notifier working correctly -- needs ACPI-enabled system");
/linux-4.1.27/drivers/clocksource/
H A Dscx200_hrt.c6 * time stamp counter (TSC), which loses time unless 'idle=poll' is
8 * will detect and de-rate the bad TSC, allowing this timer to take
/linux-4.1.27/arch/x86/lib/
H A Ddelay.c49 /* TSC based delay: */ delay_tsc()
72 * since TSC's are per-cpu we need to calculate delay_tsc()
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Dhyperv.h31 /* A partition's reference time stamp counter (TSC) page */
37 * well as the TSC frequency.
43 /* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
155 /* MSR used to retrieve the TSC frequency */
H A Dmsr-index.h15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
/linux-4.1.27/arch/x86/um/asm/
H A Dbarrier.h49 * (or get_cycles or vread that possibly accesses the TSC) in a defined
/linux-4.1.27/include/trace/events/
H A Dmce.h53 TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, ADDR/MISC: %016Lx/%016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PROCESSOR: %u:%x, TIME: %llu, SOCKET: %u, APIC: %x",
/linux-4.1.27/Documentation/prctl/
H A Ddisable-tsc-ctxt-sw-stress-test.c27 # define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
H A Ddisable-tsc-on-off-stress-test.c27 # define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
H A Ddisable-tsc-test.c22 # define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
/linux-4.1.27/drivers/acpi/
H A Dacpi_pad.c78 * AMD Fam10h TSC will tick in all power_saving_mwait_init()
85 /* TSC could halt in idle */ power_saving_mwait_init()
170 /* TSC could halt in idle, so notify users */ power_saving_thread()
171 mark_tsc_unstable("TSC halts in idle"); power_saving_thread()
H A Dprocessor_idle.c244 * AMD Fam10h TSC will tick in all tsc_check_state()
252 /* TSC could halt in idle, so notify users */ tsc_check_state()
254 mark_tsc_unstable("TSC halts in idle"); tsc_check_state()
/linux-4.1.27/include/linux/
H A Dlguest.h60 /* KHz for the TSC clock. */
/linux-4.1.27/drivers/mfd/
H A Dti_am335x_tscadc.c229 dev_err(&pdev->dev, "failed to get TSC fck\n"); ti_tscadc_probe()
255 /* Enable the TSC module enable bit */ ti_tscadc_probe()
263 /* TSC Cell */ ti_tscadc_probe()
H A Dmax8925-core.c491 /* TSC IRQ should be serviced in max8925_tsc_irq() */ max8925_irq()
520 /* non TSC IRQ should be serviced in max8925_irq() */ max8925_tsc_irq()
681 /* mask all interrupts except for TSC */ max8925_irq_init()
715 /* mask TSC interrupt */ max8925_irq_init()
719 dev_warn(chip->dev, "No interrupt support on TSC IRQ\n"); max8925_irq_init()
726 dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret); max8925_irq_init()
/linux-4.1.27/drivers/staging/rtl8192e/
H A Drtllib_crypt_tkip.c230 /* Initialize the 80-bit TTAK from TSC (IV32) and TA[0..5] */ tkip_mixing_phase1()
256 /* Step 1 - make copy of TTAK and bring in TSC */ tkip_mixing_phase2()
435 "TKIP: replay detected: STA= %pM previous TSC %08x%04x received TSC %08x%04x\n", rtllib_tkip_decrypt()
593 /* TODO: needed parameters: count, keyid, key type, TSC */ rtllib_michael_mic_failure()
645 /* Update TSC counters for RX now that the packet verification has rtllib_michael_mic_verify()
677 tkey->tx_iv16 = 1; /* TSC is initialized to 1 */ rtllib_tkip_set_key()
/linux-4.1.27/drivers/staging/rtl8192u/ieee80211/
H A Dieee80211_crypt_tkip.c239 /* Initialize the 80-bit TTAK from TSC (IV32) and TA[0..5] */ tkip_mixing_phase1()
264 /* Step 1 - make copy of TTAK and bring in TSC */ tkip_mixing_phase2()
438 " previous TSC %08x%04x received TSC " ieee80211_tkip_decrypt()
594 /* TODO: needed parameters: count, keyid, key type, TSC */ ieee80211_michael_mic_failure()
644 /* Update TSC counters for RX now that the packet verification has ieee80211_michael_mic_verify()
675 tkey->tx_iv16 = 1; /* TSC is initialized to 1 */ ieee80211_tkip_set_key()
/linux-4.1.27/net/wireless/
H A Dlib80211_crypt_tkip.c246 /* Initialize the 80-bit TTAK from TSC (IV32) and TA[0..5] */ tkip_mixing_phase1()
270 /* Step 1 - make copy of TTAK and bring in TSC */ tkip_mixing_phase2()
452 net_dbg_ratelimited("TKIP: replay detected: STA=%pM previous TSC %08x%04x received TSC %08x%04x\n", lib80211_tkip_decrypt()
594 /* TODO: needed parameters: count, keyid, key type, TSC */ lib80211_michael_mic_failure()
634 /* Update TSC counters for RX now that the packet verification has lib80211_michael_mic_verify()
663 tkey->tx_iv16 = 1; /* TSC is initialized to 1 */ lib80211_tkip_set_key()
/linux-4.1.27/drivers/thermal/
H A Drcar_thermal.c2 * R-Car THS/TSC thermal sensor driver
154 * TSC decides a value of CPTAP automatically, rcar_thermal_update_temp()
512 MODULE_DESCRIPTION("R-Car THS/TSC thermal sensor driver");
/linux-4.1.27/tools/power/cpupower/utils/helpers/
H A Dcpuid.c117 /* Invariant TSC */ get_cpu_info()
/linux-4.1.27/arch/x86/kvm/
H A Dx86.c1225 /* tsc_khz can be zero if TSC calibration fails */ kvm_set_tsc_khz()
1229 /* Compute a scale to convert nanoseconds in TSC cycles */ kvm_set_tsc_khz()
1236 * Compute the variation in TSC rate which is acceptable kvm_set_tsc_khz()
1244 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); kvm_set_tsc_khz()
1273 * In order to enable masterclock, the host clocksource must be TSC kvm_track_tsc_matching()
1341 usdiff = USEC_PER_SEC; /* disable TSC match window below */ kvm_write_tsc()
1344 * Special case: TSC write with a small delta (1 second) of virtual kvm_write_tsc()
1348 * For a reliable TSC, we can match TSC offsets, and for an unstable kvm_write_tsc()
1349 * TSC, we add elapsed time in this computation. We could let the kvm_write_tsc()
1368 * We split periods of matched TSC writes into generations. kvm_write_tsc()
1496 * Assuming a stable TSC across physical CPUS, and a stable TSC
1523 * might be smaller then the difference between corresponding TSC reads,
1546 * If the host uses TSC clock, then passthrough TSC as stable pvclock_update_vm_gtod_copy()
1604 * If the host uses TSC clock, then passthrough TSC as stable kvm_guest_time_update()
1631 * We may have to catch up the TSC to match elapsed wall clock kvm_guest_time_update()
1633 * 1) CPU could have been running below the maximum TSC rate kvm_guest_time_update()
1634 * 2) Broken TSC compensation resets the base at each VCPU kvm_guest_time_update()
1635 * entry to avoid unknown leaps of TSC even when running kvm_guest_time_update()
1700 /* If the host uses TSC clocksource, then it is stable */ kvm_guest_time_update()
2594 /* TSC increment by tick */ kvm_get_msr_common()
2935 /* Apply any externally detected TSC adjustments (due to suspend) */ kvm_arch_vcpu_load()
2946 mark_tsc_unstable("KVM discovered backwards TSC"); kvm_arch_vcpu_load()
2954 * On a host with synchronized TSC, there is no need to update kvm_arch_vcpu_load()
5548 * Changing the TSC frequency at arbitrary points in time kvmclock_cpufreq_notifier()
5550 * the TSC for each VCPU. We must flag these local variables kvmclock_cpufreq_notifier()
5570 * correct TSC value must be set before the request. However, kvmclock_cpufreq_notifier()
5775 * use, TSC clocksource pvclock_gtod_notify()
7086 "kvm: SMP vm created on host with unstable TSC; " kvm_arch_vcpu_create()
7087 "guest TSC will not be reliable\n"); kvm_arch_vcpu_create()
7223 * platforms that reset TSC during suspend or hibernate actions, but
7232 * So we simply find the maximum observed TSC above, then record the
7233 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7238 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7242 * much faster than a first, causing the observed TSC here to be
7246 * N.B. - this code below runs only on platforms with reliable TSC,
7255 * will be compensated by the logic in vcpu_load, which sets the TSC to
7270 * We have to disable TSC offset matching.. if you were
H A Dcpuid.c302 F(TSC) | F(MSR) | F(PAE) | F(MCE) | __do_cpuid_ent()
312 F(TSC) | F(MSR) | F(PAE) | F(MCE) | __do_cpuid_ent()
559 /* invariant TSC is CPUID.80000007H:EDX[8] */ __do_cpuid_ent()
H A Dsvm.c215 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
1001 /* Guest TSC same frequency as host TSC? */ svm_set_tsc_khz()
1007 /* TSC scaling supported? */ svm_set_tsc_khz()
1013 WARN(1, "user requested TSC rate below hardware speed\n"); svm_set_tsc_khz()
1019 /* TSC scaling required - calculate ratio */ svm_set_tsc_khz()
1024 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n", svm_set_tsc_khz()
H A Dvmx.c131 * Time is measured based on a counter that runs at the same rate as the TSC,
2277 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2289 WARN(1, "user requested TSC rate below hardware speed\n"); vmx_set_tsc_khz()
2304 * We're here if L1 chose not to trap WRMSR to TSC. According vmx_write_tsc_offset()
2305 * to the spec, this should set L1's TSC; The offset that L1 vmx_write_tsc_offset()
2307 * to the newly set TSC to get L2's TSC. vmx_write_tsc_offset()
10056 /* Update TSC_OFFSET if TSC was changed while L2 ran */ nested_vmx_vmexit()
H A Dlapic.c1167 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ wait_lapic_expire()
/linux-4.1.27/drivers/char/
H A Dhangcheck-timer.c26 * The hangcheck-timer driver uses the TSC to catch delays that
/linux-4.1.27/include/uapi/linux/
H A Dprctl.h77 # define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
H A Dperf_event.h496 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
H A Dnl80211.h435 * %NL80211_ATTR_KEY_SEQ to indicate the TSC value of the frame; this
/linux-4.1.27/arch/arm64/include/asm/
H A Dkvm_arm.h66 * TSC: Trap SMC
/linux-4.1.27/include/linux/mfd/
H A Dmax8925.h232 * tsc_irq: stores IRQ number of MAX8925 TSC
/linux-4.1.27/kernel/sched/
H A Dclock.c52 * that is otherwise invisible (TSC gets stopped).
193 * - use the GTOD tick value to create a window to filter crazy TSC values
H A Dfair.c2534 * unfortunately does during sched clock init when we swap over to TSC. __update_entity_runnable_avg()
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
H A Dfw-api-sta.h235 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
324 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
H A Dd3.c322 * firmware only supports TSC/RSC for a single key, iwl_mvm_wowlan_program_keys()
/linux-4.1.27/arch/x86/xen/
H A Dtime.c146 /* Get the TSC speed from Xen */ xen_tsc_khz()
482 /* As Dom0 is never moved, no penalty on using TSC there */ xen_time_init()
/linux-4.1.27/drivers/cpufreq/
H A Dlongrun.c203 /* set the upper border to the value determined during TSC init */ longrun_determine_freqs()
H A Dp4-clockmod.c150 /* on P-4s, the TSC runs with constant frequency independent whether cpufreq_p4_get_frequency()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv50.c63 { 0x00000002, "TSC", NULL },
/linux-4.1.27/init/
H A Dcalibrate.c99 "timer_rate as we had a TSC wrap around" calibrate_delay_direct()
/linux-4.1.27/arch/arm/include/asm/
H A Dkvm_arm.h57 * TSC: Trap SMC
/linux-4.1.27/tools/power/x86/turbostat/
H A Dturbostat.c395 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); dump_counters()
724 /* check for TSC < 1 Mcycles over interval */ delta_thread()
726 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" delta_thread()
764 * to exceed TSC's all cycles: show c1 = 0% in that case. delta_thread()
2602 * This is needed to check for invariant TSC. process_cpuid()
2611 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 process_cpuid()
2641 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz process_cpuid()
2665 fprintf(stderr, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", process_cpuid()
/linux-4.1.27/drivers/input/joystick/
H A Danalog.c148 #define TIME_NAME (cpu_has_tsc?"TSC":"PIT") get_time_pit()
165 #define TIME_NAME "TSC"
/linux-4.1.27/drivers/lguest/
H A Dhypercalls.c299 * initial boot and as a rough time source if the TSC isn't available.
/linux-4.1.27/arch/arm/plat-samsung/
H A Dadc.c123 adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n", s3c_adc_dbgshow()
/linux-4.1.27/arch/x86/kernel/apic/
H A Dapic.c340 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, __setup_APIC_LVTT()
346 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); __setup_APIC_LVTT()
665 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " calibrate_by_pmtimer()
2443 * apic_is_clustered_box() -- Check if we can expect good TSC
2446 * Clustered boxes may have unsynced TSC problems if they are
/linux-4.1.27/arch/x86/lguest/
H A Dboot.c442 * DX: SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, TSC, FPU and PAE. lguest_cpuid()
913 * The TSC is an Intel thing called the Time Stamp Counter. The Host tells us
916 * TSC clock will give up and not register itself.
924 * If we can't use the TSC, the kernel falls back to our lower-priority
957 /* This is the fallback clocksource: lower priority than the TSC clocksource. */
/linux-4.1.27/drivers/iio/adc/
H A Dti_am335x_adc.c129 * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only tiadc_irq_h()
/linux-4.1.27/drivers/net/wireless/
H A Dadm8211.h63 __le32 TSC; /* 0xC0 CSR32 */ member in struct:adm8211_csr
/linux-4.1.27/drivers/lguest/x86/
H A Dcore.c674 * cpu frequency. Some devious chip manufacturers decided that TSC lguest_arch_init_hypercalls()
678 * We also insist that the TSC be stable: the kernel detects unreliable lguest_arch_init_hypercalls()
/linux-4.1.27/drivers/idle/
H A Dintel_idle.c990 mark_tsc_unstable("TSC halts in idle" intel_idle_cpuidle_driver_init()
/linux-4.1.27/drivers/net/wireless/ath/ath6kl/
H A Dwmi.h771 * Bit 0 - Initialise TSC - default is Initialize
776 /* default initialise the TSC & RSC */
H A Dmain.c688 memset(tsc, 0, sizeof(tsc)); /* FIX: get correct TSC */ ath6kl_tkip_micerr_event()
/linux-4.1.27/include/xen/interface/
H A Dxen.h490 uint64_t tsc_timestamp; /* TSC at last update of time vals. */
/linux-4.1.27/drivers/edac/
H A Dsb_edac.c2203 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); sbridge_mce_check_error()
/linux-4.1.27/arch/x86/kernel/cpu/mcheck/
H A Dmce.c264 pr_emerg(HW_ERR "TSC %llx ", m->tsc); print_mce()
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
H A Dcommands.h844 u8 tkip_rx_tsc_byte2; /* TSC[2] for key mix ph1 detection */
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A Dcommands.h901 u8 tkip_rx_tsc_byte2; /* TSC[2] for key mix ph1 detection */
/linux-4.1.27/kernel/trace/
H A Dtrace.c3676 " x86-tsc: TSC cycle counter\n"
/linux-4.1.27/include/net/
H A Dcfg80211.h4193 * @tsc: The TSC value of the frame that generated the MIC failure (6 octets)

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