Searched refs:TEGRA30_CLK_PLL_D_OUT0 (Results 1 - 7 of 7) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h211 #define TEGRA30_CLK_PLL_D_OUT0 187 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h211 #define TEGRA30_CLK_PLL_D_OUT0 187 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h211 #define TEGRA30_CLK_PLL_D_OUT0 187 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h211 #define TEGRA30_CLK_PLL_D_OUT0 187 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dtegra30-car.h211 #define TEGRA30_CLK_PLL_D_OUT0 187 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dtegra30-car.h211 #define TEGRA30_CLK_PLL_D_OUT0 187 macro
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-tegra30.c604 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
981 clks[TEGRA30_CLK_PLL_D_OUT0] = clk; tegra30_pll_init()

Completed in 69 milliseconds