Searched refs:SYSC_REG_CPLL_CONFIG0 (Results 1 - 2 of 2) sorted by relevance

/linux-4.1.27/arch/mips/include/asm/mach-ralink/
H A Dmt7620.h32 #define SYSC_REG_CPLL_CONFIG0 0x54 macro
/linux-4.1.27/arch/mips/ralink/
H A Dmt7620.c277 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); mt7620_get_cpu_pll_rate()

Completed in 36 milliseconds