Searched refs:SPI0_CLK (Results 1 – 4 of 4) sorted by relevance
185 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */485 0x1d4 0 /* SPI0_CLK (IOCFG125) */
532 MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false)
1293 #define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */ macro
127 #define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)128 #define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)