Searched refs:SOR_REFCLK_DIV_INT (Results 1 – 2 of 2) sorted by relevance
408 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8) macro
910 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); in tegra_hdmi_encoder_mode_set()