Searched refs:PLL1 (Results 1 - 55 of 55) sorted by relevance

/linux-4.1.27/include/linux/iio/frequency/
H A Dad9523.h118 * @refa_r_div: PLL1 10-bit REFA R divider.
119 * @refb_r_div: PLL1 10-bit REFB R divider.
120 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
121 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
123 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
125 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
161 /* PLL1 Setting */
/linux-4.1.27/arch/arm/mach-w90x900/
H A Dclksel.c28 #define PLL1 0x01 macro
80 clkval = PLL1; nuc900_clock_source()
/linux-4.1.27/arch/sh/boards/mach-hp6xx/
H A Dpm.c56 /* disable PLL1 */ pm_enter()
86 /* enable PLL1 */ pm_enter()
/linux-4.1.27/sound/soc/codecs/
H A Dak4642.c117 #define PLL1 (1 << 5) macro
119 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
355 pll = PLL2 | PLL1; ak4642_dai_set_sysclk()
358 pll = PLL2 | PLL1 | PLL0; ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1; ak4642_dai_set_sysclk()
375 pll = PLL3 | PLL2 | PLL1 | PLL0; ak4642_dai_set_sysclk()
H A Dadav80x.c207 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
221 clk = "PLL1"; adav80x_dapm_sysclk_check()
270 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
273 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
605 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1"); adav80x_set_sysclk()
607 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1"); adav80x_set_sysclk()
807 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL1"); adav80x_probe()
H A Drt5640.c1054 SND_SOC_DAPM_SUPPLY("PLL1", RT5640_PWR_ANLG2,
1379 {"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll},
1384 {"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll},
1389 {"Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll},
1394 {"Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll},
1462 {"DAC L1", NULL, "PLL1", is_sys_clk_from_pll},
1464 {"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
1569 {"DAC L2", NULL, "PLL1", is_sys_clk_from_pll},
1571 {"DAC R2", NULL, "PLL1", is_sys_clk_from_pll},
H A Drt5631.c867 /* PLL1 */
868 SND_SOC_DAPM_SUPPLY("PLL1", RT5631_PWR_MANAG_ADD2,
1081 {"Left ADC", NULL, "PLL1", check_sysclk1_source},
1087 {"Right ADC", NULL, "PLL1", check_sysclk1_source},
1095 {"Left DAC", NULL, "PLL1", check_sysclk1_source},
1098 {"Right DAC", NULL, "PLL1", check_sysclk1_source},
H A Dalc5632.c65 { 68, 0x0000 }, /* R68 - PLL1 Control */
750 /* choose PLL1 clock rate */ alc5632_set_dai_pll()
752 /* enable PLL1 */ alc5632_set_dai_pll()
760 /* use PLL1 as main SYSCLK */ alc5632_set_dai_pll()
H A Drt5670.c1546 SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
2026 { "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2030 { "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2035 { "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
2040 { "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
2065 { "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2069 { "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2183 { "DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2184 { "DAC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
2185 { "DAC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
H A Drt5651.c917 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
1202 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
1212 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
1279 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
1282 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
H A Drt5645.c1433 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1825 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1829 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1834 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1839 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1935 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1936 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1937 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1938 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
H A Drt5677.c2500 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
3217 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3237 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3251 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3265 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3273 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3278 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3879 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3886 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3892 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3899 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3905 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3912 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3918 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
H A Dwm8804.c40 { 3, 0x21 }, /* R3 - PLL1 */
H A Dadau1373.c793 SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
983 { "SYSCLK1", NULL, "PLL1" },
H A Dwm8990.h804 * R60 (0x3C) - PLL1
H A Dwm8991.h793 * R60 (0x3C) - PLL1
H A Dwm8990.c109 { 60, 0x0008 }, /* R60 - PLL1 */
H A Dwm8991.c99 { 60, 0x0008 }, /* R60 - PLL1 */
H A Drt5670.h1935 /* PLL1 Source */
H A Drt5677.h1674 /* PLL1 Source */
H A Drt5640.h2044 /* PLL1 Source */
H A Drt5645.h2136 /* PLL1 Source */
H A Drt5651.h2041 /* PLL1 Source */
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h134 #define PLL1 117 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h134 #define PLL1 117 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h134 #define PLL1 117 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h134 #define PLL1 117 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h134 #define PLL1 117 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h134 #define PLL1 117 macro
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
H A Dclock-shx3.c31 /* PLL1 has a fixed x72 multiplier. */ pll_recalc()
H A Dclock-sh7786.c33 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1, pll_recalc()
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dclock.c271 seq_printf(s, "PLL1 = %8x\n", pm_readl(PLL1)); clk_show()
H A Dat32ap700x.c209 ctrl = pm_readl(PLL1); pll1_mode()
219 pm_writel(PLL1, ctrl); pll1_mode()
234 pm_writel(PLL1, ctrl); pll1_mode()
242 control = pm_readl(PLL1); pll1_get_rate()
261 pm_writel(PLL1, ctrl); pll1_set_rate()
274 ctrl = pm_readl(PLL1); pll1_set_parent()
284 pm_writel(PLL1, ctrl); pll1_set_parent()
2299 if (pm_readl(PLL1) & PM_BIT(PLLOSC)) setup_platform()
/linux-4.1.27/drivers/clk/
H A Dclk-nomadik.c139 * struct clk_pll1 - Nomadik PLL1 clock
283 pr_debug("register PLL1 clock \"%s\"\n", name); pll_clk_register()
545 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4. of_nomadik_hclk_setup()
/linux-4.1.27/drivers/clk/shmobile/
H A Dclk-sh73a0.c115 /* handle CFG bit for PLL1 and PLL2 */ sh73a0_cpg_register_clock()
H A Dclk-rcar-gen2.c253 * MD EXTAL PLL0 PLL1 PLL3
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-sunxi.c242 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
243 * PLL1 rate is calculated as follows
294 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
295 * PLL1 rate is calculated as follows
378 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
379 * PLL1 rate is calculated as follows
/linux-4.1.27/drivers/cpufreq/
H A Dimx6q-cpufreq.c93 * PLL1 is as below. imx6q_set_target()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dzl10039.c54 PLL1, enumerator in enum:zl10039_reg_addr
H A Dtda10023.c240 /* PLL1 */ tda10023_init()
/linux-4.1.27/drivers/clk/st/
H A Dclkgen-pll.c208 /* 407 C0 PLL1 */
527 * PLL1 output clkgena_c65_pll_setup()
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_regs.h196 /* PLL1 clock generator RW */
357 /* PLL1 Adjustment value */
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dclock-sh73a0.c93 /* PLL0, PLL1, PLL2, PLL3 */ pll_recalc()
100 /* handle CFG bit for PLL1 and PLL2 */ pll_recalc()
/linux-4.1.27/drivers/clk/spear/
H A Dspear6xx_clock.c93 /* For PLL1 = 332 MHz */
H A Dspear3xx_clock.c108 /* For PLL1 = 332 MHz */
/linux-4.1.27/arch/c6x/platforms/
H A Dplldata.c28 /* Default input for PLL1 */
/linux-4.1.27/arch/arm/mach-davinci/
H A Dda850.c1331 * Move the clock source of Async3 domain to PLL1 SYSCLK2. da850_init()
1334 * both PLL0 and PLL1 to the same frequency so, there should not da850_init()
1344 /* Unlock writing to PLL1 registers */ da850_init()
/linux-4.1.27/arch/arm/mach-ep93xx/
H A Dclock.c554 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", ep93xx_clock_init()
/linux-4.1.27/drivers/iio/frequency/
H A Dad9523.c768 * PLL1 Setup ad9523_setup()
/linux-4.1.27/drivers/mfd/
H A Dtc6393xb.c49 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
/linux-4.1.27/drivers/clk/sirf/
H A Dclk-common.c25 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-imx6sl.c170 * PLL1 clock enabled. imx6sl_set_wait_clk()
/linux-4.1.27/drivers/video/fbdev/
H A Dsmscufx.c399 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); ufx_config_sys_clk()
652 "error clearing PLL1 bypass bits in 0x7000"); ufx_config_pix_clk()
/linux-4.1.27/arch/powerpc/kernel/
H A Dmisc_32.S181 /* If switching to PLL1, disable HID0:BTIC */
/linux-4.1.27/sound/pci/hda/
H A Dpatch_realtek.c3000 alc5505_coef_set(codec, 0x61b0, 0x00005b17); /* Stop PLL1 */ alc5505_dsp_halt()
3022 alc5505_coef_set(codec, 0x61b0, 0x5b14); /* PLL1 control */ alc5505_dsp_init()

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