Searched refs:MMCR1_TD_CP_DBG0SEL_SH (Results 1 - 4 of 4) sorted by relevance

/linux-4.1.27/arch/powerpc/perf/
H A Dppc970-pmu.c56 #define MMCR1_TD_CP_DBG0SEL_SH 50 macro
344 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); p970_compute_mmcr()
H A Dpower5+-pmu.c52 #define MMCR1_TD_CP_DBG0SEL_SH 54 macro
547 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); power5p_compute_mmcr()
H A Dpower5-pmu.c52 #define MMCR1_TD_CP_DBG0SEL_SH 54 macro
487 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); power5_compute_mmcr()
H A Dpower4-pmu.c64 #define MMCR1_TD_CP_DBG0SEL_SH 50 macro
465 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); p4_compute_mmcr()

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