Searched refs:INTR_STATUS (Results 1 - 6 of 6) sorted by relevance

/linux-4.1.27/drivers/gpio/
H A Dgpio-msm-v2.c48 INTR_STATUS = 0, enumerator in enum:__anon3931
230 intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); msm_gpio_update_dual_edge_pos()
243 writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); msm_gpio_irq_ack()
324 if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) for_each_set_bit()
/linux-4.1.27/drivers/mtd/nand/
H A Ddenali.c187 denali->flash_reg + INTR_STATUS(i)); denali_nand_reset()
191 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & denali_nand_reset()
194 if (ioread32(denali->flash_reg + INTR_STATUS(i)) & denali_nand_reset()
202 denali->flash_reg + INTR_STATUS(i)); denali_nand_reset()
588 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); denali_irq_init()
623 intr_status_reg = INTR_STATUS(denali->flash_bank); clear_interrupt()
645 intr_status_reg = INTR_STATUS(denali->flash_bank); read_interrupt_status()
H A Ddenali.h217 #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) macro
/linux-4.1.27/drivers/block/
H A Dida_cmd.h42 #define INTR_STATUS 0x10 macro
/linux-4.1.27/drivers/rtc/
H A Drtc-tegra.c51 /* bits in INTR_STATUS */
/linux-4.1.27/drivers/pinctrl/qcom/
H A Dpinctrl-msm.c678 * could cause the INTR_STATUS to be set for EDGE interrupts. msm_gpio_irq_set_type()

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