Searched refs:EVERGREEN_CRTC_CONTROL (Results 1 – 3 of 3) sorted by relevance
657 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | in radeon_card_posted()658 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_card_posted()660 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | in radeon_card_posted()661 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_card_posted()664 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | in radeon_card_posted()665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_card_posted()
233 #define EVERGREEN_CRTC_CONTROL 0x6e70 macro
1310 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()1626 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()1628 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()1651 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()1653 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()2719 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()2732 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()2737 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()2761 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()2763 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()[all …]