Searched refs:DMC0 (Results 1 - 3 of 3) sorted by relevance

/linux-4.1.27/drivers/cpufreq/
H A Ds5pv210-cpufreq.c107 /* DRAM configuration (DMC0 and DMC1) */
121 DMC0 = 0, enumerator in enum:s5pv210_dmc_port
203 if (ch == DMC0) { s5pv210_set_refresh()
288 s5pv210_set_refresh(DMC0, 83000); s5pv210_target()
464 * DMC0 : 166Mhz s5pv210_target()
467 s5pv210_set_refresh(DMC0, 166000); s5pv210_target()
471 * DMC0 : 83Mhz s5pv210_target()
474 s5pv210_set_refresh(DMC0, 83000); s5pv210_target()
/linux-4.1.27/drivers/devfreq/exynos/
H A Dexynos4_bus.c87 unsigned int dmc_divtable[_LV_END]; /* DMC0 */
303 /* Change Divider - DMC0 */ exynos4210_set_busclk()
369 /* Change Divider - DMC0 */ exynos4x12_set_busclk()
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A DdefBF60x_base.h2651 DMC0
2653 #define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
2654 #define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
2655 #define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
2656 #define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
2657 #define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
2658 #define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
2659 #define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
2660 #define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
2661 #define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
2662 #define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
2663 #define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
2664 #define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
2665 #define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
2666 #define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
2667 #define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
2668 #define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
2669 #define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */

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