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Searched refs:D0Ar4 (Results 1 – 26 of 26) sorted by relevance

/linux-4.1.27/arch/metag/tbx/
Dtbictxfpu.S47 MOVT D0Ar4, #HI(METAC_CORE_ID)
48 ADD D0Ar4, D0Ar4, #LO(METAC_CORE_ID)
49 GETD D0Ar4, [D0Ar4]
54 AND D0Ar4, D0Ar4, #LO(0x0000FFFF)
55 ORT D0Ar4, D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT)
56 XOR D0Ar4, D0Ar4, D0Ar6
59 SETD [D1Ar3++], D0Ar4
78 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
90 TST D0Ar4, #METAC_COREID_NOFPACC_BIT
139 GETD D0Ar4, [D1Ar3++]
[all …]
Dtbictx.S38 XOR D0Ar4,D0Ar4,#-1 /* D0Ar4 = ~TrigBit */
39 AND D0Ar4,D0Ar4,#0xFFFF /* D0Ar4 &= 0xFFFF */
42 AND D0Ar4,D0Ar2,D0Ar4 /* D0Ar4 = Ints to allow */
43 XOR D0Ar2,D0Ar2,D0Ar4 /* Less Ints in TrigMask */
46 OR D0Ar4,D0Ar4,D0Ar6 /* Or in TXMASKI BGNDHALT if set */
47 TSTNZ D0Ar4,D0Ar4 /* Yes: AND triggers enabled */
50 MOVZ TXMASKI,D0Ar4 /* Early return: Enable Ints */
65 OR D0.6,D0Ar4,D0Ar6 /* Save TrigMask in D0.6 */
109 MOV D0Ar4,D0Ar2 /* Extract Ctx.SaveFlags value */
110 ANDMT D0Ar4,D0Ar4,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT
[all …]
Dtbipcx.S93 MSETL [A0.3],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
142 MSETL [A1.2],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
143 MOV D0Ar4,TXRPT /* Save critical CT regs */
153 MSETL [A1.2],D0Ar4,D0Ar2 /* Save CT regs state */
174 MOV D0Ar4,TXSTATI /* Read the Triggers data */
185 AND TXSTATI,D0Ar4,#TXSTATI_BGNDHALT_BIT/* Ack any HALT seen */
186 ANDS D0Ar4,D0Ar4,#0xFFFF-TXSTATI_BGNDHALT_BIT /* Only seen HALT? */
246 MOV D0Ar4,TXMASKI /* Read TXMASKI */
247 OR TXMASKI,D0Ar4,D0Re0 /* -Write-Modify TXMASKI */
262 ADD D0Ar4,A0FrP,#TBICTX_BYTES /* Source is after TBICTX */
[all …]
Dtbidspram.S46 DL MOV D0Ar4, [D0AR.0++]
48 MSETL [A0.3++], D0Re0, D0Ar6, D0Ar4, D0.5
80 DL MOV D0Ar4, [D0BR.0++]
82 MSETL [A0.3++], D0Re0, D0Ar6, D0Ar4, D0.5
112 MGETL D0Re0, D0Ar6, D0Ar4, D0.5, [A0.3++]
115 DL MOV [D0AW.0++], D0Ar4
146 MGETL D0Re0, D0Ar6, D0Ar4, D0.5, [A0.3++]
149 DL MOV [D0BW.0++], D0Ar4
Dtbitimer.S93 ADDS D0Re0,D0Ar4,D0Ar6 /* Add current time value */
120 ADDS D0Ar4,D0Ar4,D0Ar2 /* Add time added to ... */
123 SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
152 ADDS D0Ar4,D0Ar4,D0Ar2 /* Add time added to ... */
155 SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
201 GETL D0Ar4,D1Ar3,[A0.3] /* Read ___TBITime(B/I) */
Dtbisoft.S90 MSETL [A0StP],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
158 OR TXMASKI,D0Re0,D0Ar4 /* New TXMASKI */
192 MSETL [A0.2],D0Ar6,D0Ar4 /* Save extra initial args */
207 MOV D0Ar4,D0FrT /* Initial A0FrP */
210 MSETL [A0.2],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
215 MSETL [A0.2],D0Ar6,D0Ar4,D0Ar2,D0FrT D0_5 /* Set DX and then AX regs */
226 MGETL D0Re0,D0Ar6,D0Ar4,[A0FrP] /* Get hidden args */
Dtbidefr.S53 OR D0Ar4, D1Ar3, #TXSTAT_DEFER_BIT
116 DEFR D0Ar4, TXSTATI
119 MOV D1Ar3, D0Ar4
Dtbilogf.S24 MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2
40 MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2
Dtbicore.S59 GETL D1Ar3,D0Ar4,[A1LbP] /* Read segment list head */
70 GETL D1Ar3,D0Ar4,[D1Ar3] /* Read pLink and Id */
71 CMP D0Ar4,D0Ar2 /* Does it match? */
/linux-4.1.27/arch/metag/lib/
Ddiv64.S12 ORS A0.3,D1Ar3,D0Ar4
20 CMPEQ D0Ar4,D0Ar2
25 ADDS D0Ar6,D0Ar4,D0Ar4
29 CMPEQ D0Ar6,D0Ar4
32 MOV D0Ar4,D0Ar6
38 CMPEQ D0Ar4,D0Ar2
47 CMPEQ D0Ar2,D0Ar4
54 SUBS D0Ar2,D0Ar2,D0Ar4
63 LSR D0Ar4,D0Ar4,#1
65 OR D0Ar4,D0Ar4,A0.3
[all …]
Dmemmove.S18 SUB D0Ar4, D1Ar1, D1Ar3
19 ADD D0Ar4, D0Ar4, #1
20 CMP D0Ar2, D0Ar4
33 MOV D0Ar4, D0Ar2
40 ANDS D0Ar4, D0Ar4, #7
78 MOV D0Ar4, A1.2
82 ADD D0Ar4, D0Ar4, #7
83 ANDMB D0Ar4, D0Ar4, #0xfff8
85 MOV A1.2, D0Ar4
89 SUB D0Ar6, D0Ar4, D0Ar6
[all …]
Dmuldi3.S11 ! B = D1Ar3:D0Ar4 = w 2^48 + x 2^32 + y 2^16 + z 2^0
18 MULD D1Re0,D1Ar1,D0Ar4 ! (a 2^48 + b 2^32)(y 2^16 + z 2^0)
22 MULW D0Re0,D0Ar2,D0Ar4 ! (d 2^0) * (z 2^0)
25 MULW D0Ar6,D0Ar2,D0Ar4 ! (c 2^16)(z 2^0)
30 RTDW D0Ar4,D0Ar4
33 MULW D0Ar6,D0Ar2,D0Ar4 ! (c 2^16)(y 2^16)
37 MULW D0Ar6,D0Ar2,D0Ar4 ! (d 2^0)(y 2^16)
Dashldi3.S16 SUBS D0Ar4,D1Ar3,#32 ! N = COUNT - 32
20 NEG D0Ar4,D0Ar4 ! N = - N
22 LSR D0Ar6,D0Re0,D0Ar4 ! TMP= LO >> -(COUNT - 32)
24 SWAP D0Ar4,D1Ar3
25 LSL D0Re0,D0Re0,D0Ar4 ! LO = LO << COUNT
30 LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
Dip_fast_csum.S22 LSR D0Ar4,D0Re0,#16
24 AND D0Ar4,D0Ar4,#0xffff
25 ADD D0Re0,D0Re0,D0Ar4
26 LSR D0Ar4,D0Re0,#16
27 ADD D0Re0,D0Re0,D0Ar4
Ddivsi3.S17 MOV D0Ar4,#0 ! Return positive result
33 XOR D0Ar4,D1Ar1,D1Re0 ! D0Ar4 -ive if result is -ive
52 ORS D0Ar4,D0Ar4,D0Ar4 ! Return neg result?
63 !! D0Ar4 is negative if we should return a negative result
96 ORS D0Ar4,D0Ar4,D0Ar4 ! Return neg result?
Dmemcpy.S52 MOV D0Ar4, A1.2
54 ANDS D0Ar4, D0Ar4, #7 ! test source alignment
84 MOV D0Ar4, A1.2
86 ANDMB D0Ar4, D0Ar4, #0xfff8
87 MOV A1.2, D0Ar4
88 ! Save the number of bytes of mis-alignment in D0Ar4 for use later
89 SUBS D0Ar6, D0Ar6, D0Ar4
90 MOV D0Ar4, D0Ar6
181 ADD D1Ar5, D0Ar4, D0Ar6
Dlshrdi3.S16 MOV D0Ar4,D1Ar3
22 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
25 SWAP D1Ar3,D0Ar4
Dashrdi3.S16 MOV D0Ar4,D1Ar3
22 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
25 SWAP D1Ar3,D0Ar4
Ducmpdi2.S12 ! u64 b (D0Ar4, D1Ar3)
20 CMPEQ D0Ar2,D0Ar4
Dcmpdi2.S12 ! s64 b (D0Ar4, D1Ar3)
22 CMP D0Ar2,D0Ar4
Dmemset.S13 ANDS D0Ar4,D1Ar1,#7 ! Extract bottom LSBs of dst
22 SUB D1Ar5,D0Ar2,D0Ar4 ! ... subtract N
/linux-4.1.27/arch/metag/kernel/
Dftrace_stub.S19 MSETL [A0StP], D0Ar6, D0Ar4, D0Ar2, D0.4
30 GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
38 MSETL [A0StP], D0Ar6, D0Ar4, D0Ar2, D0.4
54 GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
Dhead.S16 ! D0Ar4 contains kernel arglist pointer
28 MOV D1Ar1,D0Ar4 !Store kernel boot params
Dtbiunexp.S15 MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2 ! Save args on stack
/linux-4.1.27/Documentation/metag/
Dkernel-ABI.txt63 D0.2 (D0Ar4) Argument 4 D1.2 (D1Ar3) Argument 3
132 D0.2 (D0Ar4) Syscall arg #4 Preserved
157 D0.2 (D0Ar4) lo(len) D1.2 (D1Ar3) hi(offs)
177 D0.2 (D0Ar4) 32bit argument #4 Clobbered
/linux-4.1.27/arch/metag/include/asm/
Dmetag_regs.h87 #define D0Ar4 D0.2 macro