Searched refs:Clock (Results 1 - 200 of 1114) sorted by relevance

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/linux-4.1.27/include/linux/can/platform/
H A Drcar_can.h6 /* Clock Select Register settings */
14 enum CLKR clock_select; /* Clock source select */
H A Dcc770.h5 #define CPUIF_CEN 0x01 /* Clock Out Enable */
9 #define CPUIF_DMC 0x20 /* Divide Memory Clock */
10 #define CPUIF_DSC 0x40 /* Divide System Clock */
13 /* Clock Out Register (0x1f) */
14 #define CLKOUT_CD_MASK 0x0f /* Clock Divider mask */
29 u8 cor; /* Clock Out Register */
H A Dsja1000.h6 #define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */
/linux-4.1.27/arch/arm/mach-mmp/include/mach/
H A Dregs-apbc.h4 * Application Peripheral Bus Clock Unit
17 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
18 #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
21 /* Functional Clock Selection Mask */
H A Dregs-rtc.h10 * Real Time Clock
/linux-4.1.27/arch/powerpc/include/asm/
H A Dmpc5121.h25 * Clock Control Module
29 u32 sccr1; /* System Clock Control Register 1 */
30 u32 sccr2; /* System Clock Control Register 2 */
31 u32 scfr1; /* System Clock Frequency Register 1 */
32 u32 scfr2; /* System Clock Frequency Register 2 */
33 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
35 u32 psc_ccr[12]; /* PSC Clock Control Registers */
36 u32 spccr; /* SPDIF Clock Control Register */
37 u32 cccr; /* CFM Clock Control Register */
38 u32 dccr; /* DIU Clock Control Register */
39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
42 u32 scfr3; /* System Clock Frequency Register 3 */
H A Dcpm2.h778 * CMXFCR - CMX FCC Clock Route Register
781 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
782 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
784 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
785 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
787 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
788 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
790 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
791 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
792 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
793 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
794 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
795 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
796 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
797 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
799 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
800 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
801 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
802 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
803 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
804 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
805 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
806 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
808 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
809 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
810 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
811 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
812 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
813 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
814 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
815 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
817 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
818 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
819 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
820 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
821 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
822 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
823 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
824 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
826 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
827 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
828 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
829 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
830 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
831 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
832 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
833 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
835 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
836 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
837 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
838 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
839 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
840 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
841 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
842 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
845 * CMXSCR - CMX SCC Clock Route Register
849 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
850 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
853 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
854 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
857 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
858 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
861 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
862 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
864 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
865 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
866 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
867 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
868 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
869 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
870 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
871 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
873 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
874 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
875 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
876 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
877 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
878 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
879 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
880 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
882 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
883 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
884 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
885 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
886 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
887 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
888 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
889 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
891 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
892 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
893 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
894 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
895 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
896 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
897 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
898 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
900 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
901 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
902 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
903 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
904 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
905 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
906 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
907 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
909 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
910 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
911 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
912 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
913 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
914 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
915 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
916 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
918 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
919 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
920 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
921 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
922 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
923 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
924 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
925 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
927 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
928 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
929 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
930 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
931 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
932 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
933 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
934 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
974 * SCCR - System Clock Control Register 9-8
994 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
995 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
996 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
997 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
998 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
999 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1112 CPM_CLK1, /* Clock 1 */
1113 CPM_CLK2, /* Clock 2 */
1114 CPM_CLK3, /* Clock 3 */
1115 CPM_CLK4, /* Clock 4 */
1116 CPM_CLK5, /* Clock 5 */
1117 CPM_CLK6, /* Clock 6 */
1118 CPM_CLK7, /* Clock 7 */
1119 CPM_CLK8, /* Clock 8 */
1120 CPM_CLK9, /* Clock 9 */
1121 CPM_CLK10, /* Clock 10 */
1122 CPM_CLK11, /* Clock 11 */
1123 CPM_CLK12, /* Clock 12 */
1124 CPM_CLK13, /* Clock 13 */
1125 CPM_CLK14, /* Clock 14 */
1126 CPM_CLK15, /* Clock 15 */
1127 CPM_CLK16, /* Clock 16 */
1128 CPM_CLK17, /* Clock 17 */
1129 CPM_CLK18, /* Clock 18 */
1130 CPM_CLK19, /* Clock 19 */
1131 CPM_CLK20, /* Clock 20 */
H A Dqe.h54 QE_CLK1, /* Clock 1 */
55 QE_CLK2, /* Clock 2 */
56 QE_CLK3, /* Clock 3 */
57 QE_CLK4, /* Clock 4 */
58 QE_CLK5, /* Clock 5 */
59 QE_CLK6, /* Clock 6 */
60 QE_CLK7, /* Clock 7 */
61 QE_CLK8, /* Clock 8 */
62 QE_CLK9, /* Clock 9 */
63 QE_CLK10, /* Clock 10 */
64 QE_CLK11, /* Clock 11 */
65 QE_CLK12, /* Clock 12 */
66 QE_CLK13, /* Clock 13 */
67 QE_CLK14, /* Clock 14 */
68 QE_CLK15, /* Clock 15 */
69 QE_CLK16, /* Clock 16 */
70 QE_CLK17, /* Clock 17 */
71 QE_CLK18, /* Clock 18 */
72 QE_CLK19, /* Clock 19 */
73 QE_CLK20, /* Clock 20 */
74 QE_CLK21, /* Clock 21 */
75 QE_CLK22, /* Clock 22 */
76 QE_CLK23, /* Clock 23 */
77 QE_CLK24, /* Clock 24 */
H A Dhydra.h61 #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
62 #define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
H A Dfsl_guts.h80 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
88 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
89 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
90 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
92 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
H A Drtc.h18 * Linux/SPARC Real Time Clock Driver
H A Dcpm1.h184 /* SI Clock Route Register
594 CPM_CLK1, /* Clock 1 */
595 CPM_CLK2, /* Clock 2 */
596 CPM_CLK3, /* Clock 3 */
597 CPM_CLK4, /* Clock 4 */
598 CPM_CLK5, /* Clock 5 */
599 CPM_CLK6, /* Clock 6 */
600 CPM_CLK7, /* Clock 7 */
601 CPM_CLK8, /* Clock 8 */
/linux-4.1.27/include/linux/clk/
H A Dat91_pmc.h31 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
32 #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
34 #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
35 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
36 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
37 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
38 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
39 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
40 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
41 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
42 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
43 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
44 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
45 #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
46 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
47 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
49 #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
50 #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
51 #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
53 #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
66 #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
68 #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
69 #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
70 #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
76 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
87 #define AT91_PMC_MCKR 0x30 /* Master Clock Register */
88 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
95 #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
104 #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
112 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
122 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
130 #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
135 #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
139 #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
144 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
145 #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
147 #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
157 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
160 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
161 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
162 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
163 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
166 #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
180 #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
181 #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
182 #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dat91.h15 #define AT91_PMC_MCKRDY 3 /* Master Clock */
17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
20 #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dat91.h15 #define AT91_PMC_MCKRDY 3 /* Master Clock */
17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
20 #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dat91.h15 #define AT91_PMC_MCKRDY 3 /* Master Clock */
17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
20 #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dat91.h15 #define AT91_PMC_MCKRDY 3 /* Master Clock */
17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
20 #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dat91.h15 #define AT91_PMC_MCKRDY 3 /* Master Clock */
17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
20 #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
/linux-4.1.27/include/dt-bindings/clock/
H A Dat91.h15 #define AT91_PMC_MCKRDY 3 /* Master Clock */
17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
20 #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dpxa2xx-regs.h137 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
138 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
139 #define CKEN __REG(0x41300004) /* Clock Enable Register */
157 #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
158 #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
159 #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
161 #define CKEN_IM (20) /* Internal Memory Clock Enable */
162 #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
163 #define CKEN_USIM (18) /* USIM Unit Clock Enable */
164 #define CKEN_MSL (17) /* MSL Unit Clock Enable */
165 #define CKEN_LCD (16) /* LCD Unit Clock Enable */
166 #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
167 #define CKEN_I2C (14) /* I2C Unit Clock Enable */
168 #define CKEN_FICP (13) /* FICP Unit Clock Enable */
169 #define CKEN_MMC (12) /* MMC Unit Clock Enable */
170 #define CKEN_USB (11) /* USB Unit Clock Enable */
171 #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
172 #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
173 #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
174 #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
175 #define CKEN_I2S (8) /* I2S Unit Clock Enable */
176 #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
177 #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
178 #define CKEN_STUART (5) /* STUART Unit Clock Enable */
179 #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
180 #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
181 #define CKEN_SSP (3) /* SSP Unit Clock Enable */
182 #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
183 #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
184 #define CKEN_PWM1 (1) /* PWM1 Clock Enable */
185 #define CKEN_PWM0 (0) /* PWM0 Clock Enable */
H A Dpxa3xx-regs.h127 * Application Subsystem Clock
129 #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
130 #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
132 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
133 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
134 #define CKENC __REG(0x41340024) /* C Clock Enable Register */
139 #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
140 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
146 #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
147 #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
160 * Clock Enable Bit
162 #define CKEN_LCD 1 /* < LCD Clock Enable */
165 #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
171 #define CKEN_MMC1 12 /* < MMC1 Clock enable */
173 #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
174 #define CKEN_CIR 15 /* < Consumer IR Clock Enable */
175 #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
176 #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
183 #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
199 #define CKEN_MMC3 5 /* < MMC3 Clock Enable */
H A Dregs-rtc.h7 * Real Time Clock
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dregs-spi.h25 #define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
26 #define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
28 #define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
29 #define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
H A Dsamsung-time.h16 /* SAMSUNG HR-Timer Clock mode */
/linux-4.1.27/drivers/staging/iio/adc/
H A Dad7192.h20 * 1 External Clock applied to MCLK2
21 * 2 Internal 4.92 MHz Clock not available at the MCLK2 pin
22 * 3 Internal 4.92 MHz Clock available at the MCLK2 pin
/linux-4.1.27/arch/arm/mach-ks8695/include/mach/
H A Dregs-sys.h23 #define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */
29 /* System Clock and Bus Control Register */
31 #define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */
/linux-4.1.27/drivers/clk/ux500/
H A Du9540_clk.c2 * Clock definitions for u9540 platform.
H A Dabx500-clk.c22 /* Clock definitions for ab8500 */ ab8500_reg_clks()
90 /* Clock definitions for ab8540 */ ab8540_reg_clks()
96 /* Clock definitions for ab9540 */ ab9540_reg_clks()
/linux-4.1.27/arch/blackfin/include/uapi/asm/
H A Dbfin_sport.h67 #define ITCLK 0x0002 /* Internal TX Clock Select */
78 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */
90 #define IRCLK 0x0002 /* Internal RX Clock Select */
98 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */
124 #define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
125 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
126 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
127 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
/linux-4.1.27/arch/mips/include/asm/mach-loongson1/
H A Dregs-clk.h4 * Loongson 1 Clock Register Definitions.
21 /* Clock PLL Divisor Register Bits */
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dclock.h2 * Clock management for AT32AP CPUs
22 const char *name; /* Clock name/function */
/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_mode.h35 /* Clock Phase. This clock phase only applies to Panel. */
H A Dddk750_swi2c.c63 * for the i2c Clock and i2c Data.
72 /* i2c Clock GPIO Register usage */
366 /* Initialize the GPIO pin for the i2c Clock Register */ swI2CInit_SM750LE()
370 /* Initialize the Clock GPIO Offset */ swI2CInit_SM750LE()
414 /* Initialize the GPIO pin for the i2c Clock Register */ swI2CInit()
419 /* Initialize the Clock GPIO Offset */ swI2CInit()
430 /* Enable the GPIO pins for the i2c Clock and Data (GPIO MUX) */ swI2CInit()
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-rtc.h2 * PKUnity Real-Time Clock (RTC) control registers
H A Dregs-sdc.h5 * Clock Control Reg SDC_CCR
70 * SD Clock Enable SDC_CCR_CLKEN
H A Dregs-pm.h25 * PM Clock Gate Reg PM_PCGR
/linux-4.1.27/include/linux/platform_data/
H A Dclk-ux500.h2 * Clock definitions for ux500 platforms
H A Dleds-lp55xx.h18 /* Clock configuration */
67 /* Clock configuration */
H A Dspi-s3c64xx.h34 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
49 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
H A Dclock.h4 * Clock control driver for DaVinci - header file
/linux-4.1.27/sound/soc/codecs/
H A Dadau1761.c396 SND_SOC_DAPM_SUPPLY("Serial Port Clock", ADAU1761_CLK_ENABLE0,
398 SND_SOC_DAPM_SUPPLY("Serial Input Routing Clock", ADAU1761_CLK_ENABLE0,
400 SND_SOC_DAPM_SUPPLY("Serial Output Routing Clock", ADAU1761_CLK_ENABLE0,
403 SND_SOC_DAPM_SUPPLY("Decimator Resync Clock", ADAU1761_CLK_ENABLE0,
405 SND_SOC_DAPM_SUPPLY("Interpolator Resync Clock", ADAU1761_CLK_ENABLE0,
408 SND_SOC_DAPM_SUPPLY("Slew Clock", ADAU1761_CLK_ENABLE0, 6, 0, NULL, 0),
409 SND_SOC_DAPM_SUPPLY("ALC Clock", ADAU1761_CLK_ENABLE0, 5, 0, NULL, 0),
411 SND_SOC_DAPM_SUPPLY_S("Digital Clock 0", 1, ADAU1761_CLK_ENABLE1,
413 SND_SOC_DAPM_SUPPLY_S("Digital Clock 1", 1, ADAU1761_CLK_ENABLE1,
418 { "Left Decimator", NULL, "Digital Clock 0", },
419 { "Right Decimator", NULL, "Digital Clock 0", },
420 { "Left DAC", NULL, "Digital Clock 0", },
421 { "Right DAC", NULL, "Digital Clock 0", },
423 { "AIFCLK", NULL, "Digital Clock 1" },
425 { "Playback", NULL, "Serial Port Clock" },
426 { "Capture", NULL, "Serial Port Clock" },
427 { "Playback", NULL, "Serial Input Routing Clock" },
428 { "Capture", NULL, "Serial Output Routing Clock" },
430 { "Left Decimator", NULL, "Decimator Resync Clock" },
431 { "Right Decimator", NULL, "Decimator Resync Clock" },
432 { "Left DAC", NULL, "Interpolator Resync Clock" },
433 { "Right DAC", NULL, "Interpolator Resync Clock" },
435 { "DSP", NULL, "Digital Clock 0" },
437 { "Slew Clock", NULL, "Digital Clock 0" },
438 { "Right Playback Mixer", NULL, "Slew Clock" },
439 { "Left Playback Mixer", NULL, "Slew Clock" },
441 { "Left Input Mixer", NULL, "ALC Clock" },
442 { "Right Input Mixer", NULL, "ALC Clock" },
444 { "Digital Clock 0", NULL, "SYSCLK" },
445 { "Digital Clock 1", NULL, "SYSCLK" },
H A Dssm2602.h117 #define IFACE_BCLK_INVERT 0x080 /* Bit Clock Inversion control */
122 #define SRATE_SAMPLE_RATE 0x03C /* Clock setting condition (Sampling rate control) */
123 #define SRATE_CORECLK_DIV2 0x040 /* Core Clock divider select */
124 #define SRATE_CLKOUT_DIV2 0x080 /* Clock Out divider select */
H A Dtlv320aic31xx.h49 /* Clock clock Gen muxing, Multiplexers*/
68 /* Clock setting register 8, PLL */
70 /* Clock setting register 9, PLL */
74 /* Clock setting register 9, Multiplexers */
76 /* Clock setting register 10, CLOCKOUT M divider value */
84 /* Clock setting register 11, BCLK N Divider */
H A Dwm8510.h57 /* Clock divider Id's */
H A Dwm8940.h72 /* Clock divider Id's */
H A Dwm8960.h72 * WM8960 Clock dividers
H A Dwm8974.h57 /* Clock divider Id's */
H A Dwm8978.h74 /* Clock divider Id's */
H A Dmax98925.c53 { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
54 { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
55 { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
56 { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
57 { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
58 { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
H A Dml26124.h21 /* Clock Control Register */
122 /* Clock select for machine driver */
/linux-4.1.27/drivers/pinctrl/
H A Dpinctrl-at91.h44 #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
45 #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
46 #define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
47 #define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
48 #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
/linux-4.1.27/include/linux/
H A Dpxa2xx_ssp.h40 #define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
45 #define SSACD (0x3C) /* SSP Audio Clock Divider */
46 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
137 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
138 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
139 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
140 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
153 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
160 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
H A Dserial_sci.h18 #define SCSMR_CKS 0x0003 /* Clock Select */
27 #define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
28 #define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
H A Dsxgbe_platform.h16 /* MDC Clock Selection define*/
H A Dmdio-bitbang.h13 /* Set the Management Data Clock high if level is one,
H A Di2c-algo-pca.h11 /* Clock speeds for the bus for PCA9564*/
53 #define I2C_PCA_CON_CR 0x07 /* Clock Rate (MASK) */
H A Datmel_serial.h48 #define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
76 #define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
115 #define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
H A Dscx200.h37 /* Clock Generators */
/linux-4.1.27/arch/mips/pmcs-msp71xx/
H A Dmsp_time.c56 "Clock rate in Hz parse error: %s\n", s); plat_time_init()
66 "Clock rate in MHz parse error: %s\n", s); plat_time_init()
85 printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate); plat_time_init()
/linux-4.1.27/drivers/clk/st/
H A Dclkgen.h2 File : Clock H/w specific Information
/linux-4.1.27/arch/arm/mach-omap2/
H A Dcm44xx.h2 * OMAP4 Clock Management (CM) definitions
H A Dcm2xxx.h2 * OMAP2xxx Clock Management (CM) register definitions
45 /* Clock management domain register get/set */
H A Dcm-regbits-7xx.h2 * DRA7xx Clock Management register bits
H A Dcm3xxx.h2 * OMAP2/3 Clock Management (CM) register definitions
H A Dcm81xx.h2 * Clock domain register offsets for TI81XX.
/linux-4.1.27/arch/arm/mach-imx/
H A Dcpuidle-imx6sl.c45 .desc = "Clock off",
H A Dcpuidle-imx6q.c58 .desc = "Clock off",
H A Dcpuidle-imx6sx.c71 .desc = "Clock off",
/linux-4.1.27/sound/soc/samsung/
H A Ds3c24xx-i2s.h24 /* Clock dividers */
/linux-4.1.27/include/linux/usb/
H A Disp1362.h12 /* Clock cannot be stopped */
34 /* Clock start/stop */
H A Daudio-v2.h67 /* 4.7.2.1 Clock Source Descriptor */
87 /* 4.7.2.2 Clock Source Descriptor */
99 /* 4.7.2.3 Clock Multiplier Descriptor */
268 /* A.17.1 Clock Source Control Selectors */
273 /* A.17.2 Clock Selector Control Selectors */
277 /* A.17.3 Clock Multiplier Control Selectors */
/linux-4.1.27/arch/blackfin/include/asm/
H A Dtime.h29 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
30 * Whenever we change the Core Clock frequency changes we immediately
H A Dbfin_sport3.h34 #define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
36 #define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
59 #define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
81 #define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
H A Dclocks.h2 * Common Clock definitions for various kernel files
H A Dbfin_ppi.h120 #define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
124 #define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
125 #define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
126 #define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
127 #define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
154 #define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
/linux-4.1.27/arch/m68k/include/asm/
H A Dmcfpit.h40 #define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */
41 #define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */
H A DMC68EZ328.h154 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
156 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
158 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
176 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
184 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
516 #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
524 #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
526 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
562 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
653 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
689 #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
780 #define UMISC_CLKSRC 0x4000 /* Clock Source */
936 * LCD Pixel Clock Divider Register
941 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1005 #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1007 #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1012 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1187 #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1188 #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
H A DMC68328.h192 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
193 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
195 #define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
213 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
221 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
652 #define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
659 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
697 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
846 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
881 #define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
971 #define UMISC_CLKSRC 0x4000 /* Clock Source */
1112 * LCD Pixel Clock Divider Register
1117 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1126 #define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
1190 * 0xFFFFFBxx -- Real-Time Clock (RTC)
H A DMC68VZ328.h157 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
159 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
161 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
179 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
187 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
609 #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
617 #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
619 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
655 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
746 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
783 #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
874 #define UMISC_CLKSRC 0x4000 /* Clock Source */
1032 * LCD Pixel Clock Divider Register
1037 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1101 #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1103 #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1108 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1283 #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1284 #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
/linux-4.1.27/sound/soc/davinci/
H A Ddavinci-mcasp.h179 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
188 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
197 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
206 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
244 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
245 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
249 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
250 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
/linux-4.1.27/drivers/net/phy/
H A Ddp83640_reg.h39 #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
46 #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
62 #define PTP_RD_CLK (1<<5) /* Read PTP Clock */
63 #define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
64 #define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
65 #define PTP_ENABLE (1<<2) /* Enable PTP Clock */
66 #define PTP_DISABLE (1<<1) /* Disable PTP Clock */
67 #define PTP_RESET (1<<0) /* Reset PTP Clock */
231 #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
232 #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
233 #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
234 #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
258 #define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
260 #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
/linux-4.1.27/drivers/staging/rtl8712/
H A Drtl8712_syscfg_bitdef.h68 #define SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/
73 #define CPU_CLKSEL BIT(CPU_CLKSEL_SHT) /* System Clock select,
81 #define MAC_CLK_EN BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/
165 #define EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/
166 #define EFUSE_CLK_SEL BIT(0) /* E-Fuse Clock Select,
H A Drtl8712_efuse.c50 /* Change Efuse Clock for write action to 40MHZ */ efuse_reg_ctrl()
60 /* Change Efuse Clock for write action to 500K */ efuse_reg_ctrl()
374 /* check if E-Fuse Clock Enable and E-Fuse Clock is 40M */ r8712_efuse_pg_packet_write()
503 /* check if E-Fuse Clock Enable and E-Fuse Clock is 40M */ r8712_efuse_map_write()
/linux-4.1.27/arch/powerpc/boot/
H A Dcuboot-acadia.c26 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
34 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
35 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
36 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
37 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
H A Dcuboot-katmai.c37 /* 440SP Clock logic is all but identical to 440GX katmai_fixups()
H A Dpq2.c20 #define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
21 #define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
H A Ddcr.h84 /* 440GP Clock, PM, chip control */
145 /* 440EP Clock/Power-on Reset regs */
166 /* 440GX/405EX Clock Control reg */
/linux-4.1.27/sound/mips/
H A Dhal2.h69 /* 1=Bresenham Clock Gen 1 */
70 /* 2=Bresenham Clock Gen 2 */
71 /* 3=Bresenham Clock Gen 3 */
133 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
149 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
172 /* Clock generator CTL 1, 16 bit */
181 /* Clock generator CTL 2, 32 bit */
H A Dad1843.c50 ad1843_INIT = { 0, 15, 1 }, /* Clock Initialization Flag */
92 ad1843_C1C = { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
93 ad1843_C2C = { 20, 0, 16 }, /* Clock 2 Sample Rate Select */
94 ad1843_C3C = { 23, 0, 16 }, /* Clock 3 Sample Rate Select */
114 ad1843_C1EN = { 28, 11, 1 }, /* Clock Generator 1 Enable */
115 ad1843_C2EN = { 28, 12, 1 }, /* Clock Generator 2 Enable */
116 ad1843_C3EN = { 28, 13, 1 }, /* Clock Generator 3 Enable */
/linux-4.1.27/drivers/staging/iio/accel/
H A Dadis16240.h44 /* Clock, hour and minute */
46 /* Clock, month and day */
48 /* Clock, year */
/linux-4.1.27/drivers/clk/mvebu/
H A Ddove.c40 * SAR0[11:9] : CPU to L2 Clock divider ratio
47 * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
158 * Clock Gating Control
H A Dkirkwood.c40 * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
46 * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
207 * Clock Gating Control
231 * Clock Muxing Control
H A Darmada-370.c153 * Clock Gating Control
H A Darmada-38x.c133 * Clock Gating Control
H A Darmada-39x.c137 * Clock Gating Control
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A DdefBF518.h25 #define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
26 #define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
45 #define CKOEN 0x2000 /* Clock output control */
H A DdefBF514.h16 #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
/linux-4.1.27/sound/soc/pxa/
H A Dmmp-sspa.h75 #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */
76 #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */
79 #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */
/linux-4.1.27/drivers/media/platform/s5p-tv/
H A Dregs-sdo.h33 /* SDO Clock Control Register (SDO_CLKCON) */
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h10 * Clock identifiers.
/linux-4.1.27/include/media/
H A Domap4iss.h29 * @clk: Clock lane configuration
H A Dad9389b.h31 /* Differential Data/Clock Output Drive Strength (reg. 0xa2/0xa3) */
H A Dtvp514x.h99 * @clk_polarity: Clock polarity of the current interface.
H A Dtvp7002.h33 *@clk_polarity: Clock polarity
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h10 * Clock identifiers.
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h10 * Clock identifiers.
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h10 * Clock identifiers.
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dclock.c2 * SH-Mobile Clock Framework
H A DMakefile20 # Clock objects
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h10 * Clock identifiers.
/linux-4.1.27/sound/firewire/bebob/
H A Dbebob_terratec.c12 SND_BEBOB_CLOCK_INTERNAL, "Digital In", "Word Clock"
H A Dbebob_proc.c146 snd_iprintf(buffer, "Clock Source: %s\n", proc_read_clock()
151 snd_iprintf(buffer, "Clock Source: %s (MSU-dest: %d)\n", proc_read_clock()
/linux-4.1.27/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h10 * Clock identifiers.
/linux-4.1.27/include/linux/i2c/
H A Dbfin_twi.h77 #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
78 #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
105 #define SCLOVR 0x8000 /* Serial Clock Override */
115 #define SCLSEN 0x0080 /* Serial Clock Sense */
/linux-4.1.27/drivers/clk/
H A Dclk-max77686.c2 * clk-max77686.c - Clock driver for Maxim 77686
84 MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
H A Dclk-max77802.c2 * clk-max77802.c - Clock driver for Maxim 77802
95 MODULE_DESCRIPTION("MAXIM 77802 Clock Driver");
H A Dclk-palmas.c2 * Clock driver for Palmas device.
87 * Clock can be disabled through external pin if it is externally palmas_clks_unprepare()
224 dev_err(cinfo->dev, "Clock prep failed, %d\n", ret); palmas_clks_init_configure()
276 dev_err(&pdev->dev, "Clock config failed, %d\n", ret); palmas_clks_probe()
303 MODULE_DESCRIPTION("Clock driver for Palmas Series Devices");
H A Dclk-si570.c62 * @hw: Clock hw struct
67 * @n1: Clock divider N1
68 * @hs_div: Clock divider HSDIV
69 * @rfreq: Clock multiplier RFREQ
187 * @out_n1: Clock divider N1 (output)
188 * @out_hs_div: Clock divider HSDIV (output)
/linux-4.1.27/drivers/clk/pxa/
H A Dclk-pxa.h61 * | Clock | | / div_lp |\
66 * | Clock | --- | / div_hp |
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dlgs8gxx_priv.h64 #define TS_CLK_NORMAL 0x00 /* MPEG Clock Normal */
65 #define TS_CLK_INVERTED 0x02 /* MPEG Clock Inverted */
H A Dmb86a20s.h25 * @fclk: Clock frequency. If zero, assumes the default
H A Drtl2830.h25 * @clk: Clock frequency (4000000, 16000000, 25000000, 28800000).
H A Dlgs8gxx.h57 /* A/D Clock frequency */
H A Drtl2832.h30 * @clk: Clock frequency (4000000, 16000000, 25000000, 28800000).
H A Drtl2832_sdr.h34 * @clk: Clock frequency (4000000, 16000000, 25000000, 28800000).
/linux-4.1.27/include/video/
H A Dkyro.h32 u32 PIXCLK; /* Pixel Clock */
33 u32 HCLK; /* Hor Clock */
H A Ds1d13xxxfb.h33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
34 #define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */
35 #define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */
36 #define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */
/linux-4.1.27/arch/m32r/include/asm/
H A Ds1d13806.h24 {0x0010,0x00}, // Memory Clock Configuration Register
25 {0x0014,0x00}, // LCD Pixel Clock Configuration Register
26 {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
27 {0x001C,0x00}, // MediaPlug Clock Configuration Register
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
64 {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz)
/linux-4.1.27/sound/ppc/
H A Dsnd_ps3_reg.h338 Configures Master Clock and other master Audio Output Settings
378 Master Clock Rate 1
385 Master Clock Rate 0
392 System Clock Select 0/1
393 Selects the system clock to be used as Master Clock 0/1
431 /* Bit Clock Output Disable */
476 from bclko) used by the 3-wire Audio Output Clock, which
487 Master Clock Select
488 0 - Master Clock 0
489 1 - Master Clock 1
634 from bclko) used by the S/PDIF Output Clock, which
643 Master Clock Select
644 0 - Master Clock 0
645 1 - Master Clock 1
/linux-4.1.27/sound/soc/intel/boards/
H A Dcht_bsw_rt5645.c93 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
112 {"Headphone", NULL, "Platform Clock"},
113 {"Headset Mic", NULL, "Platform Clock"},
114 {"Int Mic", NULL, "Platform Clock"},
115 {"Ext Spk", NULL, "Platform Clock"},
H A Dcht_bsw_rt5672.c109 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
131 {"Headphone", NULL, "Platform Clock"},
132 {"Headset Mic", NULL, "Platform Clock"},
133 {"Int Mic", NULL, "Platform Clock"},
134 {"Ext Spk", NULL, "Platform Clock"},
/linux-4.1.27/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c4 * Based on Exynos Audio Subsystem Clock Controller driver:
13 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
238 MODULE_DESCRIPTION("S5PV210 Audio Subsystem Clock Controller");
H A Dclk-pll.h9 * Common Clock Framework support for all PLL's in Samsung platforms
H A Dclk-exynos5440.c9 * Common Clock Framework support for Exynos5440 SoC.
110 * Exynos5440 Clock restart notifier, handles restart functionality
/linux-4.1.27/drivers/clk/mmp/
H A Dclk.h11 /* Clock type "factor" */
40 /* Clock type "mix" */
106 /* Clock type "gate". MMP private gate */
H A Dclk-apbc.c22 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
23 #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
/linux-4.1.27/drivers/atm/
H A Dnicstarmac.c36 #define CLK_HIGH 0x0004 /* Clock high */
37 #define CLK_LOW 0x0000 /* Clock low */
87 /* Clock to read from/write to the eeprom */
/linux-4.1.27/drivers/pwm/
H A Dpwm-tipwmss.c27 #define PWMSS_CLKCONFIG 0x8 /* Clock gating reg */
28 #define PWMSS_CLKSTATUS 0xc /* Clock gating status reg */
/linux-4.1.27/drivers/tty/serial/
H A Dbfin_sport_uart.h24 #define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
30 #define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
/linux-4.1.27/drivers/power/reset/
H A Dat91-poweroff.c29 #define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */
34 #define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */
/linux-4.1.27/arch/m68k/mvme16x/
H A Drtc.c2 * Real Time Clock interface for Linux on the MVME16x
161 printk(KERN_INFO "MK48T08 Real Time Clock Driver v%s\n", RTC_VERSION); rtc_MK48T08_init()
/linux-4.1.27/arch/arm/mach-s3c24xx/include/mach/
H A Dmap.h44 /* Clock and Power management */
76 /* Clock and Power management */
/linux-4.1.27/drivers/net/ethernet/marvell/
H A Dsky2.h61 P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
62 P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */
63 P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
64 P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */
65 P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */
66 P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */
67 P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */
68 P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */
69 P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */
70 P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */
71 P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */
72 P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */
73 P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
74 P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
75 P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */
76 P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */
77 P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */
78 P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */
79 P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */
80 P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */
107 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
108 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
116 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
120 /* Bit 26..16: Release Clock on Event */
133 /* Bit 10.. 0: Mask for Gate Clock */
159 /* Bit 23..21: Release Clock on Event */
163 /* Bit 20..18: Gate Clock on Event */
191 PSM_CONFIG_REG1_PTP_CLK_SEL = 1<<29, /* PTP Clock Select */
212 PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */
520 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
521 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
536 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
595 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
617 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
619 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
621 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
622 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
625 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
626 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
1542 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1598 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1869 RX_GCLKMAC_ENA = 1<<31, /* RX MAC Clock Gating Enable */
1979 /* Clock Stretching Timeout */
1990 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h324 #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
327 #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
330 #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
447 #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
448 #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
450 #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
451 #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
452 #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
455 #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
663 #define MCCR0_ECS 0x00020000 /* External Clock Select */
664 #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
665 #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
679 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
680 #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
724 #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
770 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
773 #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
788 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
789 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
791 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
793 #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
795 #define SSCR1_ECS 0x00000020 /* External Clock Select */
796 #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
797 #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
861 * Real-Time Clock (RTC) control registers
864 * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
865 * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
866 * RTTR Real-Time Clock (RTC) Trim Register (read/write).
867 * RTSR Real-Time Clock (RTC) Status Register (read/write).
967 #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
968 #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
978 #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
1087 #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
1134 * Clock
1416 #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
1444 #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1455 #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1554 #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
1560 #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
1565 #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
1783 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
1787 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
1825 #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
H A Dbadge4.h44 #define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */
H A Dshannon.h12 #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */
/linux-4.1.27/drivers/media/pci/cx18/
H A Dcx18-i2c.c256 /* Clock select 220MHz */ init_cx18_i2c()
259 /* Clock Enable */ init_cx18_i2c()
277 /* Hw I2C1 Clock Freq ~100kHz */ init_cx18_i2c()
282 /* Hw I2C2 Clock Freq ~100kHz */ init_cx18_i2c()
/linux-4.1.27/drivers/media/usb/au0828/
H A Dau0828-reg.h62 /* I2C Clock Divider (Reg 0x202) */
/linux-4.1.27/drivers/clk/socfpga/
H A Dclk.h23 /* Clock Manager offsets */
/linux-4.1.27/drivers/clk/ti/
H A Dfixed-factor.c2 * TI Fixed Factor Clock
/linux-4.1.27/arch/x86/platform/olpc/
H A Dolpc-xo1-rtc.c2 * Support for OLPC XO-1 Real Time Clock (RTC)
/linux-4.1.27/arch/xtensa/platforms/xtfpga/include/platform/
H A Dhardware.h46 /* Clock frequency in Hz (read-only): */
/linux-4.1.27/arch/sh/kernel/cpu/sh5/
H A Dclock-sh5.c19 /* Clock, Power and Reset Controller */
/linux-4.1.27/drivers/clk/qcom/
H A Dclk-branch.h31 * Clock which can gate its output.
/linux-4.1.27/arch/mips/include/asm/mach-malta/
H A Dmc146818rtc.h20 * Motorola MC146818A-compatible Real Time Clock.
/linux-4.1.27/drivers/usb/host/
H A Dohci-nxp.c221 dev_err(&pdev->dev, "failed to acquire USB DEV Clock\n"); ohci_hcd_nxp_probe()
228 dev_err(&pdev->dev, "failed to start USB DEV Clock\n"); ohci_hcd_nxp_probe()
235 dev_err(&pdev->dev, "failed to acquire USB DEV Clock\n"); ohci_hcd_nxp_probe()
244 dev_err(&pdev->dev, "failed to start USB DEV Clock\n"); ohci_hcd_nxp_probe()
/linux-4.1.27/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 /* System Clock Control Register */
/linux-4.1.27/arch/powerpc/platforms/powernv/
H A Dopal-rtc.c2 * PowerNV Real Time Clock.
/linux-4.1.27/arch/powerpc/sysdev/
H A Drtc_cmos_setup.c2 * Setup code for PC-style Real-Time Clock.
/linux-4.1.27/arch/mips/lantiq/falcon/
H A Dsysctrl.c29 /* Clock status register */
31 /* Clock enable register */
33 /* Clock clear register */
43 /* CPU0 Clock Control Register */
/linux-4.1.27/arch/mips/ralink/
H A Dclk.c75 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); plat_time_init()
/linux-4.1.27/arch/m68k/hp300/
H A Dtime.c21 /* Clock hardware definitions */
/linux-4.1.27/arch/arm/mach-tegra/
H A Dhotplug.c28 /* Clock gate the CPU */ tegra_cpu_kill()
/linux-4.1.27/arch/arm/mach-w90x900/include/mach/
H A Dregs-clock.h17 /* Clock Control Registers */
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Ddevices.c66 /* Enable SATA Clock */ cns3xxx_ahci_init()
/linux-4.1.27/arch/arm/mach-gemini/include/mach/
H A Dhardware.h65 * UART Clock when System clk is 150MHz
/linux-4.1.27/arch/arm/mach-mmp/
H A Dclock-pxa910.c14 * APB Clock register offsets for PXA910
/linux-4.1.27/drivers/devfreq/exynos/
H A Dexynos4_bus.c160 /*** Clock Divider Data for Exynos4210 ***/
163 * Clock divider value for following
177 * Clock divider value for following
189 * Clock divider value for following
200 /*** Clock Divider Data for Exynos4212/4412 ***/
203 * Clock divider value for following
221 * Clock divider value for following
238 * Clock divider value for following
256 * Clock divider value for following
273 * Clock divider value for following
/linux-4.1.27/drivers/pci/pcie/
H A Daspm.c3 * Enabling PCIe link L0s/L1 state and Clock Power Management
56 /* Clock PM state */
57 u32 clkpm_capable:1; /* Clock PM capable? */
58 u32 clkpm_enabled:1; /* Current Clock PM state */
59 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
100 /* Disable ASPM and Clock PM */ policy_to_aspm_state()
115 /* Disable ASPM and Clock PM */ policy_to_clkpm_state()
118 /* Disable Clock PM */ policy_to_clkpm_state()
144 /* Don't enable Clock PM if the link is not Clock PM capable */ pcie_set_clkpm()
191 * All functions of a slot should have the same Slot Clock pcie_aspm_configure_common_clock()
197 /* Check downstream component if bit Slot Clock Configuration is 1 */ pcie_aspm_configure_common_clock()
202 /* Check upstream component if bit Slot Clock Configuration is 1 */ pcie_aspm_configure_common_clock()
588 /* Setup initial Clock PM state */ pcie_aspm_init_link_state()
660 /* Clock PM is for endpoint device */ pcie_aspm_exit_link_state()
/linux-4.1.27/drivers/rtc/
H A Drtc-imxdi.c48 #define DCAMR 0x08 /* Clock Alarm MSB Reg */
49 #define DCALR 0x0c /* Clock Alarm LSB Reg */
71 #define DSR_CTD (1 << 17) /* Clock tamper detected */
77 #define DSR_CAF (1 << 4) /* Clock Alarm Flag */
87 #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
547 MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
H A Drtc-digicolor.c2 * Real Time Clock driver for Conexant Digicolor
226 MODULE_DESCRIPTION("Conexant Digicolor Realtime Clock Driver (RTC)");
H A Drtc-at91rm9200.h7 * Real Time Clock (RTC) - System peripheral registers.
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dsa1111.h106 * SKCDR Clock Divider Register
107 * SKAUD Audio Clock Divider Register
108 * SKPMC PS/2 Mouse Clock Divider Register
109 * SKPTC PS/2 Track Pad Clock Divider Register
111 * SKPWM0 PWM0 Clock Register
113 * SKPWM1 PWM1 Clock Register
/linux-4.1.27/drivers/scsi/qla4xxx/
H A Dql4_nvram.c52 /* Clock in a zero, then do the start bit. */ fm93c56a_cmd()
123 * The first bit is a dummy. Clock right over it. */ fm93c56a_datain()
/linux-4.1.27/drivers/pcmcia/
H A Dyenta_socket.h71 #define CB_SKTMODE 0x01000000 /* Clock frequency has changed (clear on read) */
72 #define CB_CLKCTRLEN 0x00010000 /* Clock control enabled (RW) */
/linux-4.1.27/drivers/cpufreq/
H A Delanfreq.c40 int val80h; /* CPU Clock Speed Register */
82 u8 clockspeed_reg; /* Clock Speed Register */ elanfreq_get_cpu_frequency()
H A Dlonghaul.h51 * Clock ratio tables. Div/Mod by 10 to get ratio.
/linux-4.1.27/arch/sparc/include/asm/
H A Dfhc.h1 /* fhc.h: FHC and Clock board register definitions.
9 /* Clock board register offsets. */
/linux-4.1.27/arch/sh/include/cpu-sh4/cpu/
H A Dsh7722.h6 * MD0: CPG - Clock Mode 0->3
7 * MD1: CPG - Clock Mode 0->3
/linux-4.1.27/arch/m68k/bvme6000/
H A Drtc.c2 * Real Time Clock interface for Linux on the BVME6000
171 printk(KERN_INFO "DP8570A Real Time Clock Driver v%s\n", RTC_VERSION); rtc_DP8570A_init()
/linux-4.1.27/arch/arm/mach-orion5x/
H A Drd88f5182-setup.c248 * MPP[20] PCI Clock to MV88F5182 rd88f5182_init()
249 * MPP[21] PCI Clock to mini PCI CON11 rd88f5182_init()
/linux-4.1.27/sound/pci/ice1712/
H A Ddelta.h94 /* 0 - clock are taken from Word Clock input */
145 #define ICE1712_DELTA_1010LT_WORDCLOCK 0x80 /* sample clock source: 0 = Word Clock Input, 1 = S/PDIF Input ??? */
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/
H A Dsw.c51 * 1 - Enable ASPM without Clock Req, rtl88e_init_aspm_vars()
52 * 2 - Enable ASPM with Clock Req, rtl88e_init_aspm_vars()
53 * 3 - Alwyas Enable ASPM with Clock Req, rtl88e_init_aspm_vars()
54 * 4 - Always Enable ASPM without Clock Req. rtl88e_init_aspm_vars()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ce/
H A Dsw.c59 * 1 - Enable ASPM without Clock Req, rtl92c_init_aspm_vars()
60 * 2 - Enable ASPM with Clock Req, rtl92c_init_aspm_vars()
61 * 3 - Alwyas Enable ASPM with Clock Req, rtl92c_init_aspm_vars()
62 * 4 - Always Enable ASPM without Clock Req. rtl92c_init_aspm_vars()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
H A Dsw.c55 * 1 - Enable ASPM without Clock Req, rtl92d_init_aspm_vars()
56 * 2 - Enable ASPM with Clock Req, rtl92d_init_aspm_vars()
57 * 3 - Alwyas Enable ASPM with Clock Req, rtl92d_init_aspm_vars()
58 * 4 - Always Enable ASPM without Clock Req. rtl92d_init_aspm_vars()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ee/
H A Dsw.c55 * 1 - Enable ASPM without Clock Req, rtl92ee_init_aspm_vars()
56 * 2 - Enable ASPM with Clock Req, rtl92ee_init_aspm_vars()
57 * 3 - Alwyas Enable ASPM with Clock Req, rtl92ee_init_aspm_vars()
58 * 4 - Always Enable ASPM without Clock Req. rtl92ee_init_aspm_vars()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192se/
H A Dsw.c55 * 1 - Enable ASPM without Clock Req, rtl92s_init_aspm_vars()
56 * 2 - Enable ASPM with Clock Req, rtl92s_init_aspm_vars()
57 * 3 - Alwyas Enable ASPM with Clock Req, rtl92s_init_aspm_vars()
58 * 4 - Always Enable ASPM without Clock Req. rtl92s_init_aspm_vars()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Damplc_dio200.c97 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
125 * Clock and gate interconnection notes:
127 * 1. Clock source OUT n-1 is the output of the preceding channel on the
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723ae/
H A Dsw.c57 * 1 - Enable ASPM without Clock Req, rtl8723e_init_aspm_vars()
58 * 2 - Enable ASPM with Clock Req, rtl8723e_init_aspm_vars()
59 * 3 - Alwyas Enable ASPM with Clock Req, rtl8723e_init_aspm_vars()
60 * 4 - Always Enable ASPM without Clock Req. rtl8723e_init_aspm_vars()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/
H A Dsw.c56 * 1 - Enable ASPM without Clock Req, rtl8723be_init_aspm_vars()
57 * 2 - Enable ASPM with Clock Req, rtl8723be_init_aspm_vars()
58 * 3 - Alwyas Enable ASPM with Clock Req, rtl8723be_init_aspm_vars()
59 * 4 - Always Enable ASPM without Clock Req. rtl8723be_init_aspm_vars()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Dsw.c54 * 1 - Enable ASPM without Clock Req, rtl8821ae_init_aspm_vars()
55 * 2 - Enable ASPM with Clock Req, rtl8821ae_init_aspm_vars()
56 * 3 - Alwyas Enable ASPM with Clock Req, rtl8821ae_init_aspm_vars()
57 * 4 - Always Enable ASPM without Clock Req. rtl8821ae_init_aspm_vars()
/linux-4.1.27/drivers/clk/shmobile/
H A Dclk-r8a7778.c36 /* Clock dividers per bits 1 and 2 of MODEMR */
/linux-4.1.27/drivers/clk/versatile/
H A Dclk-realview.c2 * Clock driver for the ARM RealView boards
H A Dclk-versatile.c2 * Clock driver for the ARM Integrator/AP, Integrator/CP, Versatile AB and
/linux-4.1.27/arch/metag/kernel/
H A Dclock.c96 * @desc: Clock descriptor usually provided by machine description
/linux-4.1.27/drivers/video/fbdev/via/
H A Ddvi.c216 CR93[5] DI1 Clock Source: 1 = internal. viafb_dvi_sense()
217 CR93[4] DI1 Clock Polarity. viafb_dvi_sense()
218 CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */ viafb_dvi_sense()
237 display.CR9B[2:0] DVP1 Clock Adjust */ viafb_dvi_sense()
/linux-4.1.27/include/sound/
H A Dak4113.h98 /* Master Clock Operation Select */
100 /* Master Clock Operation Select */
102 /* Master Clock Frequency Select */
104 /* Master Clock Frequency Select */
H A Dak4114.h67 #define AK4114_CM1 (1<<5) /* Master Clock Operation Select */
68 #define AK4114_CM0 (1<<4) /* Master Clock Operation Select */
69 #define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */
70 #define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */
/linux-4.1.27/arch/sh/boards/
H A Dboard-apsh4ad0a.c82 value |= MODE_PIN0; /* Clock Mode 3 */ apsh4ad0a_mode_pins()
/linux-4.1.27/arch/avr32/mach-at32ap/include/mach/
H A Dboard.h15 * Clock rates for various on-board oscillators. The number of entries

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