Searched refs:CR0 (Results 1 - 48 of 48) sorted by relevance

/linux-4.1.27/include/linux/amba/
H A Dpl330.h21 * CR0, as the PL330 implementation might have 'holes'
/linux-4.1.27/include/xen/interface/hvm/
H A Dparams.h78 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
87 /* TSS used on Intel when CR0.PE=0. */
/linux-4.1.27/tools/testing/selftests/powerpc/switch_endian/
H A Dswitch_endian_test.S61 * It clobbers r9-r12, XER, CTR and CR0-1,5-7.
/linux-4.1.27/arch/x86/realmode/rm/
H A Dreboot.S70 * The instruction that switches to real mode by writing to CR0 must be
152 * semantics we don't have to reload the segments once CR0.PE = 0.
/linux-4.1.27/arch/x86/kernel/
H A Drelocate_kernel_32.S29 #define CR0 DATA(0x4) define
54 movl %eax, CR0(%edi)
202 movl CR0(%edi), %eax
H A Drelocate_kernel_64.S31 #define CR0 DATA(0x8) define
64 movq %rax, CR0(%r11)
198 movq CR0(%r8), %r8
H A Dprocess_32.c105 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", __show_regs()
H A Dprocess_64.c101 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds, __show_regs()
/linux-4.1.27/arch/x86/include/asm/
H A Dfpu-internal.h339 * properly paired with the CR0.TS changes!
361 * Encapsulate the CR0.TS handling together with the
427 * sets the new state of the CR0.TS bit. This is
455 /* Don't change CR0.TS if we just switch! */ switch_fpu_prepare()
478 * By the time this gets called, we've already cleared CR0.TS and
/linux-4.1.27/arch/x86/platform/efi/
H A Defi_stub_32.S60 * 3. Clear PG bit in %CR0.
/linux-4.1.27/arch/x86/boot/
H A Dvideo-mode.c132 pt &= ~0x80; /* Unlock CR0-7 */ vga_recalc_vertical()
H A Dvideo-vga.c146 out_idx(0x0c, crtc, 0x11); /* Vertical sync end, unlock CR0-7 */ vga_set_480_scanlines()
/linux-4.1.27/include/uapi/asm-generic/
H A Dtermbits.h91 #define CR0 0000000 macro
/linux-4.1.27/arch/parisc/include/uapi/asm/
H A Dtermbits.h92 #define CR0 0000000 macro
/linux-4.1.27/arch/avr32/include/uapi/asm/
H A Dtermbits.h91 #define CR0 0000000 macro
/linux-4.1.27/arch/x86/include/asm/xen/
H A Dinterface.h154 unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Dprocessor-flags.h50 * Basic CPU control in CR0
/linux-4.1.27/arch/xtensa/include/uapi/asm/
H A Dtermbits.h107 #define CR0 0000000 macro
/linux-4.1.27/arch/mn10300/include/uapi/asm/
H A Dtermbits.h92 #define CR0 0000000 macro
/linux-4.1.27/arch/powerpc/include/uapi/asm/
H A Dtermbits.h105 #define CR0 00000000 macro
/linux-4.1.27/arch/cris/include/uapi/asm/
H A Dtermbits.h93 #define CR0 0000000 macro
/linux-4.1.27/arch/frv/include/uapi/asm/
H A Dtermbits.h92 #define CR0 0000000 macro
/linux-4.1.27/arch/ia64/include/uapi/asm/
H A Dtermbits.h100 #define CR0 0000000 macro
/linux-4.1.27/arch/m32r/include/uapi/asm/
H A Dtermbits.h91 #define CR0 0000000 macro
/linux-4.1.27/arch/alpha/include/uapi/asm/
H A Dtermbits.h99 #define CR0 00000000 macro
/linux-4.1.27/drivers/pci/host/
H A Dpcie-spear13xx.c60 /* CR0 ID */
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dtermbits.h121 #define CR0 0x00000000 macro
/linux-4.1.27/arch/mips/include/uapi/asm/
H A Dtermbits.h111 #define CR0 0000000 macro
/linux-4.1.27/arch/arm/kernel/
H A Dhead-common.S140 * Read processor ID register (CP#15, CR0), and look up in the linker-built
/linux-4.1.27/arch/powerpc/kernel/
H A Dhead_32.S536 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
555 mtcrf 0x80,r3 /* Restore CR0 */
609 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
639 mtcrf 0x80,r3 /* Restore CR0 */
689 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
H A Dhead_40x.S188 * CR saved in stack frame, CR0.EQ = !SRR3.PR
H A Dentry_64.S84 * This clears CR0.SO (bit 28), which is the error indication on
/linux-4.1.27/drivers/video/fbdev/
H A Dsstfb.c879 /* the fifth time, CR0 is read */ sst_detect_att()
904 /* the fifth time, CR0 is read */ sst_detect_ti()
977 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */ sst_set_pll_att_ti()
1067 /* the fifth time, CR0 is read */ sst_set_vidmod_att_ti()
/linux-4.1.27/arch/powerpc/mm/
H A Dicswx.c267 * using CR0 acop_handle_fault()
/linux-4.1.27/include/video/
H A Dvga.h108 #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
/linux-4.1.27/drivers/dma/
H A Dpl330.c130 #define CR0 0xe00 macro
1734 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; read_dmac_config()
1739 val = readl(regs + CR0); read_dmac_config()
1749 val = readl(regs + CR0); read_dmac_config()
1755 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; read_dmac_config()
/linux-4.1.27/drivers/staging/vt6655/
H A Dmac.c332 /* restore MAC context, except CR0 */ MACbSafeSoftwareReset()
/linux-4.1.27/drivers/net/wan/lmc/
H A Dlmc_media.c935 lmc_t1_write (sc, 0x01, 0x1B); /* CR0 - primary control */ lmc_t1_init()
/linux-4.1.27/drivers/net/ethernet/via/
H A Dvia-velocity.h426 * Bits in the CR0 register
/linux-4.1.27/drivers/spi/
H A Dspi-ep93xx.c120 /* converts bits per word to CR0.DSS value */
H A Dspi-pl022.c417 * @cr0: Value of control register CR0 of SSP - on later ST variants this
2448 * CR0/CR1 register
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A Duli526x.c399 uw32(DCR0, 0); //Clear CR0 uli526x_init_one()
/linux-4.1.27/arch/x86/kvm/
H A Dvmx.c1726 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing update_transition_efer()
5300 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS handle_clts()
9283 * trap. Note that CR0.TS also needs updating - we do this later. prepare_vmcs02()
9491 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to nested_vmx_run()
9492 * CR0.PG) is 1. nested_vmx_run()
H A Dsvm.c221 VMCB_CR, /* CR0, CR3, CR4, EFER */
H A Dx86.c4987 * CR0.TS may reference the host fpu state, not the guest fpu state, emulator_get_fpu()
/linux-4.1.27/drivers/video/fbdev/sis/
H A Dinit.c3334 SiS_Pr->CCRT1CRTC[0] = ((SiS_Pr->CHTotal >> 3) - 5) & 0xff; /* CR0 */ SiS_CalcCRRegisters()
H A Dinit301.c5225 /* CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 */ SiS_SetGroup1_301()
/linux-4.1.27/drivers/staging/xgifb/
H A Dvb_setmode.c654 xgifb_reg_and(pVBInfo->P3d4, 0x11, 0x7F); /* Unlock CR0~7 */ XGI_UpdateXG21CRTC()

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