Searched refs:CP (Results 1 - 161 of 161) sorted by relevance

/linux-4.1.27/arch/c6x/boot/dts/
H A DMakefile11 quiet_cmd_cp = CP $< $@$2
/linux-4.1.27/drivers/s390/char/
H A Dvmcp.h8 * z/VMs CP offers the possibility to issue commands via the diagnose code 8
10 * returns the answer of CP.
H A Dvmcp.c7 * z/VMs CP offers the possibility to issue commands via the diagnose code 8
9 * returns the answer of CP.
11 * The idea of this driver is based on cpint from Neale Ferguson and #CP in CMS
126 * CP Programming Services SC24-6084-00
128 * VMCP_GETCODE: gives the CP return code back to user space
H A Dvmur.h18 * both in SPOOL directory control statement and in CP DEFINE statement
H A Dsclp_con.c342 * written at start of each line by VM/CP sclp_console_init()
H A Dsclp_tty.c538 * written at start of each line by VM/CP sclp_tty_init()
H A Dvmur.c168 * CP commands such as PURGE or TRANSFER, while the Linux guest is suspended.
362 * cc=1 CP paging error
/linux-4.1.27/arch/microblaze/boot/dts/
H A DMakefile14 quiet_cmd_cp = CP $< $@$2
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Darm_timer.h8 * CP, V for Versatile and R for Realview.
10 * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
/linux-4.1.27/arch/arm/mach-integrator/
H A Dcm.h24 * ARM926/946/966 Integrator/CP specific
H A Dintegrator_cp.c43 /* Base address to the CP controller */
214 .name = "Integrator/CP",
294 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
H A Dhardware.h290 #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
/linux-4.1.27/include/linux/
H A Dasn1_ber_bytecode.h82 #define _tag(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | ASN1_##TAG)
83 #define _tagn(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | TAG)
H A Df2fs_fs.h145 __le16 blk_addr; /* block index in current CP */
146 __le16 blk_count; /* Number of orphan inode blocks in CP */
147 __le32 entry_count; /* Total number of orphan nodes in current CP */
/linux-4.1.27/drivers/staging/unisys/common-spar/include/channels/
H A Dcontrolvmchannel.h75 * Commands that are initiated by the command partition (CP), by an IO or
89 CONTROLVM_BUS_CREATE = 0x101, /* CP --> SP, GP */
90 CONTROLVM_BUS_DESTROY = 0x102, /* CP --> SP, GP */
91 CONTROLVM_BUS_CONFIGURE = 0x104, /* CP --> SP */
92 CONTROLVM_BUS_CHANGESTATE = 0x105, /* CP --> SP, GP */
93 CONTROLVM_BUS_CHANGESTATE_EVENT = 0x106, /* SP, GP --> CP */
96 CONTROLVM_DEVICE_CREATE = 0x201, /* CP --> SP, GP */
97 CONTROLVM_DEVICE_DESTROY = 0x202, /* CP --> SP, GP */
98 CONTROLVM_DEVICE_CONFIGURE = 0x203, /* CP --> SP */
99 CONTROLVM_DEVICE_CHANGESTATE = 0x204, /* CP --> SP, GP */
100 CONTROLVM_DEVICE_CHANGESTATE_EVENT = 0x205, /* SP, GP --> CP */
101 CONTROLVM_DEVICE_RECONFIGURE = 0x206, /* CP --> Boot */
103 CONTROLVM_DISK_CREATE = 0x221, /* CP --> SP */
104 CONTROLVM_DISK_DESTROY = 0x222, /* CP --> SP */
105 CONTROLVM_DISK_CONFIGURE = 0x223, /* CP --> SP */
106 CONTROLVM_DISK_CHANGESTATE = 0x224, /* CP --> SP */
108 CONTROLVM_CHIPSET_INIT = 0x301, /* CP --> SP, GP */
109 CONTROLVM_CHIPSET_STOP = 0x302, /* CP --> SP, GP */
110 CONTROLVM_CHIPSET_SHUTDOWN = 0x303, /* CP --> SP */
111 CONTROLVM_CHIPSET_READY = 0x304, /* CP --> SP */
112 CONTROLVM_CHIPSET_SELFTEST = 0x305, /* CP --> SP */
280 * CP. This interrupt is used for bus level
282 * sendBusInterruptHandle is kept in CP. */
/linux-4.1.27/arch/mips/cavium-octeon/executive/
H A Docteon-model.c98 /* CP = No DFA, No crypto, No zip */ octeon_model_get_string_buffer()
101 suffix = "CP"; octeon_model_get_string_buffer()
260 /* Special case. 4 core, half cache (CP with half cache) */ octeon_model_get_string_buffer()
261 if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2)) octeon_model_get_string_buffer()
294 suffix = "CP"; octeon_model_get_string_buffer()
323 suffix = "CP"; octeon_model_get_string_buffer()
336 suffix = "CP"; octeon_model_get_string_buffer()
351 suffix = "CP"; octeon_model_get_string_buffer()
362 suffix = "CP"; octeon_model_get_string_buffer()
426 * - SUFFIX = NSP, EXP, SCP, SSP, or CP
/linux-4.1.27/include/net/iucv/
H A Diucv.h18 * CP Programming Services book, also available on the web thru
23 * from CP. The definition of each return code can be found in
24 * CP Programming Services book.
60 * and can be found in CP Programming Services.
129 * a parameter area as defined by the CP Programming Services and private
256 * Returns the result of the CP IUCV call.
274 * Returns the result of the CP IUCV call.
288 * Returns the result from the CP IUCV call.
300 * Returns the result from the CP IUCV call.
311 * Returns the result from the CP IUCV call.
323 * Returns the result from the CP IUCV call.
343 * Returns the result from the CP IUCV call.
363 * Returns the result from the CP IUCV call.
378 * Returns the result from the CP IUCV call.
395 * Returns the result from the CP IUCV call.
415 * Returns the result from the CP IUCV call.
435 * Returns the result from the CP IUCV call.
457 * Returns the result from the CP IUCV call.
/linux-4.1.27/arch/xtensa/kernel/
H A Dcoprocessor.S264 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
279 /* Retrieve previous owner. (a3 still holds CP number) */
282 addx4 a0, a3, a0 # entry for CP
287 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
295 * (a4 still holds previous owner (thread_info), a3 CP number)
314 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
H A Dsignal.c217 * reloading of the original task's CP state by the lazy restore_sigcontext()
218 * context-switching mechanisms of CP exception handling. restore_sigcontext()
/linux-4.1.27/drivers/s390/net/
H A Dsmsgiucv_app.c2 * Deliver z/VM CP special messages (SMSG) as uevents.
4 * The driver registers for z/VM CP special messages with the
44 MODULE_PARM_DESC(sender, "z/VM user ID from which CP SMSGs are accepted");
217 MODULE_DESCRIPTION("Deliver z/VM CP SMSG as uevents");
/linux-4.1.27/arch/unicore32/include/asm/
H A Dhwdef-copro.h14 * Control Register bits (CP#0 CR1)
/linux-4.1.27/arch/microblaze/boot/
H A DMakefile21 quiet_cmd_cp = CP $< $@$2
/linux-4.1.27/arch/arm/kernel/
H A Dentry-armv.S606 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
607 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
614 and r8, r0, #0x00000f00 @ mask out CP number
623 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
632 ret.w lr @ CP#0
633 W(b) do_fpe @ CP#1 (FPE)
634 W(b) do_fpe @ CP#2 (FPE)
635 ret.w lr @ CP#3
637 b crunch_task_enable @ CP#4 (MaverickCrunch)
638 b crunch_task_enable @ CP#5 (MaverickCrunch)
639 b crunch_task_enable @ CP#6 (MaverickCrunch)
641 ret.w lr @ CP#4
642 ret.w lr @ CP#5
643 ret.w lr @ CP#6
645 ret.w lr @ CP#7
646 ret.w lr @ CP#8
647 ret.w lr @ CP#9
649 W(b) do_vfp @ CP#10 (VFP)
650 W(b) do_vfp @ CP#11 (VFP)
652 ret.w lr @ CP#10 (VFP)
653 ret.w lr @ CP#11 (VFP)
655 ret.w lr @ CP#12
656 ret.w lr @ CP#13
657 ret.w lr @ CP#14 (Debug)
658 ret.w lr @ CP#15 (Control)
H A Dhead-common.S140 * Read processor ID register (CP#15, CR0), and look up in the linker-built
/linux-4.1.27/include/sound/
H A Dhda_verbs.h328 #define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
329 #define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
332 #define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
333 #define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
336 #define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
337 #define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
427 /* HDMI content protection (CP) control */
431 #define AC_CPCTRL_STATE (3<<0) /* current CP request state */
/linux-4.1.27/fs/f2fs/
H A Drecovery.c22 * 1. inode(x) | CP | inode(x) | dnode(F)
25 * 2. inode(x) | CP | inode(F) | dnode(F)
28 * 3. inode(x) | CP | dnode(F) | inode(x)
31 * 4. inode(x) | CP | dnode(F) | inode(F)
34 * 5. CP | inode(x) | dnode(F)
37 * 6. CP | inode(DF) | dnode(F)
40 * 7. CP | dnode(F) | inode(DF)
43 * 8. CP | dnode(F) | inode(x)
203 * CP | dnode(F) | inode(DF) find_fsync_dnodes()
473 * inode(x) | CP | inode(x) | dnode(F) recover_data()
H A Ddebug.c215 seq_printf(s, "[SB: 1] [CP: 2] [SIT: %d] [NAT: %d] ", stat_show()
265 seq_printf(s, "CP calls: %d\n", si->cp_count); stat_show()
H A Dcheckpoint.c113 * Readahead CP/NAT/SIT/SSA pages
567 /* Read the 1st cp block in this CP pack */ validate_checkpoint()
582 /* Read the 2nd cp block in this CP pack */ validate_checkpoint()
1028 /* Here, we only have one bio having CP pack */ do_checkpoint()
H A Df2fs.h123 * For CP/NAT/SIT/SSA readahead
554 * META FS metadata pages such as SIT, NAT, CP.
H A Dsegment.c1723 * CP calls this function, which flushes SIT entries including sit_journal,
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dirqs.h26 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
45 #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
67 #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
/linux-4.1.27/drivers/ide/
H A Dpdc202xx_old.c30 u8 AP = 0, BP = 0, CP = 0; pdc202xx_set_mode() local
35 pci_read_config_byte(dev, drive_pci + 2, &CP); pdc202xx_set_mode()
73 CP &= ~0x0f; pdc202xx_set_mode()
75 pci_write_config_byte(dev, drive_pci + 2, CP | TC); pdc202xx_set_mode()
H A Dqd65xx.h64 { 30, "01 4", 175, 405 }, /* Conner CP-3104 */
/linux-4.1.27/arch/xtensa/variants/fsf/include/variant/
H A Dtie.h17 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
/linux-4.1.27/arch/s390/include/asm/
H A Dcpcmd.h18 * cpcmd is the in-kernel interface for issuing CP commands
/linux-4.1.27/arch/s390/oprofile/
H A Dhwsampler.h34 unsigned long first_sdbt; /* @ of 1st SDB-Table for this CP*/
/linux-4.1.27/drivers/scsi/
H A Deata_generic.h202 __u8 cp_addr[4]; /* W, CP address register */
204 __u8 command; /* W, command code: [read|set] conf, send CP*/
231 __u32 cplen; /* CP length: number of valid cp bytes */
291 cp_luntar:1, /* CP is for target ROUTINE */
305 * CP command ends with error */
306 /* Additional CP info begins here */
351 __u32 cplen; /* size of CP in words */
H A Dips.c1855 /* copy in the CP */ ips_flash_firmware()
1922 /* copy in the CP */ ips_usrcmd()
/linux-4.1.27/arch/unicore32/kernel/
H A Dsleep.S167 ldm (r3 - r6), [r0]+ @ CP regs + virt stack ptr
168 mov sp, r6 @ CP regs + virt stack ptr
H A Dpuv3-core.c175 * More ones like CP and general purpose register values are preserved
H A Dentry.S405 and r8, r0, #0x00003c00 @ mask out CP number
/linux-4.1.27/drivers/gpu/drm/msm/
H A Dmsm_gpu.h32 * + a3xx or a2xx 3d core, which share a common CP (the firmware
33 * for the CP seems to implement some different PM4 packet types
/linux-4.1.27/include/media/
H A Dadv7842.h210 /* HDMI free run, CP-reg 0xBA */
217 /* SDP free run, CP-reg 0xDD */
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_cp.c1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
469 * CP control, initialization
472 /* Load the microcode for the CP */ radeon_cp_init_microcode()
567 /* Flush any pending commands to the CP. This should only be used just
582 /* Wait for the CP to go idle.
614 /* on r420, any DMA from CP to system memory while 2D is active radeon_do_cp_start()
615 * can cause a hang. workaround is to queue a CP RESYNC token radeon_do_cp_start()
643 * commands, so you must wait for the CP command stream to complete
658 * commands, so you must flush the command stream and wait for the CP
681 /* Reset the engine. This will stop the CP if it is running.
736 /* Reset the CP ring */ radeon_do_engine_reset()
739 /* The CP is no longer running after an engine reset */ radeon_do_engine_reset()
1610 /* This code will reinit the Radeon CP hardware after a resume from disc.
1686 DRM_DEBUG("while CP running\n"); radeon_cp_start()
1690 DRM_DEBUG("called with bogus CP mode (%d)\n", radeon_cp_start()
1703 /* Stop the CP. The engine must have been idled before calling this
1718 /* Flush any pending CP commands. This ensures any outstanding radeon_cp_stop()
1737 /* Finally, we can turn off the CP. If the engine isn't idle, radeon_cp_stop()
1739 * rendered before the CP is shut down. radeon_cp_stop()
1823 /* Just reset the CP ring. Called as part of an X Server engine reset.
1842 /* The CP is no longer running after an engine reset */ radeon_cp_reset()
1974 * CP command submission
H A Dr420.c211 /* RV410 and R420 can lock up if CP DMA to host memory happens r420_cp_errata_init()
215 * of the CP init, apparently. r420_cp_errata_init()
230 * at the very beginning of the CP init. r420_cp_errata_fini()
270 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); r420_startup()
286 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); r420_startup()
H A Dr520.c192 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); r520_startup()
208 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); r520_startup()
H A Devergreen_cs.c2138 DRM_ERROR("bad CP DMA\n"); evergreen_packet3_check()
2152 DRM_ERROR("CP DMA command requires dw count alignment\n"); evergreen_packet3_check()
2160 DRM_ERROR("CP DMA SAS not supported\n"); evergreen_packet3_check()
2165 DRM_ERROR("CP DMA SAIC only supported for registers\n"); evergreen_packet3_check()
2172 DRM_ERROR("bad CP DMA SRC\n"); evergreen_packet3_check()
2182 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", evergreen_packet3_check()
2190 DRM_ERROR("bad CP DMA SRC_SEL\n"); evergreen_packet3_check()
2198 DRM_ERROR("CP DMA DAS not supported\n"); evergreen_packet3_check()
2204 DRM_ERROR("CP DMA DAIC only supported for registers\n"); evergreen_packet3_check()
2210 DRM_ERROR("bad CP DMA DST\n"); evergreen_packet3_check()
2220 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", evergreen_packet3_check()
2228 DRM_ERROR("bad CP DMA DST_SEL\n"); evergreen_packet3_check()
3404 DRM_ERROR("CP DMA command requires dw count alignment\n"); evergreen_vm_packet3_check()
3415 DRM_ERROR("CP DMA Bad SRC register\n"); evergreen_vm_packet3_check()
3422 DRM_ERROR("CP DMA Bad SRC register\n"); evergreen_vm_packet3_check()
3436 DRM_ERROR("CP DMA Bad DST register\n"); evergreen_vm_packet3_check()
3443 DRM_ERROR("CP DMA Bad DST register\n"); evergreen_vm_packet3_check()
H A Dradeon_ucode.h26 /* CP */
H A Dr600_cs.c1782 DRM_ERROR("bad CP DMA\n"); r600_packet3_check()
1789 DRM_ERROR("CP DMA SAS not supported\n"); r600_packet3_check()
1793 DRM_ERROR("CP DMA SAIC only supported for registers\n"); r600_packet3_check()
1799 DRM_ERROR("bad CP DMA SRC\n"); r600_packet3_check()
1809 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", r600_packet3_check()
1819 DRM_ERROR("CP DMA DAS not supported\n"); r600_packet3_check()
1824 DRM_ERROR("CP DMA DAIC only supported for registers\n"); r600_packet3_check()
1829 DRM_ERROR("bad CP DMA DST\n"); r600_packet3_check()
1839 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", r600_packet3_check()
H A Dr300.c48 * the CP read collide with the flush somehow, or maybe the MC, hard to
401 /* stop CP */ r300_asic_reset()
420 /* resetting the CP seems to be problematic sometimes it end up r300_asic_reset()
1388 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); r300_startup()
1404 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); r300_startup()
H A Dni.c1381 * CP.
1826 /* Disable CP parsing/prefetching */ cayman_gpu_soft_reset()
2030 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); cayman_startup()
2046 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); cayman_startup()
2052 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); cayman_startup()
2489 block = "CP"; cayman_vm_decode_fault()
2522 * cayman_vm_flush - vm flush using the CP
2527 * using the CP (cayman-si).
H A Dradeon_drv.h82 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
881 * 9 CP request active
884 * 12 CP retry active
888 * 16 CP command stream busy
894 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
1026 /* CP registers */
1069 /* CP command packets */
H A Drs400.c430 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); rs400_startup()
446 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); rs400_startup()
H A Dcik.c3810 * cik_scratch_init - setup driver info for CP scratch regs
3814 * Set up the number and offset of the CP scratch registers.
3815 * NOTE: use of CP scratch registers is a legacy inferface and
3998 * cik_semaphore_ring_emit - emit a semaphore on the CP ring
4005 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
4030 * cik_copy_cpdma - copy pages using the CP DMA engine
4038 * Copy GPU paging using the CP DMA engine (CIK+).
4227 * CP.
4232 * compute jobs. The gfx CP consists of three microengines (ME):
4242 * The compute CP consists of two microengines (ME):
4250 * cik_cp_gfx_enable - enable/disable the gfx CP MEs
4271 * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
4370 /* init the CP */ cik_cp_gfx_start()
4608 * cik_cp_compute_enable - enable/disable the compute CP MEs
4637 * cik_cp_compute_load_microcode - load the compute CP ME ucode
5806 /* CP and shaders */ cik_pcie_init_compute_vmid()
5914 /* CP and shaders */ cik_pcie_gart_enable()
6082 * cik_vm_flush - cik vm flush using the CP
6087 * using the CP (CIK).
7476 /* enable CP interrupts on all rings */ cik_irq_set()
7868 * CP:
8286 case 181: /* CP EOP event */ cik_irq_process()
8287 DRM_DEBUG("IH: CP EOP\n"); cik_irq_process()
8305 case 184: /* CP Privileged reg access */ cik_irq_process()
8314 * reset the CP for gfx cik_irq_process()
8328 case 185: /* CP Privileged inst */ cik_irq_process()
8337 * reset the CP for gfx cik_irq_process()
8545 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); cik_startup()
8551 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); cik_startup()
8557 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); cik_startup()
H A Drs600.c461 /* stop CP */ rs600_asic_reset()
481 /* reset CP */ rs600_asic_reset()
998 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); rs600_startup()
1014 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); rs600_startup()
H A Dcikd.h1078 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */
1081 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
1082 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
1083 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
1752 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
H A Dr600.c1643 /* Disable CP parsing/prefetching */ r600_gpu_soft_reset()
1775 /* Disable CP parsing/prefetching */ r600_gpu_pci_config_reset()
2090 /* Setup some CP states */ r600_gpu_init()
2362 * CP & Ring
2814 * CP fences/semaphores
2866 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2873 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2902 * r600_copy_cpdma - copy pages using the CP DMA engine
2910 * Copy GPU paging using the CP DMA engine (r6xx+).
3022 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); r600_startup()
3366 * the same as the CP ring buffer, but in reverse. Rather than the CPU
4197 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); r600_irq_process()
4200 case 181: /* CP EOP event */ r600_irq_process()
4201 DRM_DEBUG("IH: CP EOP\n"); r600_irq_process()
H A Dsi.c3456 * CP.
3565 /* init the CP */ si_cp_start()
3873 /* Disable CP parsing/prefetching */ si_gpu_soft_reset()
4042 /* Disable CP parsing/prefetching */ si_gpu_pci_config_reset()
4476 DRM_ERROR("CP DMA Bad SRC register\n"); si_vm_packet3_cp_dma_check()
4483 DRM_ERROR("CP DMA Bad SRC register\n"); si_vm_packet3_cp_dma_check()
4497 DRM_ERROR("CP DMA Bad DST register\n"); si_vm_packet3_cp_dma_check()
4504 DRM_ERROR("CP DMA Bad DST register\n"); si_vm_packet3_cp_dma_check()
4901 block = "CP"; si_vm_decode_fault()
5019 block = "CP"; si_vm_decode_fault()
6102 /* enable CP interrupts on all rings */ si_irq_set()
6803 case 181: /* CP EOP event */ si_irq_process()
6804 DRM_DEBUG("IH: CP EOP\n"); si_irq_process()
6918 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); si_startup()
6924 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); si_startup()
6930 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); si_startup()
H A Dr600_cp.c351 DRM_INFO("Loading %s CP Microcode\n", chip_name); r600_cp_init_microcode()
602 /* Reset the CP ring */ r600_do_engine_reset()
605 /* The CP is no longer running after an engine reset */ r600_do_engine_reset()
2305 /* Wait for the CP to go idle.
2396 * pad the data with a Type-2 CP packet. r600_cp_dispatch_indirect()
H A Dr100.c992 /* Load the microcode for the CP */ r100_cp_init_microcode()
1123 DRM_ERROR("Failed to register debugfs file for CP !\n"); r100_cp_init()
1233 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); r100_cp_fini()
2571 /* stop CP */ r100_asic_reset()
2592 /* reset CP */ r100_asic_reset()
3752 /* Shutdown CP we shouldn't need to do that but better be safe than r100_mc_stop()
3895 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); r100_startup()
3911 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); r100_startup()
3985 * boots the new kernel. However doing our init sequence with the CP and
H A Dradeon_device.c237 * Init CP scratch register driver information (r1xx-r5xx)
262 * Allocate a CP scratch register for use by the driver (all asics).
285 * Free a CP scratch register allocated for use by the driver (all asics)
1468 * after the CP ring have chew one packet at least. Hence here we stop radeon_device_init()
H A Dcik_sdma.c46 * The programming model is very similar to the CP
49 * used by the CP. sDMA supports copying data, writing
H A Devergreen.c2969 * CP.
3948 /* Disable CP parsing/prefetching */ evergreen_gpu_soft_reset()
4058 /* Disable CP parsing/prefetching */ evergreen_gpu_pci_config_reset()
4598 /* enable CP interrupts on all rings */ evergreen_irq_set()
5398 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); evergreen_irq_process()
5401 case 181: /* CP EOP event */ evergreen_irq_process()
5402 DRM_DEBUG("IH: CP EOP\n"); evergreen_irq_process()
5524 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); evergreen_startup()
H A Dradeon_kms.c53 * the rest of the device (CP, writeback, etc.). radeon_has_atpx()
89 * parts of the chip (asic init, CP, writeback, etc.), and
H A Drs690.c707 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); rs690_startup()
723 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); rs690_startup()
H A Drv515.c539 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); rv515_startup()
555 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); rv515_startup()
H A Drv770.c1075 * CP.
1716 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); rv770_startup()
H A Dradeon.h130 /* r1xx+ has gfx CP ring */
133 /* cayman has 2 compute CP rings */
833 * CP & rings.
H A Dradeon_state.c446 * CP hardware state programming functions
871 * CP command dispatch functions
1616 * pad the data with a Type-2 CP packet. radeon_cp_dispatch_indirect()
H A Dradeon_reg.h3290 /* Registers for CP and Microcode Engine */
3381 /* CP packet types */
H A Dr300_reg.h1764 * CP type-3 packets
/linux-4.1.27/drivers/clk/versatile/
H A Dclk-versatile.c2 * Clock driver for the ARM Integrator/AP, Integrator/CP, Versatile AB and
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A Dsleep.S38 * restore the MMU and other basic CP registers saved and restart
/linux-4.1.27/arch/arm/mach-sa1100/
H A Dpm.c43 * More ones like CP and general purpose register values are preserved
/linux-4.1.27/drivers/watchdog/
H A Ddiag288_wdt.c5 * to CP.
63 MODULE_PARM_DESC(cmd, "CP command that is run when the watchdog triggers (z/VM only)");
66 MODULE_PARM_DESC(conceal, "Enable the CONCEAL CP option while the watchdog is active (z/VM only)");
/linux-4.1.27/arch/m68k/include/asm/
H A Dm68360_quicc.h187 volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
188 volatile unsigned long intr_cipr; /* CP interrupt pending reg */
189 volatile unsigned long intr_cimr; /* CP interrupt mask reg */
190 volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
227 /* CP */
H A Dm68360_regs.h37 /* quicc32 CP commands */
164 #define INTR_CP_TIMER 0x00020000 /* CP timer */
/linux-4.1.27/net/iucv/
H A Diucv.c19 * CP Programming Service, IBM document # SC24-5760
63 * and can be found in CP Programming Services.
316 * @code: identifier of IUCV call to CP.
319 * Calls CP to execute IUCV commands.
321 * Returns the result of the CP IUCV call.
876 * Returns the result of the CP IUCV call.
923 * Returns the result of the CP IUCV call.
986 * Returns the result from the CP IUCV call.
1018 * Returns the result from the CP IUCV call.
1048 * Returns the result from the CP IUCV call.
1080 * Returns the result from the CP IUCV call.
1170 * Returns the result from the CP IUCV call.
1220 * Returns the result from the CP IUCV call.
1246 * Returns the result from the CP IUCV call.
1284 * Returns the result from the CP IUCV call.
1335 * Returns the result from the CP IUCV call.
1389 * Returns the result from the CP IUCV call.
1420 * Returns the result from the CP IUCV call.
1815 * Handles external interrupts coming in from CP.
/linux-4.1.27/drivers/leds/
H A Dleds-lp5521.c74 #define LP5521_CP_MODE_OFF 0 /* Charge pump (CP) off */
75 #define LP5521_CP_MODE_BYPASS 8 /* CP forced to bypass mode */
76 #define LP5521_CP_MODE_1X5 0x10 /* CP forced to 1.5x mode */
78 #define LP5521_R_TO_BATT 0x04 /* R out: 0 = CP, 1 = Vbat */
/linux-4.1.27/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_kernel_queue.h48 * queue are equal, which means the CP has read all the submitted packets.
H A Dkfd_flat_memory.c64 * clients (CP/RLC, DMA, SHADER(ifetch, scalar, and vector ops)) to access
/linux-4.1.27/arch/arm/mm/
H A Dproc-mohawk.S357 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
375 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
395 mov r0, #0 @ don't allow CP access
396 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
H A Dproc-xsc3.S420 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
438 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
461 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
H A Dproc-xscale.S535 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
551 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
/linux-4.1.27/arch/arm/include/asm/
H A Dcp15.h7 * CR1 bits (CP#15 CR1)
/linux-4.1.27/drivers/video/fbdev/omap2/displays-new/
H A Dencoder-tpd12s015.c237 /* CT CP HPD GPIO */ tpd_probe_of()
240 dev_err(&pdev->dev, "failed to parse CT CP HPD gpio\n"); tpd_probe_of()
/linux-4.1.27/drivers/tty/
H A Dmxser.c120 { "CP-132 series", 2, },
121 { "CP-114 series", 4, },
123 { "CP-102 series", 2, MXSER_HIGHBAUD },
124 { "CP-104U series", 4, },
125 { "CP-168U series", 8, },
126 { "CP-132U series", 2, },
127 /*15*/ { "CP-134U series", 4, },
128 { "CP-104JU series", 4, },
130 { "CP-118U series", 8, },
131 { "CP-102UL series", 2, },
132 /*20*/ { "CP-102U series", 2, },
133 { "CP-118EL series", 8, },
134 { "CP-168EL series", 8, },
135 { "CP-104EL series", 4, },
139 { "CP-138U series", 8, },
141 { "CP-114UL series", 4, },
142 /*30*/ { "CP-102UF series", 2, },
143 { "CP-112UL series", 2, },
2623 /* exception....CP-102 */ mxser_probe()
H A Dmoxa.c87 "CP-204J series",
/linux-4.1.27/drivers/media/i2c/
H A Dadv7842.c766 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); adv7842_inv_register()
1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); adv7842_set_offset()
1080 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); adv7842_set_gain()
1232 /* CP */ adv7842_s_ctrl()
1282 /* status from CP block */ adv7842_g_input_status()
1291 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", adv7842_g_input_status()
1750 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ select_input()
1751 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ select_input()
1752 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ select_input()
1806 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ select_input()
1807 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ select_input()
1809 /* CP coast control */ select_input()
1915 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ adv7842_irq_enable()
1973 /* format change CP */ adv7842_isr()
1982 /* digital format CP */ adv7842_isr()
2227 /* CP block */ adv7842_cp_log_status()
2295 v4l2_info(sd, "CP free run: %s\n", adv7842_cp_log_status()
2577 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ adv7842_core_init()
H A Dadv7604.c791 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); adv76xx_inv_register()
1006 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); adv76xx_set_offset()
1036 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); adv76xx_set_gain()
1179 /* Entire chip or CP powered off */ no_power()
1248 /* CP has detected a non standard number of lines on the incoming no_lock_cp()
1702 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ select_input()
1703 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ select_input()
1704 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ select_input()
2206 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); adv76xx_log_status()
2207 v4l2_info(sd, "CP free run: %s\n", adv76xx_log_status()
2395 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ adv76xx_core_init()
2430 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ adv76xx_core_init()
2487 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2488 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2489 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2490 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2513 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
/linux-4.1.27/drivers/mfd/
H A D88pm800.c272 * CP implementation.CP does not "own" the ADC configuration device_gpadc_init()
275 * for CP to get VBAT and RF temperature readings. device_gpadc_init()
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c160 /* Tune the hystersis counters for SP and CP idle detection */ a4xx_hw_init()
222 /* CP registers */ a4xx_hw_init()
330 /* CP */
H A Dadreno_gpu.c149 * even number of qwords to avoid issue w/ CP hanging on wrap- adreno_submit()
209 /* wait for CP to drain ringbuffer: */ adreno_idle()
H A Da3xx_gpu.c165 /* Tune the hystersis counters for SP and CP idle detection: */ a3xx_hw_init()
233 /* CP registers */ a3xx_hw_init()
273 /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ a3xx_hw_init()
/linux-4.1.27/arch/xtensa/variants/dc232b/include/variant/
H A Dtie.h17 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
/linux-4.1.27/arch/ia64/sn/pci/pcibr/
H A Dpcibr_provider.c242 * Provider entries for PIC/CP
H A Dpcibr_dma.c321 * above code, and so the following code is PIC/CP centric. sn_dma_flush()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dsleep.S129 @ other CP registers instead.
H A Dpxa25x.c229 * More ones like CP and general purpose register values are preserved
H A Dpxa27x.c268 * More ones like CP and general purpose register values are preserved
/linux-4.1.27/arch/arm/mach-mmp/
H A Dpxa910.c124 * UART1 - Slow UART (can be used both by AP and CP)
/linux-4.1.27/drivers/staging/rtl8712/
H A Dusb_halinit.c133 /* Engineer Packet CP test Enable */ r8712_usb_hal_bus_init()
215 /* Engineer Packet CP test Enable */ r8712_usb_hal_bus_init()
/linux-4.1.27/drivers/staging/rtl8188eu/include/
H A Drtl8188e_hal.h162 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
180 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
/linux-4.1.27/tools/power/cpupower/
H A DMakefile84 CP = cp -fpR macro
265 $(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/
/linux-4.1.27/drivers/net/wan/
H A Dhdlc_ppp.c303 SCJ: RUC must supply CP packet len and data */ ppp_cp_event()
466 if (len < sizeof(struct cp_header) /* no complete CP header? */ || ppp_rx()
472 /* HDLC and CP headers stripped from skb */ ppp_rx()
H A Dwanxlfw.S94 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
95 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
96 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
470 bsetl #31, (%d1) // CP go ahead
/linux-4.1.27/arch/sparc/kernel/
H A Dpcic.c10 * CP-1200 by Eric Brower.
152 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
770 * XXX On CP-1200 PCI #SERR may happen, we do not know pcic_nmi()
H A Dsetup_32.c284 sparc_cpu_model = sun4m; /* CP-1200 with PROM 2.30 -E */ sparc32_start_kernel()
/linux-4.1.27/drivers/net/wireless/b43/
H A Dradio_2055.h62 #define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */
64 #define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */
H A Dphy_lp.h620 #define B2063_PLL_JTAG_PLL_CP1 B43_LP_RADIO(0x067) /* PLL JTAG PLL CP 1 */
621 #define B2063_PLL_JTAG_PLL_CP2 B43_LP_RADIO(0x068) /* PLL JTAG PLL CP 2 */
622 #define B2063_PLL_JTAG_PLL_CP3 B43_LP_RADIO(0x069) /* PLL JTAG PLL CP 3 */
623 #define B2063_PLL_JTAG_PLL_CP4 B43_LP_RADIO(0x06A) /* PLL JTAG PLL CP 4 */
/linux-4.1.27/sound/soc/intel/atom/
H A Dsst-mfld-dsp.h258 u64 ring_buffer_counter; /* PB/CP: Bytes copied from/to DDR. */
259 u64 hardware_counter; /* PB/CP: Bytes DMAed to/from SSP. */
/linux-4.1.27/drivers/net/can/cc770/
H A Dcc770_platform.c259 {.compatible = "intc,82527"}, /* AN82527 from Intel CP */
/linux-4.1.27/drivers/net/ethernet/mellanox/mlx5/core/
H A Dcq.c124 mlx5_core_dbg(dev, "failed adding CP 0x%x to debug file system\n", mlx5_core_create_cq()
/linux-4.1.27/drivers/regulator/
H A Darizona-micsupp.c55 dev_err(arizona->dev, "Failed to read CP state: %d\n", ret); arizona_micsupp_check_cp()
H A Dmax8998.c600 .name = "EN32KHz-CP",
/linux-4.1.27/drivers/staging/lustre/lustre/ldlm/
H A Dldlm_internal.h128 int type; /* LDLM_{CP,BL,GL}_CALLBACK */
H A Dldlm_flock.c620 /* CP AST RPC: lock get granted, wake it up */ ldlm_flock_completion_ast()
/linux-4.1.27/arch/xtensa/variants/dc233c/include/variant/
H A Dtie.h36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dtiocp.h180 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
/linux-4.1.27/arch/arm/mach-omap1/
H A Dpm.h173 * More ones like CP and general purpose register values are preserved
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A Dde2104x.c101 #define TX_BUFFS_AVAIL(CP) \
102 (((CP)->tx_tail <= (CP)->tx_head) ? \
103 (CP)->tx_tail + (DE_TX_RING_SIZE - 1) - (CP)->tx_head : \
104 (CP)->tx_tail - (CP)->tx_head - 1)
/linux-4.1.27/drivers/net/ethernet/realtek/
H A D8139cp.c115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
/linux-4.1.27/drivers/media/tuners/
H A Dtda827x.c212 /* correct CP value */ tda827xo_set_params()
627 /* correct CP value */ tda827xa_set_params()
/linux-4.1.27/drivers/video/fbdev/
H A Dw100fb.h53 /* Block CP Start: */
58 /* Block CP End: */
H A Dsh_mobile_hdmi.c618 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current, sh_hdmi_phy_config()
625 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current, sh_hdmi_phy_config()
/linux-4.1.27/drivers/media/rc/
H A Dnuvoton-cir.c150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); cir_dump_regs()
507 * set carrier on 2 registers: CP & CC
508 * always set CP as 0x81
/linux-4.1.27/drivers/net/wireless/iwlwifi/
H A Diwl-eeprom-read.c177 /* OTP only valid for CP/PP and after */ iwl_nvm_is_otp()
/linux-4.1.27/drivers/staging/rtl8723au/include/
H A Drtl8723a_hal.h196 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
/linux-4.1.27/drivers/s390/block/
H A Ddasd_fba.c519 len = sprintf(page, PRINTK_HEADER " Related CP in req: %p\n", req); dasd_fba_dump_sense()
H A Ddasd_eckd.c1501 * Build CP for Perform Subsystem Function - SSC.
4208 " Related CP in req: %p\n", req); dasd_eckd_dump_sense_ccw()
/linux-4.1.27/drivers/staging/rtl8188eu/core/
H A Drtw_efuse.c506 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */ Efuse_PgPacketRead()
/linux-4.1.27/drivers/gpu/drm/bridge/
H A Dps8622.c208 /* HPD CP toggle enable */ ps8622_send_config()
/linux-4.1.27/sound/pci/hda/
H A Dhda_proc.c757 snd_iprintf(buffer, " CP"); print_codec_info()
H A Dpatch_hdmi.c1212 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", hdmi_non_intrinsic_event()
/linux-4.1.27/drivers/media/pci/zoran/
H A Dzr36060.c673 ///*CP*/ reg = (zr->params.norm == 1 ? 57 : 68); zr36060_set_video()
H A Dzoran_device.c1593 /*CP*/ // btwrite(IRQ_MASK, ZR36057_ICR); // Enable Vsync interrupts too. SM WHY ? LP zoran_init_hardware()
/linux-4.1.27/fs/nilfs2/
H A Dcpfile.c873 /* CP number is invalid if it's zero or larger than the nilfs_cpfile_is_snapshot()
H A Dsegment.c2484 "CP frequency < %lu seconds\n", nilfs_segctor_thread()
/linux-4.1.27/include/uapi/drm/
H A Dradeon_drm.h1021 /* query if CP DMA is supported on the compute ring */
/linux-4.1.27/drivers/staging/dgap/
H A Ddgap.h345 #ifdef CP
/linux-4.1.27/arch/arm64/kvm/
H A Dsys_regs.c814 kvm_err("Unsupported guest CP%d access at: %08lx\n", unhandled_cp_access()
/linux-4.1.27/sound/pci/emu10k1/
H A Demu10k1x.c984 * CP = 1 (Copyright unasserted) snd_emu10k1x_create()
H A Demu10k1_main.c2020 * CP = 1 (Copyright unasserted) snd_emu10k1_create()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/
H A Dreg.h634 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/
H A Dreg.h628 * dummy 7 bytes frome CP test
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Dreg.h656 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
/linux-4.1.27/sound/pci/ca0106/
H A Dca0106_main.c1486 * CP = 1 (Copyright unasserted) ca0106_init_chip()
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
H A Dcommands.h3945 * bit1: CP leave channel with CTS
3946 * bit2: CP leave channel qith Quiet
/linux-4.1.27/drivers/gpu/drm/i915/
H A Di915_irq.c1987 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); cpt_irq_handler()
1990 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); cpt_irq_handler()
H A Dintel_dp.c4079 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); intel_dp_check_link_status()
H A Di915_reg.h2145 * every way. It is not accessible from the CP register read instructions.
/linux-4.1.27/drivers/dma/ppc4xx/
H A Dadma.c92 /* Pointer to DMA0, DMA1 CP/CS FIFO */
4475 * <fsiz> register (because there are two FIFOs for each DMA: CP and CS) ppc440spe_configure_raid_devices()
/linux-4.1.27/drivers/block/
H A Dfloppy.c424 * This is the same as the Sharp MZ-80 5.25" CP/M disk format, except that the
432 * is 1 (represented by 0x00<<2). For some CP/M and music sampler
/linux-4.1.27/drivers/staging/lustre/lustre/osc/
H A Dosc_request.c2202 /* Let CP AST to grant the lock first. */ osc_enqueue_interpret()
/linux-4.1.27/arch/x86/kernel/cpu/
H A Dperf_event_intel.c2428 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with hsw_hw_config()
/linux-4.1.27/sound/pci/
H A Dvia82xx.c1583 chip->intr_mask = 0x77; /* FLAG | EOL for PB, CP, FM */ snd_via686_pcm_new()
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h4439 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4959 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5458 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
/linux-4.1.27/drivers/media/pci/bt8xx/
H A Dbttv-cards.c1074 .name = "Prolink PV-BT878P+4E / PixelView PlayTV PAK / Lenco MXTV-9578 CP",
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dcnic.c4810 /* Set the CP and COM doorbells. These two processors polls the cnic_start_bnx2_hw()
/linux-4.1.27/drivers/infiniband/hw/nes/
H A Dnes_verbs.c2593 nes_debug(NES_DBG_MR, "Attempting to allocate CP PBL memory"); nes_reg_user_mr()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Ddrxk_hard.c3773 /* Mandatory fix, always stop CP, required to set spl offset back to set_dvbt()

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