Searched refs:B43_PHY_CCK (Results 1 - 5 of 5) sorted by relevance

/linux-4.1.27/drivers/net/wireless/b43/
H A Dphy_lp.h8 #define B43_LPPHY_B_VERSION B43_PHY_CCK(0x00) /* B PHY version */
9 #define B43_LPPHY_B_BBCONFIG B43_PHY_CCK(0x01) /* B PHY BBConfig */
10 #define B43_LPPHY_B_RX_STAT0 B43_PHY_CCK(0x04) /* B PHY RX Status0 */
11 #define B43_LPPHY_B_RX_STAT1 B43_PHY_CCK(0x05) /* B PHY RX Status1 */
12 #define B43_LPPHY_B_CRS_THRESH B43_PHY_CCK(0x06) /* B PHY CRS Thresh */
13 #define B43_LPPHY_B_TXERROR B43_PHY_CCK(0x07) /* B PHY TxError */
14 #define B43_LPPHY_B_CHANNEL B43_PHY_CCK(0x08) /* B PHY Channel */
15 #define B43_LPPHY_B_WORKAROUND B43_PHY_CCK(0x09) /* B PHY workaround */
16 #define B43_LPPHY_B_TEST B43_PHY_CCK(0x0A) /* B PHY Test */
17 #define B43_LPPHY_B_FOURWIRE_ADDR B43_PHY_CCK(0x0B) /* B PHY Fourwire Address */
18 #define B43_LPPHY_B_FOURWIRE_DATA_HI B43_PHY_CCK(0x0C) /* B PHY Fourwire Data Hi */
19 #define B43_LPPHY_B_FOURWIRE_DATA_LO B43_PHY_CCK(0x0D) /* B PHY Fourwire Data Lo */
20 #define B43_LPPHY_B_BIST_STAT B43_PHY_CCK(0x0E) /* B PHY Bist Status */
21 #define B43_LPPHY_PA_RAMP_TX_TO B43_PHY_CCK(0x10) /* PA Ramp TX Timeout */
22 #define B43_LPPHY_RF_SYNTH_DC_TIMER B43_PHY_CCK(0x11) /* RF Synth DC Timer */
23 #define B43_LPPHY_PA_RAMP_TX_TIME_IN B43_PHY_CCK(0x12) /* PA ramp TX Time in */
24 #define B43_LPPHY_RX_FILTER_TIME_IN B43_PHY_CCK(0x13) /* RX Filter Time in */
25 #define B43_LPPHY_PLL_COEFF_S B43_PHY_CCK(0x18) /* PLL Coefficient(s) */
26 #define B43_LPPHY_PLL_OUT B43_PHY_CCK(0x19) /* PLL Out */
27 #define B43_LPPHY_RSSI_THRES B43_PHY_CCK(0x20) /* RSSI Threshold */
28 #define B43_LPPHY_IQ_THRES_HH B43_PHY_CCK(0x21) /* IQ Threshold HH */
29 #define B43_LPPHY_IQ_THRES_H B43_PHY_CCK(0x22) /* IQ Threshold H */
30 #define B43_LPPHY_IQ_THRES_L B43_PHY_CCK(0x23) /* IQ Threshold L */
31 #define B43_LPPHY_IQ_THRES_LL B43_PHY_CCK(0x24) /* IQ Threshold LL */
32 #define B43_LPPHY_AGC_GAIN B43_PHY_CCK(0x25) /* AGC Gain */
33 #define B43_LPPHY_LNA_GAIN_RANGE B43_PHY_CCK(0x26) /* LNA Gain Range */
34 #define B43_LPPHY_JSSI B43_PHY_CCK(0x27) /* JSSI */
35 #define B43_LPPHY_TSSI_CTL B43_PHY_CCK(0x28) /* TSSI Control */
36 #define B43_LPPHY_TSSI B43_PHY_CCK(0x29) /* TSSI */
37 #define B43_LPPHY_TR_LOSS B43_PHY_CCK(0x2A) /* TR Loss */
38 #define B43_LPPHY_LO_LEAKAGE B43_PHY_CCK(0x2B) /* LO Leakage */
39 #define B43_LPPHY_LO_RSSIACC B43_PHY_CCK(0x2C) /* LO RSSIAcc */
40 #define B43_LPPHY_LO_IQ_MAG_ACC B43_PHY_CCK(0x2D) /* LO IQ Mag Acc */
41 #define B43_LPPHY_TX_DCOFFSET1 B43_PHY_CCK(0x2E) /* TX DCOffset1 */
42 #define B43_LPPHY_TX_DCOFFSET2 B43_PHY_CCK(0x2F) /* TX DCOffset2 */
43 #define B43_LPPHY_SYNCPEAKCNT B43_PHY_CCK(0x30) /* SyncPeakCnt */
44 #define B43_LPPHY_SYNCFREQ B43_PHY_CCK(0x31) /* SyncFreq */
45 #define B43_LPPHY_SYNCDIVERSITYCTL B43_PHY_CCK(0x32) /* SyncDiversityControl */
46 #define B43_LPPHY_PEAKENERGYL B43_PHY_CCK(0x33) /* PeakEnergyL */
47 #define B43_LPPHY_PEAKENERGYH B43_PHY_CCK(0x34) /* PeakEnergyH */
48 #define B43_LPPHY_SYNCCTL B43_PHY_CCK(0x35) /* SyncControl */
49 #define B43_LPPHY_DSSSSTEP B43_PHY_CCK(0x38) /* DsssStep */
50 #define B43_LPPHY_DSSSWARMUP B43_PHY_CCK(0x39) /* DsssWarmup */
51 #define B43_LPPHY_DSSSSIGPOW B43_PHY_CCK(0x3D) /* DsssSigPow */
52 #define B43_LPPHY_SFDDETECTBLOCKTIME B43_PHY_CCK(0x40) /* SfdDetectBlockTIme */
53 #define B43_LPPHY_SFDTO B43_PHY_CCK(0x41) /* SFDTimeOut */
54 #define B43_LPPHY_SFDCTL B43_PHY_CCK(0x42) /* SFDControl */
55 #define B43_LPPHY_RXDBG B43_PHY_CCK(0x43) /* rxDebug */
56 #define B43_LPPHY_RX_DELAYCOMP B43_PHY_CCK(0x44) /* RX DelayComp */
57 #define B43_LPPHY_CRSDROPOUTTO B43_PHY_CCK(0x45) /* CRSDropoutTimeout */
58 #define B43_LPPHY_PSEUDOSHORTTO B43_PHY_CCK(0x46) /* PseudoShortTimeout */
59 #define B43_LPPHY_PR3931 B43_PHY_CCK(0x47) /* PR3931 */
60 #define B43_LPPHY_DSSSCOEFF1 B43_PHY_CCK(0x48) /* DSSSCoeff1 */
61 #define B43_LPPHY_DSSSCOEFF2 B43_PHY_CCK(0x49) /* DSSSCoeff2 */
62 #define B43_LPPHY_CCKCOEFF1 B43_PHY_CCK(0x4A) /* CCKCoeff1 */
63 #define B43_LPPHY_CCKCOEFF2 B43_PHY_CCK(0x4B) /* CCKCoeff2 */
64 #define B43_LPPHY_TRCORR B43_PHY_CCK(0x4C) /* TRCorr */
65 #define B43_LPPHY_ANGLESCALE B43_PHY_CCK(0x4D) /* AngleScale */
66 #define B43_LPPHY_OPTIONALMODES2 B43_PHY_CCK(0x4F) /* OptionalModes2 */
67 #define B43_LPPHY_CCKLMSSTEPSIZE B43_PHY_CCK(0x50) /* CCKLMSStepSize */
68 #define B43_LPPHY_DFEBYPASS B43_PHY_CCK(0x51) /* DFEBypass */
69 #define B43_LPPHY_CCKSTARTDELAYLONG B43_PHY_CCK(0x52) /* CCKStartDelayLong */
70 #define B43_LPPHY_CCKSTARTDELAYSHORT B43_PHY_CCK(0x53) /* CCKStartDelayShort */
71 #define B43_LPPHY_PPROCCHDELAY B43_PHY_CCK(0x54) /* PprocChDelay */
72 #define B43_LPPHY_PPROCONOFF B43_PHY_CCK(0x55) /* PProcOnOff */
73 #define B43_LPPHY_LNAGAINTWOBIT10 B43_PHY_CCK(0x5B) /* LNAGainTwoBit10 */
74 #define B43_LPPHY_LNAGAINTWOBIT32 B43_PHY_CCK(0x5C) /* LNAGainTwoBit32 */
75 #define B43_LPPHY_OPTIONALMODES B43_PHY_CCK(0x5D) /* OptionalModes */
76 #define B43_LPPHY_B_RX_STAT2 B43_PHY_CCK(0x5E) /* B PHY RX Status2 */
77 #define B43_LPPHY_B_RX_STAT3 B43_PHY_CCK(0x5F) /* B PHY RX Status3 */
78 #define B43_LPPHY_PWDNDACDELAY B43_PHY_CCK(0x63) /* pwdnDacDelay */
79 #define B43_LPPHY_FINEDIGIGAIN_CTL B43_PHY_CCK(0x67) /* FineDigiGain Control */
80 #define B43_LPPHY_LG2GAINTBLLNA8 B43_PHY_CCK(0x68) /* Lg2GainTblLNA8 */
81 #define B43_LPPHY_LG2GAINTBLLNA28 B43_PHY_CCK(0x69) /* Lg2GainTblLNA28 */
82 #define B43_LPPHY_GAINTBLLNATRSW B43_PHY_CCK(0x6A) /* GainTblLNATrSw */
83 #define B43_LPPHY_PEAKENERGY B43_PHY_CCK(0x6B) /* PeakEnergy */
84 #define B43_LPPHY_LG2INITGAIN B43_PHY_CCK(0x6C) /* lg2InitGain */
85 #define B43_LPPHY_BLANKCOUNTLNAPGA B43_PHY_CCK(0x6D) /* BlankCountLnaPga */
86 #define B43_LPPHY_LNAGAINTWOBIT54 B43_PHY_CCK(0x6E) /* LNAGainTwoBit54 */
87 #define B43_LPPHY_LNAGAINTWOBIT76 B43_PHY_CCK(0x6F) /* LNAGainTwoBit76 */
88 #define B43_LPPHY_JSSICTL B43_PHY_CCK(0x70) /* JSSIControl */
89 #define B43_LPPHY_LG2GAINTBLLNA44 B43_PHY_CCK(0x71) /* Lg2GainTblLNA44 */
90 #define B43_LPPHY_LG2GAINTBLLNA62 B43_PHY_CCK(0x72) /* Lg2GainTblLNA62 */
H A Dphy_g.h8 #define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
9 #define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
10 #define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
14 #define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
15 #define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
16 #define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
17 #define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
18 #define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
19 #define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
20 #define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
21 #define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
H A Dlo.c398 sav->phy_cck_14 = b43_phy_read(dev, B43_PHY_CCK(0x14)); lo_measure_setup()
404 b43_phy_set(dev, B43_PHY_CCK(0x14), 0x200); lo_measure_setup()
408 b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410); lo_measure_setup()
409 b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820); lo_measure_setup()
418 sav->phy_cck_3E = b43_phy_read(dev, B43_PHY_CCK(0x3E)); lo_measure_setup()
435 b43_phy_write(dev, B43_PHY_CCK(0x3E), 0); lo_measure_setup()
442 sav->phy_cck_2A = b43_phy_read(dev, B43_PHY_CCK(0x2A)); lo_measure_setup()
451 sav->phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); lo_measure_setup()
452 sav->phy_cck_06 = b43_phy_read(dev, B43_PHY_CCK(0x06)); lo_measure_setup()
453 b43_phy_write(dev, B43_PHY_CCK(0x30), 0x00FF); lo_measure_setup()
454 b43_phy_write(dev, B43_PHY_CCK(0x06), 0x3F3F); lo_measure_setup()
463 (phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_CCK(0x2E); lo_measure_setup()
471 b43_phy_write(dev, B43_PHY_CCK(0x2A), 0x8A3); lo_measure_setup()
475 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1003); lo_measure_setup()
477 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802); lo_measure_setup()
483 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0); lo_measure_setup()
494 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078); lo_measure_setup()
521 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078); lo_measure_restore()
523 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078); lo_measure_restore()
525 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0202); lo_measure_restore()
527 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0101); lo_measure_restore()
531 b43_phy_write(dev, B43_PHY_CCK(0x2A), sav->phy_cck_2A); lo_measure_restore()
543 b43_phy_write(dev, B43_PHY_CCK(0x30), sav->phy_cck_30); lo_measure_restore()
544 b43_phy_write(dev, B43_PHY_CCK(0x06), sav->phy_cck_06); lo_measure_restore()
553 b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E); lo_measure_restore()
561 b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14); lo_measure_restore()
H A Dphy_g.c1273 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A)); b43_radio_init2050()
1274 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59)); b43_radio_init2050()
1275 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58)); b43_radio_init2050()
1278 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); b43_radio_init2050()
1281 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF); b43_radio_init2050()
1324 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40); b43_radio_init2050()
1340 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403); b43_radio_init2050()
1354 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); b43_radio_init2050()
1357 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480); b43_radio_init2050()
1358 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); b43_radio_init2050()
1359 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); b43_radio_init2050()
1385 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); b43_radio_init2050()
1396 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); b43_radio_init2050()
1405 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80); b43_radio_init2050()
1406 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); b43_radio_init2050()
1407 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); b43_radio_init2050()
1436 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); b43_radio_init2050()
1457 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A); b43_radio_init2050()
1458 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59); b43_radio_init2050()
1459 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58); b43_radio_init2050()
1466 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30); b43_radio_init2050()
1726 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A)); b43_calc_loopback_gain()
1727 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59)); b43_calc_loopback_gain()
1728 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58)); b43_calc_loopback_gain()
1729 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A)); b43_calc_loopback_gain()
1730 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03)); b43_calc_loopback_gain()
1733 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B)); b43_calc_loopback_gain()
1758 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); b43_calc_loopback_gain()
1759 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); b43_calc_loopback_gain()
1760 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); b43_calc_loopback_gain()
1762 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); b43_calc_loopback_gain()
1767 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40); b43_calc_loopback_gain()
1783 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01); b43_calc_loopback_gain()
1784 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800); b43_calc_loopback_gain()
1833 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]); b43_calc_loopback_gain()
1834 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]); b43_calc_loopback_gain()
1835 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]); b43_calc_loopback_gain()
1836 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]); b43_calc_loopback_gain()
1837 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]); b43_calc_loopback_gain()
1840 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]); b43_calc_loopback_gain()
2052 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); b43_phy_initg()
2055 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); b43_phy_initg()
2057 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); b43_phy_initg()
2059 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101); b43_phy_initg()
2061 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202); b43_phy_initg()
H A Dphy_common.h24 #define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE) macro

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