Searched refs:APMU_SDH0 (Results 1 – 7 of 7) sorted by relevance
| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 42 #define APMU_SDH0 0x54 macro
182 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
198 …{PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh…
|
| D | clk-of-pxa910.c | 40 #define APMU_SDH0 0x54 macro
184 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
200 …{PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh…
|
| D | clk-pxa910.c | 38 #define APMU_SDH0 0x54 macro
266 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); in pxa910_clk_init()
270 apmu_base + APMU_SDH0, 0x1b, &clk_lock); in pxa910_clk_init()
|
| D | clk-mmp2.c | 44 #define APMU_SDH0 0x54 macro
337 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); in mmp2_clk_init()
341 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, in mmp2_clk_init()
345 clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, in mmp2_clk_init()
|
| D | clk-of-mmp2.c | 46 #define APMU_SDH0 0x54 macro
224 …{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sd…
245 sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; in mmp2_axi_periph_clk_init()
|
| D | clk-pxa168.c | 40 #define APMU_SDH0 0x54 macro
291 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
294 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, in pxa168_clk_init()
|
| /linux-4.1.27/arch/arm/mach-mmp/ |
| D | clock-mmp2.c | 42 #define APMU_SDH0 APMU_REG(0x054) macro
|