Searched refs:APBC_UART1 (Results 1 – 9 of 9) sorted by relevance
| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 29 #define APBC_UART1 0x4 macro
126 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
147 …{PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &u…
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| D | clk-of-pxa910.c | 29 #define APBC_UART1 0x4 macro
122 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
142 …{PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &u…
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| D | clk-pxa910.c | 27 #define APBC_UART1 0x4 macro
220 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in pxa910_clk_init()
225 apbc_base + APBC_UART1, 10, 0, &clk_lock); in pxa910_clk_init()
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| D | clk-of-mmp2.c | 34 #define APBC_UART1 0x30 macro
141 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
166 …{MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uar…
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| D | clk-pxa168.c | 27 #define APBC_UART1 0x4 macro
215 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
220 apbc_base + APBC_UART1, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 32 #define APBC_UART1 0x30 macro
264 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in mmp2_clk_init()
269 apbc_base + APBC_UART1, 10, 0, &clk_lock); in mmp2_clk_init()
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| /linux-4.1.27/arch/arm/mach-mmp/ |
| D | clock-pxa910.c | 17 #define APBC_UART1 APBC_REG(0x004) macro
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| D | clock-pxa168.c | 16 #define APBC_UART1 APBC_REG(0x000) macro
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| D | clock-mmp2.c | 22 #define APBC_UART1 APBC_REG(0x02c) macro
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