1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213 };
214
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216 SH_ETH_OFFSET_DEFAULTS,
217
218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
258 [RMIIMODE] = 0x026c,
259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261 };
262
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264 SH_ETH_OFFSET_DEFAULTS,
265
266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315 };
316
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318 SH_ETH_OFFSET_DEFAULTS,
319
320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
404 };
405
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
sh_eth_write(struct net_device * ndev,u32 data,int enum_index)409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410 {
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418 }
419
sh_eth_read(struct net_device * ndev,int enum_index)420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421 {
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429 }
430
sh_eth_is_gether(struct sh_eth_private * mdp)431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
432 {
433 return mdp->reg_offset == sh_eth_offset_gigabit;
434 }
435
sh_eth_is_rz_fast_ether(struct sh_eth_private * mdp)436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
437 {
438 return mdp->reg_offset == sh_eth_offset_fast_rz;
439 }
440
sh_eth_select_mii(struct net_device * ndev)441 static void sh_eth_select_mii(struct net_device *ndev)
442 {
443 u32 value = 0x0;
444 struct sh_eth_private *mdp = netdev_priv(ndev);
445
446 switch (mdp->phy_interface) {
447 case PHY_INTERFACE_MODE_GMII:
448 value = 0x2;
449 break;
450 case PHY_INTERFACE_MODE_MII:
451 value = 0x1;
452 break;
453 case PHY_INTERFACE_MODE_RMII:
454 value = 0x0;
455 break;
456 default:
457 netdev_warn(ndev,
458 "PHY interface mode was not setup. Set to MII.\n");
459 value = 0x1;
460 break;
461 }
462
463 sh_eth_write(ndev, value, RMII_MII);
464 }
465
sh_eth_set_duplex(struct net_device * ndev)466 static void sh_eth_set_duplex(struct net_device *ndev)
467 {
468 struct sh_eth_private *mdp = netdev_priv(ndev);
469
470 if (mdp->duplex) /* Full */
471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
472 else /* Half */
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
474 }
475
476 /* There is CPU dependent code */
sh_eth_set_rate_r8a777x(struct net_device * ndev)477 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
478 {
479 struct sh_eth_private *mdp = netdev_priv(ndev);
480
481 switch (mdp->speed) {
482 case 10: /* 10BASE */
483 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
484 break;
485 case 100:/* 100BASE */
486 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
487 break;
488 default:
489 break;
490 }
491 }
492
493 /* R8A7778/9 */
494 static struct sh_eth_cpu_data r8a777x_data = {
495 .set_duplex = sh_eth_set_duplex,
496 .set_rate = sh_eth_set_rate_r8a777x,
497
498 .register_type = SH_ETH_REG_FAST_RCAR,
499
500 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
501 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
502 .eesipr_value = 0x01ff009f,
503
504 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
505 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
506 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
507 EESR_ECI,
508 .fdr_value = 0x00000f0f,
509
510 .apr = 1,
511 .mpr = 1,
512 .tpauser = 1,
513 .hw_swap = 1,
514 };
515
516 /* R8A7790/1 */
517 static struct sh_eth_cpu_data r8a779x_data = {
518 .set_duplex = sh_eth_set_duplex,
519 .set_rate = sh_eth_set_rate_r8a777x,
520
521 .register_type = SH_ETH_REG_FAST_RCAR,
522
523 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
524 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
525 .eesipr_value = 0x01ff009f,
526
527 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
528 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
529 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
530 EESR_ECI,
531 .fdr_value = 0x00000f0f,
532
533 .trscer_err_mask = DESC_I_RINT8,
534
535 .apr = 1,
536 .mpr = 1,
537 .tpauser = 1,
538 .hw_swap = 1,
539 .rmiimode = 1,
540 };
541
sh_eth_set_rate_sh7724(struct net_device * ndev)542 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
543 {
544 struct sh_eth_private *mdp = netdev_priv(ndev);
545
546 switch (mdp->speed) {
547 case 10: /* 10BASE */
548 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
549 break;
550 case 100:/* 100BASE */
551 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
552 break;
553 default:
554 break;
555 }
556 }
557
558 /* SH7724 */
559 static struct sh_eth_cpu_data sh7724_data = {
560 .set_duplex = sh_eth_set_duplex,
561 .set_rate = sh_eth_set_rate_sh7724,
562
563 .register_type = SH_ETH_REG_FAST_SH4,
564
565 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
566 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
567 .eesipr_value = 0x01ff009f,
568
569 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
570 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
571 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
572 EESR_ECI,
573
574 .apr = 1,
575 .mpr = 1,
576 .tpauser = 1,
577 .hw_swap = 1,
578 .rpadir = 1,
579 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
580 };
581
sh_eth_set_rate_sh7757(struct net_device * ndev)582 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
583 {
584 struct sh_eth_private *mdp = netdev_priv(ndev);
585
586 switch (mdp->speed) {
587 case 10: /* 10BASE */
588 sh_eth_write(ndev, 0, RTRATE);
589 break;
590 case 100:/* 100BASE */
591 sh_eth_write(ndev, 1, RTRATE);
592 break;
593 default:
594 break;
595 }
596 }
597
598 /* SH7757 */
599 static struct sh_eth_cpu_data sh7757_data = {
600 .set_duplex = sh_eth_set_duplex,
601 .set_rate = sh_eth_set_rate_sh7757,
602
603 .register_type = SH_ETH_REG_FAST_SH4,
604
605 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
606
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 EESR_ECI,
611
612 .irq_flags = IRQF_SHARED,
613 .apr = 1,
614 .mpr = 1,
615 .tpauser = 1,
616 .hw_swap = 1,
617 .no_ade = 1,
618 .rpadir = 1,
619 .rpadir_value = 2 << 16,
620 .rtrate = 1,
621 };
622
623 #define SH_GIGA_ETH_BASE 0xfee00000UL
624 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
625 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
sh_eth_chip_reset_giga(struct net_device * ndev)626 static void sh_eth_chip_reset_giga(struct net_device *ndev)
627 {
628 int i;
629 u32 mahr[2], malr[2];
630
631 /* save MAHR and MALR */
632 for (i = 0; i < 2; i++) {
633 malr[i] = ioread32((void *)GIGA_MALR(i));
634 mahr[i] = ioread32((void *)GIGA_MAHR(i));
635 }
636
637 /* reset device */
638 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
639 mdelay(1);
640
641 /* restore MAHR and MALR */
642 for (i = 0; i < 2; i++) {
643 iowrite32(malr[i], (void *)GIGA_MALR(i));
644 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
645 }
646 }
647
sh_eth_set_rate_giga(struct net_device * ndev)648 static void sh_eth_set_rate_giga(struct net_device *ndev)
649 {
650 struct sh_eth_private *mdp = netdev_priv(ndev);
651
652 switch (mdp->speed) {
653 case 10: /* 10BASE */
654 sh_eth_write(ndev, 0x00000000, GECMR);
655 break;
656 case 100:/* 100BASE */
657 sh_eth_write(ndev, 0x00000010, GECMR);
658 break;
659 case 1000: /* 1000BASE */
660 sh_eth_write(ndev, 0x00000020, GECMR);
661 break;
662 default:
663 break;
664 }
665 }
666
667 /* SH7757(GETHERC) */
668 static struct sh_eth_cpu_data sh7757_data_giga = {
669 .chip_reset = sh_eth_chip_reset_giga,
670 .set_duplex = sh_eth_set_duplex,
671 .set_rate = sh_eth_set_rate_giga,
672
673 .register_type = SH_ETH_REG_GIGABIT,
674
675 .ecsr_value = ECSR_ICD | ECSR_MPD,
676 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
677 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
678
679 .tx_check = EESR_TC1 | EESR_FTC,
680 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
681 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
682 EESR_TDE | EESR_ECI,
683 .fdr_value = 0x0000072f,
684
685 .irq_flags = IRQF_SHARED,
686 .apr = 1,
687 .mpr = 1,
688 .tpauser = 1,
689 .bculr = 1,
690 .hw_swap = 1,
691 .rpadir = 1,
692 .rpadir_value = 2 << 16,
693 .no_trimd = 1,
694 .no_ade = 1,
695 .tsu = 1,
696 };
697
sh_eth_chip_reset(struct net_device * ndev)698 static void sh_eth_chip_reset(struct net_device *ndev)
699 {
700 struct sh_eth_private *mdp = netdev_priv(ndev);
701
702 /* reset device */
703 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
704 mdelay(1);
705 }
706
sh_eth_set_rate_gether(struct net_device * ndev)707 static void sh_eth_set_rate_gether(struct net_device *ndev)
708 {
709 struct sh_eth_private *mdp = netdev_priv(ndev);
710
711 switch (mdp->speed) {
712 case 10: /* 10BASE */
713 sh_eth_write(ndev, GECMR_10, GECMR);
714 break;
715 case 100:/* 100BASE */
716 sh_eth_write(ndev, GECMR_100, GECMR);
717 break;
718 case 1000: /* 1000BASE */
719 sh_eth_write(ndev, GECMR_1000, GECMR);
720 break;
721 default:
722 break;
723 }
724 }
725
726 /* SH7734 */
727 static struct sh_eth_cpu_data sh7734_data = {
728 .chip_reset = sh_eth_chip_reset,
729 .set_duplex = sh_eth_set_duplex,
730 .set_rate = sh_eth_set_rate_gether,
731
732 .register_type = SH_ETH_REG_GIGABIT,
733
734 .ecsr_value = ECSR_ICD | ECSR_MPD,
735 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
736 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
737
738 .tx_check = EESR_TC1 | EESR_FTC,
739 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
740 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
741 EESR_TDE | EESR_ECI,
742
743 .apr = 1,
744 .mpr = 1,
745 .tpauser = 1,
746 .bculr = 1,
747 .hw_swap = 1,
748 .no_trimd = 1,
749 .no_ade = 1,
750 .tsu = 1,
751 .hw_crc = 1,
752 .select_mii = 1,
753 };
754
755 /* SH7763 */
756 static struct sh_eth_cpu_data sh7763_data = {
757 .chip_reset = sh_eth_chip_reset,
758 .set_duplex = sh_eth_set_duplex,
759 .set_rate = sh_eth_set_rate_gether,
760
761 .register_type = SH_ETH_REG_GIGABIT,
762
763 .ecsr_value = ECSR_ICD | ECSR_MPD,
764 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
765 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
766
767 .tx_check = EESR_TC1 | EESR_FTC,
768 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
769 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
770 EESR_ECI,
771
772 .apr = 1,
773 .mpr = 1,
774 .tpauser = 1,
775 .bculr = 1,
776 .hw_swap = 1,
777 .no_trimd = 1,
778 .no_ade = 1,
779 .tsu = 1,
780 .irq_flags = IRQF_SHARED,
781 };
782
sh_eth_chip_reset_r8a7740(struct net_device * ndev)783 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
784 {
785 struct sh_eth_private *mdp = netdev_priv(ndev);
786
787 /* reset device */
788 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
789 mdelay(1);
790
791 sh_eth_select_mii(ndev);
792 }
793
794 /* R8A7740 */
795 static struct sh_eth_cpu_data r8a7740_data = {
796 .chip_reset = sh_eth_chip_reset_r8a7740,
797 .set_duplex = sh_eth_set_duplex,
798 .set_rate = sh_eth_set_rate_gether,
799
800 .register_type = SH_ETH_REG_GIGABIT,
801
802 .ecsr_value = ECSR_ICD | ECSR_MPD,
803 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
804 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
805
806 .tx_check = EESR_TC1 | EESR_FTC,
807 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
808 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
809 EESR_TDE | EESR_ECI,
810 .fdr_value = 0x0000070f,
811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .rpadir = 1,
818 .rpadir_value = 2 << 16,
819 .no_trimd = 1,
820 .no_ade = 1,
821 .tsu = 1,
822 .select_mii = 1,
823 .shift_rd0 = 1,
824 };
825
826 /* R7S72100 */
827 static struct sh_eth_cpu_data r7s72100_data = {
828 .chip_reset = sh_eth_chip_reset,
829 .set_duplex = sh_eth_set_duplex,
830
831 .register_type = SH_ETH_REG_FAST_RZ,
832
833 .ecsr_value = ECSR_ICD,
834 .ecsipr_value = ECSIPR_ICDIP,
835 .eesipr_value = 0xff7f009f,
836
837 .tx_check = EESR_TC1 | EESR_FTC,
838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
840 EESR_TDE | EESR_ECI,
841 .fdr_value = 0x0000070f,
842
843 .no_psr = 1,
844 .apr = 1,
845 .mpr = 1,
846 .tpauser = 1,
847 .hw_swap = 1,
848 .rpadir = 1,
849 .rpadir_value = 2 << 16,
850 .no_trimd = 1,
851 .no_ade = 1,
852 .hw_crc = 1,
853 .tsu = 1,
854 .shift_rd0 = 1,
855 };
856
857 static struct sh_eth_cpu_data sh7619_data = {
858 .register_type = SH_ETH_REG_FAST_SH3_SH2,
859
860 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
861
862 .apr = 1,
863 .mpr = 1,
864 .tpauser = 1,
865 .hw_swap = 1,
866 };
867
868 static struct sh_eth_cpu_data sh771x_data = {
869 .register_type = SH_ETH_REG_FAST_SH3_SH2,
870
871 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
872 .tsu = 1,
873 };
874
sh_eth_set_default_cpu_data(struct sh_eth_cpu_data * cd)875 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
876 {
877 if (!cd->ecsr_value)
878 cd->ecsr_value = DEFAULT_ECSR_INIT;
879
880 if (!cd->ecsipr_value)
881 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
882
883 if (!cd->fcftr_value)
884 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
885 DEFAULT_FIFO_F_D_RFD;
886
887 if (!cd->fdr_value)
888 cd->fdr_value = DEFAULT_FDR_INIT;
889
890 if (!cd->tx_check)
891 cd->tx_check = DEFAULT_TX_CHECK;
892
893 if (!cd->eesr_err_check)
894 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
895
896 if (!cd->trscer_err_mask)
897 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
898 }
899
sh_eth_check_reset(struct net_device * ndev)900 static int sh_eth_check_reset(struct net_device *ndev)
901 {
902 int ret = 0;
903 int cnt = 100;
904
905 while (cnt > 0) {
906 if (!(sh_eth_read(ndev, EDMR) & 0x3))
907 break;
908 mdelay(1);
909 cnt--;
910 }
911 if (cnt <= 0) {
912 netdev_err(ndev, "Device reset failed\n");
913 ret = -ETIMEDOUT;
914 }
915 return ret;
916 }
917
sh_eth_reset(struct net_device * ndev)918 static int sh_eth_reset(struct net_device *ndev)
919 {
920 struct sh_eth_private *mdp = netdev_priv(ndev);
921 int ret = 0;
922
923 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
924 sh_eth_write(ndev, EDSR_ENALL, EDSR);
925 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
926 EDMR);
927
928 ret = sh_eth_check_reset(ndev);
929 if (ret)
930 return ret;
931
932 /* Table Init */
933 sh_eth_write(ndev, 0x0, TDLAR);
934 sh_eth_write(ndev, 0x0, TDFAR);
935 sh_eth_write(ndev, 0x0, TDFXR);
936 sh_eth_write(ndev, 0x0, TDFFR);
937 sh_eth_write(ndev, 0x0, RDLAR);
938 sh_eth_write(ndev, 0x0, RDFAR);
939 sh_eth_write(ndev, 0x0, RDFXR);
940 sh_eth_write(ndev, 0x0, RDFFR);
941
942 /* Reset HW CRC register */
943 if (mdp->cd->hw_crc)
944 sh_eth_write(ndev, 0x0, CSMR);
945
946 /* Select MII mode */
947 if (mdp->cd->select_mii)
948 sh_eth_select_mii(ndev);
949 } else {
950 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
951 EDMR);
952 mdelay(3);
953 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
954 EDMR);
955 }
956
957 return ret;
958 }
959
sh_eth_set_receive_align(struct sk_buff * skb)960 static void sh_eth_set_receive_align(struct sk_buff *skb)
961 {
962 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
963
964 if (reserve)
965 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
966 }
967
968
969 /* CPU <-> EDMAC endian convert */
cpu_to_edmac(struct sh_eth_private * mdp,u32 x)970 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
971 {
972 switch (mdp->edmac_endian) {
973 case EDMAC_LITTLE_ENDIAN:
974 return cpu_to_le32(x);
975 case EDMAC_BIG_ENDIAN:
976 return cpu_to_be32(x);
977 }
978 return x;
979 }
980
edmac_to_cpu(struct sh_eth_private * mdp,u32 x)981 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
982 {
983 switch (mdp->edmac_endian) {
984 case EDMAC_LITTLE_ENDIAN:
985 return le32_to_cpu(x);
986 case EDMAC_BIG_ENDIAN:
987 return be32_to_cpu(x);
988 }
989 return x;
990 }
991
992 /* Program the hardware MAC address from dev->dev_addr. */
update_mac_address(struct net_device * ndev)993 static void update_mac_address(struct net_device *ndev)
994 {
995 sh_eth_write(ndev,
996 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
997 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
998 sh_eth_write(ndev,
999 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1000 }
1001
1002 /* Get MAC address from SuperH MAC address register
1003 *
1004 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1005 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1006 * When you want use this device, you must set MAC address in bootloader.
1007 *
1008 */
read_mac_address(struct net_device * ndev,unsigned char * mac)1009 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1010 {
1011 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1012 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1013 } else {
1014 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
1015 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
1016 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
1017 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
1018 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
1019 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
1020 }
1021 }
1022
sh_eth_get_edtrr_trns(struct sh_eth_private * mdp)1023 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1024 {
1025 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1026 return EDTRR_TRNS_GETHER;
1027 else
1028 return EDTRR_TRNS_ETHER;
1029 }
1030
1031 struct bb_info {
1032 void (*set_gate)(void *addr);
1033 struct mdiobb_ctrl ctrl;
1034 void *addr;
1035 u32 mmd_msk;/* MMD */
1036 u32 mdo_msk;
1037 u32 mdi_msk;
1038 u32 mdc_msk;
1039 };
1040
1041 /* PHY bit set */
bb_set(void * addr,u32 msk)1042 static void bb_set(void *addr, u32 msk)
1043 {
1044 iowrite32(ioread32(addr) | msk, addr);
1045 }
1046
1047 /* PHY bit clear */
bb_clr(void * addr,u32 msk)1048 static void bb_clr(void *addr, u32 msk)
1049 {
1050 iowrite32((ioread32(addr) & ~msk), addr);
1051 }
1052
1053 /* PHY bit read */
bb_read(void * addr,u32 msk)1054 static int bb_read(void *addr, u32 msk)
1055 {
1056 return (ioread32(addr) & msk) != 0;
1057 }
1058
1059 /* Data I/O pin control */
sh_mmd_ctrl(struct mdiobb_ctrl * ctrl,int bit)1060 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1061 {
1062 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1063
1064 if (bitbang->set_gate)
1065 bitbang->set_gate(bitbang->addr);
1066
1067 if (bit)
1068 bb_set(bitbang->addr, bitbang->mmd_msk);
1069 else
1070 bb_clr(bitbang->addr, bitbang->mmd_msk);
1071 }
1072
1073 /* Set bit data*/
sh_set_mdio(struct mdiobb_ctrl * ctrl,int bit)1074 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1075 {
1076 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1077
1078 if (bitbang->set_gate)
1079 bitbang->set_gate(bitbang->addr);
1080
1081 if (bit)
1082 bb_set(bitbang->addr, bitbang->mdo_msk);
1083 else
1084 bb_clr(bitbang->addr, bitbang->mdo_msk);
1085 }
1086
1087 /* Get bit data*/
sh_get_mdio(struct mdiobb_ctrl * ctrl)1088 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1089 {
1090 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1091
1092 if (bitbang->set_gate)
1093 bitbang->set_gate(bitbang->addr);
1094
1095 return bb_read(bitbang->addr, bitbang->mdi_msk);
1096 }
1097
1098 /* MDC pin control */
sh_mdc_ctrl(struct mdiobb_ctrl * ctrl,int bit)1099 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1100 {
1101 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1102
1103 if (bitbang->set_gate)
1104 bitbang->set_gate(bitbang->addr);
1105
1106 if (bit)
1107 bb_set(bitbang->addr, bitbang->mdc_msk);
1108 else
1109 bb_clr(bitbang->addr, bitbang->mdc_msk);
1110 }
1111
1112 /* mdio bus control struct */
1113 static struct mdiobb_ops bb_ops = {
1114 .owner = THIS_MODULE,
1115 .set_mdc = sh_mdc_ctrl,
1116 .set_mdio_dir = sh_mmd_ctrl,
1117 .set_mdio_data = sh_set_mdio,
1118 .get_mdio_data = sh_get_mdio,
1119 };
1120
1121 /* free skb and descriptor buffer */
sh_eth_ring_free(struct net_device * ndev)1122 static void sh_eth_ring_free(struct net_device *ndev)
1123 {
1124 struct sh_eth_private *mdp = netdev_priv(ndev);
1125 int ringsize, i;
1126
1127 /* Free Rx skb ringbuffer */
1128 if (mdp->rx_skbuff) {
1129 for (i = 0; i < mdp->num_rx_ring; i++)
1130 dev_kfree_skb(mdp->rx_skbuff[i]);
1131 }
1132 kfree(mdp->rx_skbuff);
1133 mdp->rx_skbuff = NULL;
1134
1135 /* Free Tx skb ringbuffer */
1136 if (mdp->tx_skbuff) {
1137 for (i = 0; i < mdp->num_tx_ring; i++)
1138 dev_kfree_skb(mdp->tx_skbuff[i]);
1139 }
1140 kfree(mdp->tx_skbuff);
1141 mdp->tx_skbuff = NULL;
1142
1143 if (mdp->rx_ring) {
1144 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1145 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1146 mdp->rx_desc_dma);
1147 mdp->rx_ring = NULL;
1148 }
1149
1150 if (mdp->tx_ring) {
1151 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1152 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1153 mdp->tx_desc_dma);
1154 mdp->tx_ring = NULL;
1155 }
1156 }
1157
1158 /* format skb and descriptor buffer */
sh_eth_ring_format(struct net_device * ndev)1159 static void sh_eth_ring_format(struct net_device *ndev)
1160 {
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1162 int i;
1163 struct sk_buff *skb;
1164 struct sh_eth_rxdesc *rxdesc = NULL;
1165 struct sh_eth_txdesc *txdesc = NULL;
1166 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1167 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1168 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1169 dma_addr_t dma_addr;
1170 u32 buf_len;
1171
1172 mdp->cur_rx = 0;
1173 mdp->cur_tx = 0;
1174 mdp->dirty_rx = 0;
1175 mdp->dirty_tx = 0;
1176
1177 memset(mdp->rx_ring, 0, rx_ringsize);
1178
1179 /* build Rx ring buffer */
1180 for (i = 0; i < mdp->num_rx_ring; i++) {
1181 /* skb */
1182 mdp->rx_skbuff[i] = NULL;
1183 skb = netdev_alloc_skb(ndev, skbuff_size);
1184 if (skb == NULL)
1185 break;
1186 sh_eth_set_receive_align(skb);
1187
1188 /* The size of the buffer is a multiple of 32 bytes. */
1189 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1190 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1191 DMA_FROM_DEVICE);
1192 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1193 kfree_skb(skb);
1194 break;
1195 }
1196 mdp->rx_skbuff[i] = skb;
1197
1198 /* RX descriptor */
1199 rxdesc = &mdp->rx_ring[i];
1200 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1201 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1202 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1203
1204 /* Rx descriptor address set */
1205 if (i == 0) {
1206 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1207 if (sh_eth_is_gether(mdp) ||
1208 sh_eth_is_rz_fast_ether(mdp))
1209 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1210 }
1211 }
1212
1213 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1214
1215 /* Mark the last entry as wrapping the ring. */
1216 if (rxdesc)
1217 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1218
1219 memset(mdp->tx_ring, 0, tx_ringsize);
1220
1221 /* build Tx ring buffer */
1222 for (i = 0; i < mdp->num_tx_ring; i++) {
1223 mdp->tx_skbuff[i] = NULL;
1224 txdesc = &mdp->tx_ring[i];
1225 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1226 txdesc->len = cpu_to_edmac(mdp, 0);
1227 if (i == 0) {
1228 /* Tx descriptor address set */
1229 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1230 if (sh_eth_is_gether(mdp) ||
1231 sh_eth_is_rz_fast_ether(mdp))
1232 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1233 }
1234 }
1235
1236 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1237 }
1238
1239 /* Get skb and descriptor buffer */
sh_eth_ring_init(struct net_device * ndev)1240 static int sh_eth_ring_init(struct net_device *ndev)
1241 {
1242 struct sh_eth_private *mdp = netdev_priv(ndev);
1243 int rx_ringsize, tx_ringsize;
1244
1245 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1246 * card needs room to do 8 byte alignment, +2 so we can reserve
1247 * the first 2 bytes, and +16 gets room for the status word from the
1248 * card.
1249 */
1250 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1251 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1252 if (mdp->cd->rpadir)
1253 mdp->rx_buf_sz += NET_IP_ALIGN;
1254
1255 /* Allocate RX and TX skb rings */
1256 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1257 GFP_KERNEL);
1258 if (!mdp->rx_skbuff)
1259 return -ENOMEM;
1260
1261 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1262 GFP_KERNEL);
1263 if (!mdp->tx_skbuff)
1264 goto ring_free;
1265
1266 /* Allocate all Rx descriptors. */
1267 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1268 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1269 GFP_KERNEL);
1270 if (!mdp->rx_ring)
1271 goto ring_free;
1272
1273 mdp->dirty_rx = 0;
1274
1275 /* Allocate all Tx descriptors. */
1276 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1277 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1278 GFP_KERNEL);
1279 if (!mdp->tx_ring)
1280 goto ring_free;
1281 return 0;
1282
1283 ring_free:
1284 /* Free Rx and Tx skb ring buffer and DMA buffer */
1285 sh_eth_ring_free(ndev);
1286
1287 return -ENOMEM;
1288 }
1289
sh_eth_dev_init(struct net_device * ndev,bool start)1290 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1291 {
1292 int ret = 0;
1293 struct sh_eth_private *mdp = netdev_priv(ndev);
1294 u32 val;
1295
1296 /* Soft Reset */
1297 ret = sh_eth_reset(ndev);
1298 if (ret)
1299 return ret;
1300
1301 if (mdp->cd->rmiimode)
1302 sh_eth_write(ndev, 0x1, RMIIMODE);
1303
1304 /* Descriptor format */
1305 sh_eth_ring_format(ndev);
1306 if (mdp->cd->rpadir)
1307 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1308
1309 /* all sh_eth int mask */
1310 sh_eth_write(ndev, 0, EESIPR);
1311
1312 #if defined(__LITTLE_ENDIAN)
1313 if (mdp->cd->hw_swap)
1314 sh_eth_write(ndev, EDMR_EL, EDMR);
1315 else
1316 #endif
1317 sh_eth_write(ndev, 0, EDMR);
1318
1319 /* FIFO size set */
1320 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1321 sh_eth_write(ndev, 0, TFTR);
1322
1323 /* Frame recv control (enable multiple-packets per rx irq) */
1324 sh_eth_write(ndev, RMCR_RNC, RMCR);
1325
1326 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1327
1328 if (mdp->cd->bculr)
1329 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1330
1331 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1332
1333 if (!mdp->cd->no_trimd)
1334 sh_eth_write(ndev, 0, TRIMD);
1335
1336 /* Recv frame limit set register */
1337 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1338 RFLR);
1339
1340 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1341 if (start) {
1342 mdp->irq_enabled = true;
1343 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1344 }
1345
1346 /* PAUSE Prohibition */
1347 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1348 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1349
1350 sh_eth_write(ndev, val, ECMR);
1351
1352 if (mdp->cd->set_rate)
1353 mdp->cd->set_rate(ndev);
1354
1355 /* E-MAC Status Register clear */
1356 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1357
1358 /* E-MAC Interrupt Enable register */
1359 if (start)
1360 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1361
1362 /* Set MAC address */
1363 update_mac_address(ndev);
1364
1365 /* mask reset */
1366 if (mdp->cd->apr)
1367 sh_eth_write(ndev, APR_AP, APR);
1368 if (mdp->cd->mpr)
1369 sh_eth_write(ndev, MPR_MP, MPR);
1370 if (mdp->cd->tpauser)
1371 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1372
1373 if (start) {
1374 /* Setting the Rx mode will start the Rx process. */
1375 sh_eth_write(ndev, EDRRR_R, EDRRR);
1376
1377 netif_start_queue(ndev);
1378 }
1379
1380 return ret;
1381 }
1382
sh_eth_dev_exit(struct net_device * ndev)1383 static void sh_eth_dev_exit(struct net_device *ndev)
1384 {
1385 struct sh_eth_private *mdp = netdev_priv(ndev);
1386 int i;
1387
1388 /* Deactivate all TX descriptors, so DMA should stop at next
1389 * packet boundary if it's currently running
1390 */
1391 for (i = 0; i < mdp->num_tx_ring; i++)
1392 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1393
1394 /* Disable TX FIFO egress to MAC */
1395 sh_eth_rcv_snd_disable(ndev);
1396
1397 /* Stop RX DMA at next packet boundary */
1398 sh_eth_write(ndev, 0, EDRRR);
1399
1400 /* Aside from TX DMA, we can't tell when the hardware is
1401 * really stopped, so we need to reset to make sure.
1402 * Before doing that, wait for long enough to *probably*
1403 * finish transmitting the last packet and poll stats.
1404 */
1405 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1406 sh_eth_get_stats(ndev);
1407 sh_eth_reset(ndev);
1408
1409 /* Set MAC address again */
1410 update_mac_address(ndev);
1411 }
1412
1413 /* free Tx skb function */
sh_eth_txfree(struct net_device * ndev)1414 static int sh_eth_txfree(struct net_device *ndev)
1415 {
1416 struct sh_eth_private *mdp = netdev_priv(ndev);
1417 struct sh_eth_txdesc *txdesc;
1418 int free_num = 0;
1419 int entry = 0;
1420
1421 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1422 entry = mdp->dirty_tx % mdp->num_tx_ring;
1423 txdesc = &mdp->tx_ring[entry];
1424 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1425 break;
1426 /* TACT bit must be checked before all the following reads */
1427 dma_rmb();
1428 netif_info(mdp, tx_done, ndev,
1429 "tx entry %d status 0x%08x\n",
1430 entry, edmac_to_cpu(mdp, txdesc->status));
1431 /* Free the original skb. */
1432 if (mdp->tx_skbuff[entry]) {
1433 dma_unmap_single(&ndev->dev,
1434 edmac_to_cpu(mdp, txdesc->addr),
1435 edmac_to_cpu(mdp, txdesc->len) >> 16,
1436 DMA_TO_DEVICE);
1437 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1438 mdp->tx_skbuff[entry] = NULL;
1439 free_num++;
1440 }
1441 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1442 if (entry >= mdp->num_tx_ring - 1)
1443 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1444
1445 ndev->stats.tx_packets++;
1446 ndev->stats.tx_bytes += edmac_to_cpu(mdp, txdesc->len) >> 16;
1447 }
1448 return free_num;
1449 }
1450
1451 /* Packet receive function */
sh_eth_rx(struct net_device * ndev,u32 intr_status,int * quota)1452 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1453 {
1454 struct sh_eth_private *mdp = netdev_priv(ndev);
1455 struct sh_eth_rxdesc *rxdesc;
1456
1457 int entry = mdp->cur_rx % mdp->num_rx_ring;
1458 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1459 int limit;
1460 struct sk_buff *skb;
1461 u16 pkt_len = 0;
1462 u32 desc_status;
1463 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1464 dma_addr_t dma_addr;
1465 u32 buf_len;
1466
1467 boguscnt = min(boguscnt, *quota);
1468 limit = boguscnt;
1469 rxdesc = &mdp->rx_ring[entry];
1470 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1471 /* RACT bit must be checked before all the following reads */
1472 dma_rmb();
1473 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1474 pkt_len = edmac_to_cpu(mdp, rxdesc->len) & RD_RFL;
1475
1476 if (--boguscnt < 0)
1477 break;
1478
1479 netif_info(mdp, rx_status, ndev,
1480 "rx entry %d status 0x%08x len %d\n",
1481 entry, desc_status, pkt_len);
1482
1483 if (!(desc_status & RDFEND))
1484 ndev->stats.rx_length_errors++;
1485
1486 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1487 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1488 * bit 0. However, in case of the R8A7740 and R7S72100
1489 * the RFS bits are from bit 25 to bit 16. So, the
1490 * driver needs right shifting by 16.
1491 */
1492 if (mdp->cd->shift_rd0)
1493 desc_status >>= 16;
1494
1495 skb = mdp->rx_skbuff[entry];
1496 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1497 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1498 ndev->stats.rx_errors++;
1499 if (desc_status & RD_RFS1)
1500 ndev->stats.rx_crc_errors++;
1501 if (desc_status & RD_RFS2)
1502 ndev->stats.rx_frame_errors++;
1503 if (desc_status & RD_RFS3)
1504 ndev->stats.rx_length_errors++;
1505 if (desc_status & RD_RFS4)
1506 ndev->stats.rx_length_errors++;
1507 if (desc_status & RD_RFS6)
1508 ndev->stats.rx_missed_errors++;
1509 if (desc_status & RD_RFS10)
1510 ndev->stats.rx_over_errors++;
1511 } else if (skb) {
1512 dma_addr = edmac_to_cpu(mdp, rxdesc->addr);
1513 if (!mdp->cd->hw_swap)
1514 sh_eth_soft_swap(
1515 phys_to_virt(ALIGN(dma_addr, 4)),
1516 pkt_len + 2);
1517 mdp->rx_skbuff[entry] = NULL;
1518 if (mdp->cd->rpadir)
1519 skb_reserve(skb, NET_IP_ALIGN);
1520 dma_unmap_single(&ndev->dev, dma_addr,
1521 ALIGN(mdp->rx_buf_sz, 32),
1522 DMA_FROM_DEVICE);
1523 skb_put(skb, pkt_len);
1524 skb->protocol = eth_type_trans(skb, ndev);
1525 netif_receive_skb(skb);
1526 ndev->stats.rx_packets++;
1527 ndev->stats.rx_bytes += pkt_len;
1528 if (desc_status & RD_RFS8)
1529 ndev->stats.multicast++;
1530 }
1531 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1532 rxdesc = &mdp->rx_ring[entry];
1533 }
1534
1535 /* Refill the Rx ring buffers. */
1536 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1537 entry = mdp->dirty_rx % mdp->num_rx_ring;
1538 rxdesc = &mdp->rx_ring[entry];
1539 /* The size of the buffer is 32 byte boundary. */
1540 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1541 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1542
1543 if (mdp->rx_skbuff[entry] == NULL) {
1544 skb = netdev_alloc_skb(ndev, skbuff_size);
1545 if (skb == NULL)
1546 break; /* Better luck next round. */
1547 sh_eth_set_receive_align(skb);
1548 dma_addr = dma_map_single(&ndev->dev, skb->data,
1549 buf_len, DMA_FROM_DEVICE);
1550 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1551 kfree_skb(skb);
1552 break;
1553 }
1554 mdp->rx_skbuff[entry] = skb;
1555
1556 skb_checksum_none_assert(skb);
1557 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1558 }
1559 dma_wmb(); /* RACT bit must be set after all the above writes */
1560 if (entry >= mdp->num_rx_ring - 1)
1561 rxdesc->status |=
1562 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1563 else
1564 rxdesc->status |=
1565 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1566 }
1567
1568 /* Restart Rx engine if stopped. */
1569 /* If we don't need to check status, don't. -KDU */
1570 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1571 /* fix the values for the next receiving if RDE is set */
1572 if (intr_status & EESR_RDE &&
1573 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1574 u32 count = (sh_eth_read(ndev, RDFAR) -
1575 sh_eth_read(ndev, RDLAR)) >> 4;
1576
1577 mdp->cur_rx = count;
1578 mdp->dirty_rx = count;
1579 }
1580 sh_eth_write(ndev, EDRRR_R, EDRRR);
1581 }
1582
1583 *quota -= limit - boguscnt - 1;
1584
1585 return *quota <= 0;
1586 }
1587
sh_eth_rcv_snd_disable(struct net_device * ndev)1588 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1589 {
1590 /* disable tx and rx */
1591 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1592 ~(ECMR_RE | ECMR_TE), ECMR);
1593 }
1594
sh_eth_rcv_snd_enable(struct net_device * ndev)1595 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1596 {
1597 /* enable tx and rx */
1598 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1599 (ECMR_RE | ECMR_TE), ECMR);
1600 }
1601
1602 /* error control function */
sh_eth_error(struct net_device * ndev,u32 intr_status)1603 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1604 {
1605 struct sh_eth_private *mdp = netdev_priv(ndev);
1606 u32 felic_stat;
1607 u32 link_stat;
1608 u32 mask;
1609
1610 if (intr_status & EESR_ECI) {
1611 felic_stat = sh_eth_read(ndev, ECSR);
1612 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1613 if (felic_stat & ECSR_ICD)
1614 ndev->stats.tx_carrier_errors++;
1615 if (felic_stat & ECSR_LCHNG) {
1616 /* Link Changed */
1617 if (mdp->cd->no_psr || mdp->no_ether_link) {
1618 goto ignore_link;
1619 } else {
1620 link_stat = (sh_eth_read(ndev, PSR));
1621 if (mdp->ether_link_active_low)
1622 link_stat = ~link_stat;
1623 }
1624 if (!(link_stat & PHY_ST_LINK)) {
1625 sh_eth_rcv_snd_disable(ndev);
1626 } else {
1627 /* Link Up */
1628 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1629 ~DMAC_M_ECI, EESIPR);
1630 /* clear int */
1631 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1632 ECSR);
1633 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1634 DMAC_M_ECI, EESIPR);
1635 /* enable tx and rx */
1636 sh_eth_rcv_snd_enable(ndev);
1637 }
1638 }
1639 }
1640
1641 ignore_link:
1642 if (intr_status & EESR_TWB) {
1643 /* Unused write back interrupt */
1644 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1645 ndev->stats.tx_aborted_errors++;
1646 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1647 }
1648 }
1649
1650 if (intr_status & EESR_RABT) {
1651 /* Receive Abort int */
1652 if (intr_status & EESR_RFRMER) {
1653 /* Receive Frame Overflow int */
1654 ndev->stats.rx_frame_errors++;
1655 }
1656 }
1657
1658 if (intr_status & EESR_TDE) {
1659 /* Transmit Descriptor Empty int */
1660 ndev->stats.tx_fifo_errors++;
1661 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1662 }
1663
1664 if (intr_status & EESR_TFE) {
1665 /* FIFO under flow */
1666 ndev->stats.tx_fifo_errors++;
1667 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1668 }
1669
1670 if (intr_status & EESR_RDE) {
1671 /* Receive Descriptor Empty int */
1672 ndev->stats.rx_over_errors++;
1673 }
1674
1675 if (intr_status & EESR_RFE) {
1676 /* Receive FIFO Overflow int */
1677 ndev->stats.rx_fifo_errors++;
1678 }
1679
1680 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1681 /* Address Error */
1682 ndev->stats.tx_fifo_errors++;
1683 netif_err(mdp, tx_err, ndev, "Address Error\n");
1684 }
1685
1686 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1687 if (mdp->cd->no_ade)
1688 mask &= ~EESR_ADE;
1689 if (intr_status & mask) {
1690 /* Tx error */
1691 u32 edtrr = sh_eth_read(ndev, EDTRR);
1692
1693 /* dmesg */
1694 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1695 intr_status, mdp->cur_tx, mdp->dirty_tx,
1696 (u32)ndev->state, edtrr);
1697 /* dirty buffer free */
1698 sh_eth_txfree(ndev);
1699
1700 /* SH7712 BUG */
1701 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1702 /* tx dma start */
1703 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1704 }
1705 /* wakeup */
1706 netif_wake_queue(ndev);
1707 }
1708 }
1709
sh_eth_interrupt(int irq,void * netdev)1710 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1711 {
1712 struct net_device *ndev = netdev;
1713 struct sh_eth_private *mdp = netdev_priv(ndev);
1714 struct sh_eth_cpu_data *cd = mdp->cd;
1715 irqreturn_t ret = IRQ_NONE;
1716 u32 intr_status, intr_enable;
1717
1718 spin_lock(&mdp->lock);
1719
1720 /* Get interrupt status */
1721 intr_status = sh_eth_read(ndev, EESR);
1722 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1723 * enabled since it's the one that comes thru regardless of the mask,
1724 * and we need to fully handle it in sh_eth_error() in order to quench
1725 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1726 */
1727 intr_enable = sh_eth_read(ndev, EESIPR);
1728 intr_status &= intr_enable | DMAC_M_ECI;
1729 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1730 ret = IRQ_HANDLED;
1731 else
1732 goto out;
1733
1734 if (!likely(mdp->irq_enabled)) {
1735 sh_eth_write(ndev, 0, EESIPR);
1736 goto out;
1737 }
1738
1739 if (intr_status & EESR_RX_CHECK) {
1740 if (napi_schedule_prep(&mdp->napi)) {
1741 /* Mask Rx interrupts */
1742 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1743 EESIPR);
1744 __napi_schedule(&mdp->napi);
1745 } else {
1746 netdev_warn(ndev,
1747 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1748 intr_status, intr_enable);
1749 }
1750 }
1751
1752 /* Tx Check */
1753 if (intr_status & cd->tx_check) {
1754 /* Clear Tx interrupts */
1755 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1756
1757 sh_eth_txfree(ndev);
1758 netif_wake_queue(ndev);
1759 }
1760
1761 if (intr_status & cd->eesr_err_check) {
1762 /* Clear error interrupts */
1763 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1764
1765 sh_eth_error(ndev, intr_status);
1766 }
1767
1768 out:
1769 spin_unlock(&mdp->lock);
1770
1771 return ret;
1772 }
1773
sh_eth_poll(struct napi_struct * napi,int budget)1774 static int sh_eth_poll(struct napi_struct *napi, int budget)
1775 {
1776 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1777 napi);
1778 struct net_device *ndev = napi->dev;
1779 int quota = budget;
1780 u32 intr_status;
1781
1782 for (;;) {
1783 intr_status = sh_eth_read(ndev, EESR);
1784 if (!(intr_status & EESR_RX_CHECK))
1785 break;
1786 /* Clear Rx interrupts */
1787 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1788
1789 if (sh_eth_rx(ndev, intr_status, "a))
1790 goto out;
1791 }
1792
1793 napi_complete(napi);
1794
1795 /* Reenable Rx interrupts */
1796 if (mdp->irq_enabled)
1797 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1798 out:
1799 return budget - quota;
1800 }
1801
1802 /* PHY state control function */
sh_eth_adjust_link(struct net_device * ndev)1803 static void sh_eth_adjust_link(struct net_device *ndev)
1804 {
1805 struct sh_eth_private *mdp = netdev_priv(ndev);
1806 struct phy_device *phydev = mdp->phydev;
1807 int new_state = 0;
1808
1809 if (phydev->link) {
1810 if (phydev->duplex != mdp->duplex) {
1811 new_state = 1;
1812 mdp->duplex = phydev->duplex;
1813 if (mdp->cd->set_duplex)
1814 mdp->cd->set_duplex(ndev);
1815 }
1816
1817 if (phydev->speed != mdp->speed) {
1818 new_state = 1;
1819 mdp->speed = phydev->speed;
1820 if (mdp->cd->set_rate)
1821 mdp->cd->set_rate(ndev);
1822 }
1823 if (!mdp->link) {
1824 sh_eth_write(ndev,
1825 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1826 ECMR);
1827 new_state = 1;
1828 mdp->link = phydev->link;
1829 if (mdp->cd->no_psr || mdp->no_ether_link)
1830 sh_eth_rcv_snd_enable(ndev);
1831 }
1832 } else if (mdp->link) {
1833 new_state = 1;
1834 mdp->link = 0;
1835 mdp->speed = 0;
1836 mdp->duplex = -1;
1837 if (mdp->cd->no_psr || mdp->no_ether_link)
1838 sh_eth_rcv_snd_disable(ndev);
1839 }
1840
1841 if (new_state && netif_msg_link(mdp))
1842 phy_print_status(phydev);
1843 }
1844
1845 /* PHY init function */
sh_eth_phy_init(struct net_device * ndev)1846 static int sh_eth_phy_init(struct net_device *ndev)
1847 {
1848 struct device_node *np = ndev->dev.parent->of_node;
1849 struct sh_eth_private *mdp = netdev_priv(ndev);
1850 struct phy_device *phydev = NULL;
1851
1852 mdp->link = 0;
1853 mdp->speed = 0;
1854 mdp->duplex = -1;
1855
1856 /* Try connect to PHY */
1857 if (np) {
1858 struct device_node *pn;
1859
1860 pn = of_parse_phandle(np, "phy-handle", 0);
1861 phydev = of_phy_connect(ndev, pn,
1862 sh_eth_adjust_link, 0,
1863 mdp->phy_interface);
1864
1865 if (!phydev)
1866 phydev = ERR_PTR(-ENOENT);
1867 } else {
1868 char phy_id[MII_BUS_ID_SIZE + 3];
1869
1870 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1871 mdp->mii_bus->id, mdp->phy_id);
1872
1873 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1874 mdp->phy_interface);
1875 }
1876
1877 if (IS_ERR(phydev)) {
1878 netdev_err(ndev, "failed to connect PHY\n");
1879 return PTR_ERR(phydev);
1880 }
1881
1882 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1883 phydev->addr, phydev->irq, phydev->drv->name);
1884
1885 mdp->phydev = phydev;
1886
1887 return 0;
1888 }
1889
1890 /* PHY control start function */
sh_eth_phy_start(struct net_device * ndev)1891 static int sh_eth_phy_start(struct net_device *ndev)
1892 {
1893 struct sh_eth_private *mdp = netdev_priv(ndev);
1894 int ret;
1895
1896 ret = sh_eth_phy_init(ndev);
1897 if (ret)
1898 return ret;
1899
1900 phy_start(mdp->phydev);
1901
1902 return 0;
1903 }
1904
sh_eth_get_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)1905 static int sh_eth_get_settings(struct net_device *ndev,
1906 struct ethtool_cmd *ecmd)
1907 {
1908 struct sh_eth_private *mdp = netdev_priv(ndev);
1909 unsigned long flags;
1910 int ret;
1911
1912 if (!mdp->phydev)
1913 return -ENODEV;
1914
1915 spin_lock_irqsave(&mdp->lock, flags);
1916 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1917 spin_unlock_irqrestore(&mdp->lock, flags);
1918
1919 return ret;
1920 }
1921
sh_eth_set_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)1922 static int sh_eth_set_settings(struct net_device *ndev,
1923 struct ethtool_cmd *ecmd)
1924 {
1925 struct sh_eth_private *mdp = netdev_priv(ndev);
1926 unsigned long flags;
1927 int ret;
1928
1929 if (!mdp->phydev)
1930 return -ENODEV;
1931
1932 spin_lock_irqsave(&mdp->lock, flags);
1933
1934 /* disable tx and rx */
1935 sh_eth_rcv_snd_disable(ndev);
1936
1937 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1938 if (ret)
1939 goto error_exit;
1940
1941 if (ecmd->duplex == DUPLEX_FULL)
1942 mdp->duplex = 1;
1943 else
1944 mdp->duplex = 0;
1945
1946 if (mdp->cd->set_duplex)
1947 mdp->cd->set_duplex(ndev);
1948
1949 error_exit:
1950 mdelay(1);
1951
1952 /* enable tx and rx */
1953 sh_eth_rcv_snd_enable(ndev);
1954
1955 spin_unlock_irqrestore(&mdp->lock, flags);
1956
1957 return ret;
1958 }
1959
1960 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1961 * version must be bumped as well. Just adding registers up to that
1962 * limit is fine, as long as the existing register indices don't
1963 * change.
1964 */
1965 #define SH_ETH_REG_DUMP_VERSION 1
1966 #define SH_ETH_REG_DUMP_MAX_REGS 256
1967
__sh_eth_get_regs(struct net_device * ndev,u32 * buf)1968 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1969 {
1970 struct sh_eth_private *mdp = netdev_priv(ndev);
1971 struct sh_eth_cpu_data *cd = mdp->cd;
1972 u32 *valid_map;
1973 size_t len;
1974
1975 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1976
1977 /* Dump starts with a bitmap that tells ethtool which
1978 * registers are defined for this chip.
1979 */
1980 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1981 if (buf) {
1982 valid_map = buf;
1983 buf += len;
1984 } else {
1985 valid_map = NULL;
1986 }
1987
1988 /* Add a register to the dump, if it has a defined offset.
1989 * This automatically skips most undefined registers, but for
1990 * some it is also necessary to check a capability flag in
1991 * struct sh_eth_cpu_data.
1992 */
1993 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1994 #define add_reg_from(reg, read_expr) do { \
1995 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1996 if (buf) { \
1997 mark_reg_valid(reg); \
1998 *buf++ = read_expr; \
1999 } \
2000 ++len; \
2001 } \
2002 } while (0)
2003 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2004 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2005
2006 add_reg(EDSR);
2007 add_reg(EDMR);
2008 add_reg(EDTRR);
2009 add_reg(EDRRR);
2010 add_reg(EESR);
2011 add_reg(EESIPR);
2012 add_reg(TDLAR);
2013 add_reg(TDFAR);
2014 add_reg(TDFXR);
2015 add_reg(TDFFR);
2016 add_reg(RDLAR);
2017 add_reg(RDFAR);
2018 add_reg(RDFXR);
2019 add_reg(RDFFR);
2020 add_reg(TRSCER);
2021 add_reg(RMFCR);
2022 add_reg(TFTR);
2023 add_reg(FDR);
2024 add_reg(RMCR);
2025 add_reg(TFUCR);
2026 add_reg(RFOCR);
2027 if (cd->rmiimode)
2028 add_reg(RMIIMODE);
2029 add_reg(FCFTR);
2030 if (cd->rpadir)
2031 add_reg(RPADIR);
2032 if (!cd->no_trimd)
2033 add_reg(TRIMD);
2034 add_reg(ECMR);
2035 add_reg(ECSR);
2036 add_reg(ECSIPR);
2037 add_reg(PIR);
2038 if (!cd->no_psr)
2039 add_reg(PSR);
2040 add_reg(RDMLR);
2041 add_reg(RFLR);
2042 add_reg(IPGR);
2043 if (cd->apr)
2044 add_reg(APR);
2045 if (cd->mpr)
2046 add_reg(MPR);
2047 add_reg(RFCR);
2048 add_reg(RFCF);
2049 if (cd->tpauser)
2050 add_reg(TPAUSER);
2051 add_reg(TPAUSECR);
2052 add_reg(GECMR);
2053 if (cd->bculr)
2054 add_reg(BCULR);
2055 add_reg(MAHR);
2056 add_reg(MALR);
2057 add_reg(TROCR);
2058 add_reg(CDCR);
2059 add_reg(LCCR);
2060 add_reg(CNDCR);
2061 add_reg(CEFCR);
2062 add_reg(FRECR);
2063 add_reg(TSFRCR);
2064 add_reg(TLFRCR);
2065 add_reg(CERCR);
2066 add_reg(CEECR);
2067 add_reg(MAFCR);
2068 if (cd->rtrate)
2069 add_reg(RTRATE);
2070 if (cd->hw_crc)
2071 add_reg(CSMR);
2072 if (cd->select_mii)
2073 add_reg(RMII_MII);
2074 add_reg(ARSTR);
2075 if (cd->tsu) {
2076 add_tsu_reg(TSU_CTRST);
2077 add_tsu_reg(TSU_FWEN0);
2078 add_tsu_reg(TSU_FWEN1);
2079 add_tsu_reg(TSU_FCM);
2080 add_tsu_reg(TSU_BSYSL0);
2081 add_tsu_reg(TSU_BSYSL1);
2082 add_tsu_reg(TSU_PRISL0);
2083 add_tsu_reg(TSU_PRISL1);
2084 add_tsu_reg(TSU_FWSL0);
2085 add_tsu_reg(TSU_FWSL1);
2086 add_tsu_reg(TSU_FWSLC);
2087 add_tsu_reg(TSU_QTAG0);
2088 add_tsu_reg(TSU_QTAG1);
2089 add_tsu_reg(TSU_QTAGM0);
2090 add_tsu_reg(TSU_QTAGM1);
2091 add_tsu_reg(TSU_FWSR);
2092 add_tsu_reg(TSU_FWINMK);
2093 add_tsu_reg(TSU_ADQT0);
2094 add_tsu_reg(TSU_ADQT1);
2095 add_tsu_reg(TSU_VTAG0);
2096 add_tsu_reg(TSU_VTAG1);
2097 add_tsu_reg(TSU_ADSBSY);
2098 add_tsu_reg(TSU_TEN);
2099 add_tsu_reg(TSU_POST1);
2100 add_tsu_reg(TSU_POST2);
2101 add_tsu_reg(TSU_POST3);
2102 add_tsu_reg(TSU_POST4);
2103 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2104 /* This is the start of a table, not just a single
2105 * register.
2106 */
2107 if (buf) {
2108 unsigned int i;
2109
2110 mark_reg_valid(TSU_ADRH0);
2111 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2112 *buf++ = ioread32(
2113 mdp->tsu_addr +
2114 mdp->reg_offset[TSU_ADRH0] +
2115 i * 4);
2116 }
2117 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2118 }
2119 }
2120
2121 #undef mark_reg_valid
2122 #undef add_reg_from
2123 #undef add_reg
2124 #undef add_tsu_reg
2125
2126 return len * 4;
2127 }
2128
sh_eth_get_regs_len(struct net_device * ndev)2129 static int sh_eth_get_regs_len(struct net_device *ndev)
2130 {
2131 return __sh_eth_get_regs(ndev, NULL);
2132 }
2133
sh_eth_get_regs(struct net_device * ndev,struct ethtool_regs * regs,void * buf)2134 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2135 void *buf)
2136 {
2137 struct sh_eth_private *mdp = netdev_priv(ndev);
2138
2139 regs->version = SH_ETH_REG_DUMP_VERSION;
2140
2141 pm_runtime_get_sync(&mdp->pdev->dev);
2142 __sh_eth_get_regs(ndev, buf);
2143 pm_runtime_put_sync(&mdp->pdev->dev);
2144 }
2145
sh_eth_nway_reset(struct net_device * ndev)2146 static int sh_eth_nway_reset(struct net_device *ndev)
2147 {
2148 struct sh_eth_private *mdp = netdev_priv(ndev);
2149 unsigned long flags;
2150 int ret;
2151
2152 if (!mdp->phydev)
2153 return -ENODEV;
2154
2155 spin_lock_irqsave(&mdp->lock, flags);
2156 ret = phy_start_aneg(mdp->phydev);
2157 spin_unlock_irqrestore(&mdp->lock, flags);
2158
2159 return ret;
2160 }
2161
sh_eth_get_msglevel(struct net_device * ndev)2162 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2163 {
2164 struct sh_eth_private *mdp = netdev_priv(ndev);
2165 return mdp->msg_enable;
2166 }
2167
sh_eth_set_msglevel(struct net_device * ndev,u32 value)2168 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2169 {
2170 struct sh_eth_private *mdp = netdev_priv(ndev);
2171 mdp->msg_enable = value;
2172 }
2173
2174 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2175 "rx_current", "tx_current",
2176 "rx_dirty", "tx_dirty",
2177 };
2178 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2179
sh_eth_get_sset_count(struct net_device * netdev,int sset)2180 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2181 {
2182 switch (sset) {
2183 case ETH_SS_STATS:
2184 return SH_ETH_STATS_LEN;
2185 default:
2186 return -EOPNOTSUPP;
2187 }
2188 }
2189
sh_eth_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * stats,u64 * data)2190 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2191 struct ethtool_stats *stats, u64 *data)
2192 {
2193 struct sh_eth_private *mdp = netdev_priv(ndev);
2194 int i = 0;
2195
2196 /* device-specific stats */
2197 data[i++] = mdp->cur_rx;
2198 data[i++] = mdp->cur_tx;
2199 data[i++] = mdp->dirty_rx;
2200 data[i++] = mdp->dirty_tx;
2201 }
2202
sh_eth_get_strings(struct net_device * ndev,u32 stringset,u8 * data)2203 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2204 {
2205 switch (stringset) {
2206 case ETH_SS_STATS:
2207 memcpy(data, *sh_eth_gstrings_stats,
2208 sizeof(sh_eth_gstrings_stats));
2209 break;
2210 }
2211 }
2212
sh_eth_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)2213 static void sh_eth_get_ringparam(struct net_device *ndev,
2214 struct ethtool_ringparam *ring)
2215 {
2216 struct sh_eth_private *mdp = netdev_priv(ndev);
2217
2218 ring->rx_max_pending = RX_RING_MAX;
2219 ring->tx_max_pending = TX_RING_MAX;
2220 ring->rx_pending = mdp->num_rx_ring;
2221 ring->tx_pending = mdp->num_tx_ring;
2222 }
2223
sh_eth_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)2224 static int sh_eth_set_ringparam(struct net_device *ndev,
2225 struct ethtool_ringparam *ring)
2226 {
2227 struct sh_eth_private *mdp = netdev_priv(ndev);
2228 int ret;
2229
2230 if (ring->tx_pending > TX_RING_MAX ||
2231 ring->rx_pending > RX_RING_MAX ||
2232 ring->tx_pending < TX_RING_MIN ||
2233 ring->rx_pending < RX_RING_MIN)
2234 return -EINVAL;
2235 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2236 return -EINVAL;
2237
2238 if (netif_running(ndev)) {
2239 netif_device_detach(ndev);
2240 netif_tx_disable(ndev);
2241
2242 /* Serialise with the interrupt handler and NAPI, then
2243 * disable interrupts. We have to clear the
2244 * irq_enabled flag first to ensure that interrupts
2245 * won't be re-enabled.
2246 */
2247 mdp->irq_enabled = false;
2248 synchronize_irq(ndev->irq);
2249 napi_synchronize(&mdp->napi);
2250 sh_eth_write(ndev, 0x0000, EESIPR);
2251
2252 sh_eth_dev_exit(ndev);
2253
2254 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2255 sh_eth_ring_free(ndev);
2256 }
2257
2258 /* Set new parameters */
2259 mdp->num_rx_ring = ring->rx_pending;
2260 mdp->num_tx_ring = ring->tx_pending;
2261
2262 if (netif_running(ndev)) {
2263 ret = sh_eth_ring_init(ndev);
2264 if (ret < 0) {
2265 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2266 __func__);
2267 return ret;
2268 }
2269 ret = sh_eth_dev_init(ndev, false);
2270 if (ret < 0) {
2271 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2272 __func__);
2273 return ret;
2274 }
2275
2276 mdp->irq_enabled = true;
2277 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2278 /* Setting the Rx mode will start the Rx process. */
2279 sh_eth_write(ndev, EDRRR_R, EDRRR);
2280 netif_device_attach(ndev);
2281 }
2282
2283 return 0;
2284 }
2285
2286 static const struct ethtool_ops sh_eth_ethtool_ops = {
2287 .get_settings = sh_eth_get_settings,
2288 .set_settings = sh_eth_set_settings,
2289 .get_regs_len = sh_eth_get_regs_len,
2290 .get_regs = sh_eth_get_regs,
2291 .nway_reset = sh_eth_nway_reset,
2292 .get_msglevel = sh_eth_get_msglevel,
2293 .set_msglevel = sh_eth_set_msglevel,
2294 .get_link = ethtool_op_get_link,
2295 .get_strings = sh_eth_get_strings,
2296 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2297 .get_sset_count = sh_eth_get_sset_count,
2298 .get_ringparam = sh_eth_get_ringparam,
2299 .set_ringparam = sh_eth_set_ringparam,
2300 };
2301
2302 /* network device open function */
sh_eth_open(struct net_device * ndev)2303 static int sh_eth_open(struct net_device *ndev)
2304 {
2305 int ret = 0;
2306 struct sh_eth_private *mdp = netdev_priv(ndev);
2307
2308 pm_runtime_get_sync(&mdp->pdev->dev);
2309
2310 napi_enable(&mdp->napi);
2311
2312 ret = request_irq(ndev->irq, sh_eth_interrupt,
2313 mdp->cd->irq_flags, ndev->name, ndev);
2314 if (ret) {
2315 netdev_err(ndev, "Can not assign IRQ number\n");
2316 goto out_napi_off;
2317 }
2318
2319 /* Descriptor set */
2320 ret = sh_eth_ring_init(ndev);
2321 if (ret)
2322 goto out_free_irq;
2323
2324 /* device init */
2325 ret = sh_eth_dev_init(ndev, true);
2326 if (ret)
2327 goto out_free_irq;
2328
2329 /* PHY control start*/
2330 ret = sh_eth_phy_start(ndev);
2331 if (ret)
2332 goto out_free_irq;
2333
2334 mdp->is_opened = 1;
2335
2336 return ret;
2337
2338 out_free_irq:
2339 free_irq(ndev->irq, ndev);
2340 out_napi_off:
2341 napi_disable(&mdp->napi);
2342 pm_runtime_put_sync(&mdp->pdev->dev);
2343 return ret;
2344 }
2345
2346 /* Timeout function */
sh_eth_tx_timeout(struct net_device * ndev)2347 static void sh_eth_tx_timeout(struct net_device *ndev)
2348 {
2349 struct sh_eth_private *mdp = netdev_priv(ndev);
2350 struct sh_eth_rxdesc *rxdesc;
2351 int i;
2352
2353 netif_stop_queue(ndev);
2354
2355 netif_err(mdp, timer, ndev,
2356 "transmit timed out, status %8.8x, resetting...\n",
2357 sh_eth_read(ndev, EESR));
2358
2359 /* tx_errors count up */
2360 ndev->stats.tx_errors++;
2361
2362 /* Free all the skbuffs in the Rx queue. */
2363 for (i = 0; i < mdp->num_rx_ring; i++) {
2364 rxdesc = &mdp->rx_ring[i];
2365 rxdesc->status = cpu_to_edmac(mdp, 0);
2366 rxdesc->addr = cpu_to_edmac(mdp, 0xBADF00D0);
2367 dev_kfree_skb(mdp->rx_skbuff[i]);
2368 mdp->rx_skbuff[i] = NULL;
2369 }
2370 for (i = 0; i < mdp->num_tx_ring; i++) {
2371 dev_kfree_skb(mdp->tx_skbuff[i]);
2372 mdp->tx_skbuff[i] = NULL;
2373 }
2374
2375 /* device init */
2376 sh_eth_dev_init(ndev, true);
2377 }
2378
2379 /* Packet transmit function */
sh_eth_start_xmit(struct sk_buff * skb,struct net_device * ndev)2380 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2381 {
2382 struct sh_eth_private *mdp = netdev_priv(ndev);
2383 struct sh_eth_txdesc *txdesc;
2384 dma_addr_t dma_addr;
2385 u32 entry;
2386 unsigned long flags;
2387
2388 spin_lock_irqsave(&mdp->lock, flags);
2389 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2390 if (!sh_eth_txfree(ndev)) {
2391 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2392 netif_stop_queue(ndev);
2393 spin_unlock_irqrestore(&mdp->lock, flags);
2394 return NETDEV_TX_BUSY;
2395 }
2396 }
2397 spin_unlock_irqrestore(&mdp->lock, flags);
2398
2399 if (skb_put_padto(skb, ETH_ZLEN))
2400 return NETDEV_TX_OK;
2401
2402 entry = mdp->cur_tx % mdp->num_tx_ring;
2403 mdp->tx_skbuff[entry] = skb;
2404 txdesc = &mdp->tx_ring[entry];
2405 /* soft swap. */
2406 if (!mdp->cd->hw_swap)
2407 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2408 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2409 DMA_TO_DEVICE);
2410 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2411 kfree_skb(skb);
2412 return NETDEV_TX_OK;
2413 }
2414 txdesc->addr = cpu_to_edmac(mdp, dma_addr);
2415 txdesc->len = cpu_to_edmac(mdp, skb->len << 16);
2416
2417 dma_wmb(); /* TACT bit must be set after all the above writes */
2418 if (entry >= mdp->num_tx_ring - 1)
2419 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2420 else
2421 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2422
2423 mdp->cur_tx++;
2424
2425 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2426 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2427
2428 return NETDEV_TX_OK;
2429 }
2430
2431 /* The statistics registers have write-clear behaviour, which means we
2432 * will lose any increment between the read and write. We mitigate
2433 * this by only clearing when we read a non-zero value, so we will
2434 * never falsely report a total of zero.
2435 */
2436 static void
sh_eth_update_stat(struct net_device * ndev,unsigned long * stat,int reg)2437 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2438 {
2439 u32 delta = sh_eth_read(ndev, reg);
2440
2441 if (delta) {
2442 *stat += delta;
2443 sh_eth_write(ndev, 0, reg);
2444 }
2445 }
2446
sh_eth_get_stats(struct net_device * ndev)2447 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2448 {
2449 struct sh_eth_private *mdp = netdev_priv(ndev);
2450
2451 if (sh_eth_is_rz_fast_ether(mdp))
2452 return &ndev->stats;
2453
2454 if (!mdp->is_opened)
2455 return &ndev->stats;
2456
2457 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2458 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2459 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2460
2461 if (sh_eth_is_gether(mdp)) {
2462 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2463 CERCR);
2464 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2465 CEECR);
2466 } else {
2467 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2468 CNDCR);
2469 }
2470
2471 return &ndev->stats;
2472 }
2473
2474 /* device close function */
sh_eth_close(struct net_device * ndev)2475 static int sh_eth_close(struct net_device *ndev)
2476 {
2477 struct sh_eth_private *mdp = netdev_priv(ndev);
2478
2479 netif_stop_queue(ndev);
2480
2481 /* Serialise with the interrupt handler and NAPI, then disable
2482 * interrupts. We have to clear the irq_enabled flag first to
2483 * ensure that interrupts won't be re-enabled.
2484 */
2485 mdp->irq_enabled = false;
2486 synchronize_irq(ndev->irq);
2487 napi_disable(&mdp->napi);
2488 sh_eth_write(ndev, 0x0000, EESIPR);
2489
2490 sh_eth_dev_exit(ndev);
2491
2492 /* PHY Disconnect */
2493 if (mdp->phydev) {
2494 phy_stop(mdp->phydev);
2495 phy_disconnect(mdp->phydev);
2496 mdp->phydev = NULL;
2497 }
2498
2499 free_irq(ndev->irq, ndev);
2500
2501 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2502 sh_eth_ring_free(ndev);
2503
2504 pm_runtime_put_sync(&mdp->pdev->dev);
2505
2506 mdp->is_opened = 0;
2507
2508 return 0;
2509 }
2510
2511 /* ioctl to device function */
sh_eth_do_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)2512 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2513 {
2514 struct sh_eth_private *mdp = netdev_priv(ndev);
2515 struct phy_device *phydev = mdp->phydev;
2516
2517 if (!netif_running(ndev))
2518 return -EINVAL;
2519
2520 if (!phydev)
2521 return -ENODEV;
2522
2523 return phy_mii_ioctl(phydev, rq, cmd);
2524 }
2525
2526 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
sh_eth_tsu_get_post_reg_offset(struct sh_eth_private * mdp,int entry)2527 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2528 int entry)
2529 {
2530 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2531 }
2532
sh_eth_tsu_get_post_mask(int entry)2533 static u32 sh_eth_tsu_get_post_mask(int entry)
2534 {
2535 return 0x0f << (28 - ((entry % 8) * 4));
2536 }
2537
sh_eth_tsu_get_post_bit(struct sh_eth_private * mdp,int entry)2538 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2539 {
2540 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2541 }
2542
sh_eth_tsu_enable_cam_entry_post(struct net_device * ndev,int entry)2543 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2544 int entry)
2545 {
2546 struct sh_eth_private *mdp = netdev_priv(ndev);
2547 u32 tmp;
2548 void *reg_offset;
2549
2550 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2551 tmp = ioread32(reg_offset);
2552 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2553 }
2554
sh_eth_tsu_disable_cam_entry_post(struct net_device * ndev,int entry)2555 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2556 int entry)
2557 {
2558 struct sh_eth_private *mdp = netdev_priv(ndev);
2559 u32 post_mask, ref_mask, tmp;
2560 void *reg_offset;
2561
2562 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2563 post_mask = sh_eth_tsu_get_post_mask(entry);
2564 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2565
2566 tmp = ioread32(reg_offset);
2567 iowrite32(tmp & ~post_mask, reg_offset);
2568
2569 /* If other port enables, the function returns "true" */
2570 return tmp & ref_mask;
2571 }
2572
sh_eth_tsu_busy(struct net_device * ndev)2573 static int sh_eth_tsu_busy(struct net_device *ndev)
2574 {
2575 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2576 struct sh_eth_private *mdp = netdev_priv(ndev);
2577
2578 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2579 udelay(10);
2580 timeout--;
2581 if (timeout <= 0) {
2582 netdev_err(ndev, "%s: timeout\n", __func__);
2583 return -ETIMEDOUT;
2584 }
2585 }
2586
2587 return 0;
2588 }
2589
sh_eth_tsu_write_entry(struct net_device * ndev,void * reg,const u8 * addr)2590 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2591 const u8 *addr)
2592 {
2593 u32 val;
2594
2595 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2596 iowrite32(val, reg);
2597 if (sh_eth_tsu_busy(ndev) < 0)
2598 return -EBUSY;
2599
2600 val = addr[4] << 8 | addr[5];
2601 iowrite32(val, reg + 4);
2602 if (sh_eth_tsu_busy(ndev) < 0)
2603 return -EBUSY;
2604
2605 return 0;
2606 }
2607
sh_eth_tsu_read_entry(void * reg,u8 * addr)2608 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2609 {
2610 u32 val;
2611
2612 val = ioread32(reg);
2613 addr[0] = (val >> 24) & 0xff;
2614 addr[1] = (val >> 16) & 0xff;
2615 addr[2] = (val >> 8) & 0xff;
2616 addr[3] = val & 0xff;
2617 val = ioread32(reg + 4);
2618 addr[4] = (val >> 8) & 0xff;
2619 addr[5] = val & 0xff;
2620 }
2621
2622
sh_eth_tsu_find_entry(struct net_device * ndev,const u8 * addr)2623 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2624 {
2625 struct sh_eth_private *mdp = netdev_priv(ndev);
2626 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2627 int i;
2628 u8 c_addr[ETH_ALEN];
2629
2630 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2631 sh_eth_tsu_read_entry(reg_offset, c_addr);
2632 if (ether_addr_equal(addr, c_addr))
2633 return i;
2634 }
2635
2636 return -ENOENT;
2637 }
2638
sh_eth_tsu_find_empty(struct net_device * ndev)2639 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2640 {
2641 u8 blank[ETH_ALEN];
2642 int entry;
2643
2644 memset(blank, 0, sizeof(blank));
2645 entry = sh_eth_tsu_find_entry(ndev, blank);
2646 return (entry < 0) ? -ENOMEM : entry;
2647 }
2648
sh_eth_tsu_disable_cam_entry_table(struct net_device * ndev,int entry)2649 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2650 int entry)
2651 {
2652 struct sh_eth_private *mdp = netdev_priv(ndev);
2653 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2654 int ret;
2655 u8 blank[ETH_ALEN];
2656
2657 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2658 ~(1 << (31 - entry)), TSU_TEN);
2659
2660 memset(blank, 0, sizeof(blank));
2661 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2662 if (ret < 0)
2663 return ret;
2664 return 0;
2665 }
2666
sh_eth_tsu_add_entry(struct net_device * ndev,const u8 * addr)2667 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2668 {
2669 struct sh_eth_private *mdp = netdev_priv(ndev);
2670 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2671 int i, ret;
2672
2673 if (!mdp->cd->tsu)
2674 return 0;
2675
2676 i = sh_eth_tsu_find_entry(ndev, addr);
2677 if (i < 0) {
2678 /* No entry found, create one */
2679 i = sh_eth_tsu_find_empty(ndev);
2680 if (i < 0)
2681 return -ENOMEM;
2682 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2683 if (ret < 0)
2684 return ret;
2685
2686 /* Enable the entry */
2687 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2688 (1 << (31 - i)), TSU_TEN);
2689 }
2690
2691 /* Entry found or created, enable POST */
2692 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2693
2694 return 0;
2695 }
2696
sh_eth_tsu_del_entry(struct net_device * ndev,const u8 * addr)2697 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2698 {
2699 struct sh_eth_private *mdp = netdev_priv(ndev);
2700 int i, ret;
2701
2702 if (!mdp->cd->tsu)
2703 return 0;
2704
2705 i = sh_eth_tsu_find_entry(ndev, addr);
2706 if (i) {
2707 /* Entry found */
2708 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2709 goto done;
2710
2711 /* Disable the entry if both ports was disabled */
2712 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2713 if (ret < 0)
2714 return ret;
2715 }
2716 done:
2717 return 0;
2718 }
2719
sh_eth_tsu_purge_all(struct net_device * ndev)2720 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2721 {
2722 struct sh_eth_private *mdp = netdev_priv(ndev);
2723 int i, ret;
2724
2725 if (!mdp->cd->tsu)
2726 return 0;
2727
2728 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2729 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2730 continue;
2731
2732 /* Disable the entry if both ports was disabled */
2733 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2734 if (ret < 0)
2735 return ret;
2736 }
2737
2738 return 0;
2739 }
2740
sh_eth_tsu_purge_mcast(struct net_device * ndev)2741 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2742 {
2743 struct sh_eth_private *mdp = netdev_priv(ndev);
2744 u8 addr[ETH_ALEN];
2745 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2746 int i;
2747
2748 if (!mdp->cd->tsu)
2749 return;
2750
2751 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2752 sh_eth_tsu_read_entry(reg_offset, addr);
2753 if (is_multicast_ether_addr(addr))
2754 sh_eth_tsu_del_entry(ndev, addr);
2755 }
2756 }
2757
2758 /* Update promiscuous flag and multicast filter */
sh_eth_set_rx_mode(struct net_device * ndev)2759 static void sh_eth_set_rx_mode(struct net_device *ndev)
2760 {
2761 struct sh_eth_private *mdp = netdev_priv(ndev);
2762 u32 ecmr_bits;
2763 int mcast_all = 0;
2764 unsigned long flags;
2765
2766 spin_lock_irqsave(&mdp->lock, flags);
2767 /* Initial condition is MCT = 1, PRM = 0.
2768 * Depending on ndev->flags, set PRM or clear MCT
2769 */
2770 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2771 if (mdp->cd->tsu)
2772 ecmr_bits |= ECMR_MCT;
2773
2774 if (!(ndev->flags & IFF_MULTICAST)) {
2775 sh_eth_tsu_purge_mcast(ndev);
2776 mcast_all = 1;
2777 }
2778 if (ndev->flags & IFF_ALLMULTI) {
2779 sh_eth_tsu_purge_mcast(ndev);
2780 ecmr_bits &= ~ECMR_MCT;
2781 mcast_all = 1;
2782 }
2783
2784 if (ndev->flags & IFF_PROMISC) {
2785 sh_eth_tsu_purge_all(ndev);
2786 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2787 } else if (mdp->cd->tsu) {
2788 struct netdev_hw_addr *ha;
2789 netdev_for_each_mc_addr(ha, ndev) {
2790 if (mcast_all && is_multicast_ether_addr(ha->addr))
2791 continue;
2792
2793 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2794 if (!mcast_all) {
2795 sh_eth_tsu_purge_mcast(ndev);
2796 ecmr_bits &= ~ECMR_MCT;
2797 mcast_all = 1;
2798 }
2799 }
2800 }
2801 }
2802
2803 /* update the ethernet mode */
2804 sh_eth_write(ndev, ecmr_bits, ECMR);
2805
2806 spin_unlock_irqrestore(&mdp->lock, flags);
2807 }
2808
sh_eth_get_vtag_index(struct sh_eth_private * mdp)2809 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2810 {
2811 if (!mdp->port)
2812 return TSU_VTAG0;
2813 else
2814 return TSU_VTAG1;
2815 }
2816
sh_eth_vlan_rx_add_vid(struct net_device * ndev,__be16 proto,u16 vid)2817 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2818 __be16 proto, u16 vid)
2819 {
2820 struct sh_eth_private *mdp = netdev_priv(ndev);
2821 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2822
2823 if (unlikely(!mdp->cd->tsu))
2824 return -EPERM;
2825
2826 /* No filtering if vid = 0 */
2827 if (!vid)
2828 return 0;
2829
2830 mdp->vlan_num_ids++;
2831
2832 /* The controller has one VLAN tag HW filter. So, if the filter is
2833 * already enabled, the driver disables it and the filte
2834 */
2835 if (mdp->vlan_num_ids > 1) {
2836 /* disable VLAN filter */
2837 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2838 return 0;
2839 }
2840
2841 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2842 vtag_reg_index);
2843
2844 return 0;
2845 }
2846
sh_eth_vlan_rx_kill_vid(struct net_device * ndev,__be16 proto,u16 vid)2847 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2848 __be16 proto, u16 vid)
2849 {
2850 struct sh_eth_private *mdp = netdev_priv(ndev);
2851 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2852
2853 if (unlikely(!mdp->cd->tsu))
2854 return -EPERM;
2855
2856 /* No filtering if vid = 0 */
2857 if (!vid)
2858 return 0;
2859
2860 mdp->vlan_num_ids--;
2861 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2862
2863 return 0;
2864 }
2865
2866 /* SuperH's TSU register init function */
sh_eth_tsu_init(struct sh_eth_private * mdp)2867 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2868 {
2869 if (sh_eth_is_rz_fast_ether(mdp)) {
2870 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2871 return;
2872 }
2873
2874 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2875 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2876 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2877 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2878 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2879 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2880 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2881 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2882 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2883 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2884 if (sh_eth_is_gether(mdp)) {
2885 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2886 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2887 } else {
2888 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2889 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2890 }
2891 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2892 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2893 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2894 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2895 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2896 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2897 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2898 }
2899
2900 /* MDIO bus release function */
sh_mdio_release(struct sh_eth_private * mdp)2901 static int sh_mdio_release(struct sh_eth_private *mdp)
2902 {
2903 /* unregister mdio bus */
2904 mdiobus_unregister(mdp->mii_bus);
2905
2906 /* free bitbang info */
2907 free_mdio_bitbang(mdp->mii_bus);
2908
2909 return 0;
2910 }
2911
2912 /* MDIO bus init function */
sh_mdio_init(struct sh_eth_private * mdp,struct sh_eth_plat_data * pd)2913 static int sh_mdio_init(struct sh_eth_private *mdp,
2914 struct sh_eth_plat_data *pd)
2915 {
2916 int ret, i;
2917 struct bb_info *bitbang;
2918 struct platform_device *pdev = mdp->pdev;
2919 struct device *dev = &mdp->pdev->dev;
2920
2921 /* create bit control struct for PHY */
2922 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2923 if (!bitbang)
2924 return -ENOMEM;
2925
2926 /* bitbang init */
2927 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2928 bitbang->set_gate = pd->set_mdio_gate;
2929 bitbang->mdi_msk = PIR_MDI;
2930 bitbang->mdo_msk = PIR_MDO;
2931 bitbang->mmd_msk = PIR_MMD;
2932 bitbang->mdc_msk = PIR_MDC;
2933 bitbang->ctrl.ops = &bb_ops;
2934
2935 /* MII controller setting */
2936 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2937 if (!mdp->mii_bus)
2938 return -ENOMEM;
2939
2940 /* Hook up MII support for ethtool */
2941 mdp->mii_bus->name = "sh_mii";
2942 mdp->mii_bus->parent = dev;
2943 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2944 pdev->name, pdev->id);
2945
2946 /* PHY IRQ */
2947 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2948 GFP_KERNEL);
2949 if (!mdp->mii_bus->irq) {
2950 ret = -ENOMEM;
2951 goto out_free_bus;
2952 }
2953
2954 /* register MDIO bus */
2955 if (dev->of_node) {
2956 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2957 } else {
2958 for (i = 0; i < PHY_MAX_ADDR; i++)
2959 mdp->mii_bus->irq[i] = PHY_POLL;
2960 if (pd->phy_irq > 0)
2961 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2962
2963 ret = mdiobus_register(mdp->mii_bus);
2964 }
2965
2966 if (ret)
2967 goto out_free_bus;
2968
2969 return 0;
2970
2971 out_free_bus:
2972 free_mdio_bitbang(mdp->mii_bus);
2973 return ret;
2974 }
2975
sh_eth_get_register_offset(int register_type)2976 static const u16 *sh_eth_get_register_offset(int register_type)
2977 {
2978 const u16 *reg_offset = NULL;
2979
2980 switch (register_type) {
2981 case SH_ETH_REG_GIGABIT:
2982 reg_offset = sh_eth_offset_gigabit;
2983 break;
2984 case SH_ETH_REG_FAST_RZ:
2985 reg_offset = sh_eth_offset_fast_rz;
2986 break;
2987 case SH_ETH_REG_FAST_RCAR:
2988 reg_offset = sh_eth_offset_fast_rcar;
2989 break;
2990 case SH_ETH_REG_FAST_SH4:
2991 reg_offset = sh_eth_offset_fast_sh4;
2992 break;
2993 case SH_ETH_REG_FAST_SH3_SH2:
2994 reg_offset = sh_eth_offset_fast_sh3_sh2;
2995 break;
2996 default:
2997 break;
2998 }
2999
3000 return reg_offset;
3001 }
3002
3003 static const struct net_device_ops sh_eth_netdev_ops = {
3004 .ndo_open = sh_eth_open,
3005 .ndo_stop = sh_eth_close,
3006 .ndo_start_xmit = sh_eth_start_xmit,
3007 .ndo_get_stats = sh_eth_get_stats,
3008 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3009 .ndo_tx_timeout = sh_eth_tx_timeout,
3010 .ndo_do_ioctl = sh_eth_do_ioctl,
3011 .ndo_validate_addr = eth_validate_addr,
3012 .ndo_set_mac_address = eth_mac_addr,
3013 .ndo_change_mtu = eth_change_mtu,
3014 };
3015
3016 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3017 .ndo_open = sh_eth_open,
3018 .ndo_stop = sh_eth_close,
3019 .ndo_start_xmit = sh_eth_start_xmit,
3020 .ndo_get_stats = sh_eth_get_stats,
3021 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3022 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3023 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3024 .ndo_tx_timeout = sh_eth_tx_timeout,
3025 .ndo_do_ioctl = sh_eth_do_ioctl,
3026 .ndo_validate_addr = eth_validate_addr,
3027 .ndo_set_mac_address = eth_mac_addr,
3028 .ndo_change_mtu = eth_change_mtu,
3029 };
3030
3031 #ifdef CONFIG_OF
sh_eth_parse_dt(struct device * dev)3032 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3033 {
3034 struct device_node *np = dev->of_node;
3035 struct sh_eth_plat_data *pdata;
3036 const char *mac_addr;
3037
3038 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3039 if (!pdata)
3040 return NULL;
3041
3042 pdata->phy_interface = of_get_phy_mode(np);
3043
3044 mac_addr = of_get_mac_address(np);
3045 if (mac_addr)
3046 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3047
3048 pdata->no_ether_link =
3049 of_property_read_bool(np, "renesas,no-ether-link");
3050 pdata->ether_link_active_low =
3051 of_property_read_bool(np, "renesas,ether-link-active-low");
3052
3053 return pdata;
3054 }
3055
3056 static const struct of_device_id sh_eth_match_table[] = {
3057 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3058 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3059 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3060 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3061 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3062 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3063 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3064 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3065 { }
3066 };
3067 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3068 #else
sh_eth_parse_dt(struct device * dev)3069 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3070 {
3071 return NULL;
3072 }
3073 #endif
3074
sh_eth_drv_probe(struct platform_device * pdev)3075 static int sh_eth_drv_probe(struct platform_device *pdev)
3076 {
3077 int ret, devno = 0;
3078 struct resource *res;
3079 struct net_device *ndev = NULL;
3080 struct sh_eth_private *mdp = NULL;
3081 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3082 const struct platform_device_id *id = platform_get_device_id(pdev);
3083
3084 /* get base addr */
3085 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3086
3087 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3088 if (!ndev)
3089 return -ENOMEM;
3090
3091 pm_runtime_enable(&pdev->dev);
3092 pm_runtime_get_sync(&pdev->dev);
3093
3094 devno = pdev->id;
3095 if (devno < 0)
3096 devno = 0;
3097
3098 ndev->dma = -1;
3099 ret = platform_get_irq(pdev, 0);
3100 if (ret < 0)
3101 goto out_release;
3102 ndev->irq = ret;
3103
3104 SET_NETDEV_DEV(ndev, &pdev->dev);
3105
3106 mdp = netdev_priv(ndev);
3107 mdp->num_tx_ring = TX_RING_SIZE;
3108 mdp->num_rx_ring = RX_RING_SIZE;
3109 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3110 if (IS_ERR(mdp->addr)) {
3111 ret = PTR_ERR(mdp->addr);
3112 goto out_release;
3113 }
3114
3115 ndev->base_addr = res->start;
3116
3117 spin_lock_init(&mdp->lock);
3118 mdp->pdev = pdev;
3119
3120 if (pdev->dev.of_node)
3121 pd = sh_eth_parse_dt(&pdev->dev);
3122 if (!pd) {
3123 dev_err(&pdev->dev, "no platform data\n");
3124 ret = -EINVAL;
3125 goto out_release;
3126 }
3127
3128 /* get PHY ID */
3129 mdp->phy_id = pd->phy;
3130 mdp->phy_interface = pd->phy_interface;
3131 /* EDMAC endian */
3132 mdp->edmac_endian = pd->edmac_endian;
3133 mdp->no_ether_link = pd->no_ether_link;
3134 mdp->ether_link_active_low = pd->ether_link_active_low;
3135
3136 /* set cpu data */
3137 if (id) {
3138 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3139 } else {
3140 const struct of_device_id *match;
3141
3142 match = of_match_device(of_match_ptr(sh_eth_match_table),
3143 &pdev->dev);
3144 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3145 }
3146 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3147 if (!mdp->reg_offset) {
3148 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3149 mdp->cd->register_type);
3150 ret = -EINVAL;
3151 goto out_release;
3152 }
3153 sh_eth_set_default_cpu_data(mdp->cd);
3154
3155 /* set function */
3156 if (mdp->cd->tsu)
3157 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3158 else
3159 ndev->netdev_ops = &sh_eth_netdev_ops;
3160 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3161 ndev->watchdog_timeo = TX_TIMEOUT;
3162
3163 /* debug message level */
3164 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3165
3166 /* read and set MAC address */
3167 read_mac_address(ndev, pd->mac_addr);
3168 if (!is_valid_ether_addr(ndev->dev_addr)) {
3169 dev_warn(&pdev->dev,
3170 "no valid MAC address supplied, using a random one.\n");
3171 eth_hw_addr_random(ndev);
3172 }
3173
3174 /* ioremap the TSU registers */
3175 if (mdp->cd->tsu) {
3176 struct resource *rtsu;
3177 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3178 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3179 if (IS_ERR(mdp->tsu_addr)) {
3180 ret = PTR_ERR(mdp->tsu_addr);
3181 goto out_release;
3182 }
3183 mdp->port = devno % 2;
3184 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3185 }
3186
3187 /* initialize first or needed device */
3188 if (!devno || pd->needs_init) {
3189 if (mdp->cd->chip_reset)
3190 mdp->cd->chip_reset(ndev);
3191
3192 if (mdp->cd->tsu) {
3193 /* TSU init (Init only)*/
3194 sh_eth_tsu_init(mdp);
3195 }
3196 }
3197
3198 if (mdp->cd->rmiimode)
3199 sh_eth_write(ndev, 0x1, RMIIMODE);
3200
3201 /* MDIO bus init */
3202 ret = sh_mdio_init(mdp, pd);
3203 if (ret) {
3204 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3205 goto out_release;
3206 }
3207
3208 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3209
3210 /* network device register */
3211 ret = register_netdev(ndev);
3212 if (ret)
3213 goto out_napi_del;
3214
3215 /* print device information */
3216 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3217 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3218
3219 pm_runtime_put(&pdev->dev);
3220 platform_set_drvdata(pdev, ndev);
3221
3222 return ret;
3223
3224 out_napi_del:
3225 netif_napi_del(&mdp->napi);
3226 sh_mdio_release(mdp);
3227
3228 out_release:
3229 /* net_dev free */
3230 if (ndev)
3231 free_netdev(ndev);
3232
3233 pm_runtime_put(&pdev->dev);
3234 pm_runtime_disable(&pdev->dev);
3235 return ret;
3236 }
3237
sh_eth_drv_remove(struct platform_device * pdev)3238 static int sh_eth_drv_remove(struct platform_device *pdev)
3239 {
3240 struct net_device *ndev = platform_get_drvdata(pdev);
3241 struct sh_eth_private *mdp = netdev_priv(ndev);
3242
3243 unregister_netdev(ndev);
3244 netif_napi_del(&mdp->napi);
3245 sh_mdio_release(mdp);
3246 pm_runtime_disable(&pdev->dev);
3247 free_netdev(ndev);
3248
3249 return 0;
3250 }
3251
3252 #ifdef CONFIG_PM
3253 #ifdef CONFIG_PM_SLEEP
sh_eth_suspend(struct device * dev)3254 static int sh_eth_suspend(struct device *dev)
3255 {
3256 struct net_device *ndev = dev_get_drvdata(dev);
3257 int ret = 0;
3258
3259 if (netif_running(ndev)) {
3260 netif_device_detach(ndev);
3261 ret = sh_eth_close(ndev);
3262 }
3263
3264 return ret;
3265 }
3266
sh_eth_resume(struct device * dev)3267 static int sh_eth_resume(struct device *dev)
3268 {
3269 struct net_device *ndev = dev_get_drvdata(dev);
3270 int ret = 0;
3271
3272 if (netif_running(ndev)) {
3273 ret = sh_eth_open(ndev);
3274 if (ret < 0)
3275 return ret;
3276 netif_device_attach(ndev);
3277 }
3278
3279 return ret;
3280 }
3281 #endif
3282
sh_eth_runtime_nop(struct device * dev)3283 static int sh_eth_runtime_nop(struct device *dev)
3284 {
3285 /* Runtime PM callback shared between ->runtime_suspend()
3286 * and ->runtime_resume(). Simply returns success.
3287 *
3288 * This driver re-initializes all registers after
3289 * pm_runtime_get_sync() anyway so there is no need
3290 * to save and restore registers here.
3291 */
3292 return 0;
3293 }
3294
3295 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3296 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3297 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3298 };
3299 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3300 #else
3301 #define SH_ETH_PM_OPS NULL
3302 #endif
3303
3304 static struct platform_device_id sh_eth_id_table[] = {
3305 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3306 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3307 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3308 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3309 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3310 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3311 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3312 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3313 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3314 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3315 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3316 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3317 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3318 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3319 { }
3320 };
3321 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3322
3323 static struct platform_driver sh_eth_driver = {
3324 .probe = sh_eth_drv_probe,
3325 .remove = sh_eth_drv_remove,
3326 .id_table = sh_eth_id_table,
3327 .driver = {
3328 .name = CARDNAME,
3329 .pm = SH_ETH_PM_OPS,
3330 .of_match_table = of_match_ptr(sh_eth_match_table),
3331 },
3332 };
3333
3334 module_platform_driver(sh_eth_driver);
3335
3336 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3337 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3338 MODULE_LICENSE("GPL v2");
3339