1 /*
2 * OMAP DMAengine support
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/omap-dma.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_device.h>
22
23 #include "virt-dma.h"
24
25 #define OMAP_SDMA_REQUESTS 127
26 #define OMAP_SDMA_CHANNELS 32
27
28 struct omap_dmadev {
29 struct dma_device ddev;
30 spinlock_t lock;
31 struct tasklet_struct task;
32 struct list_head pending;
33 void __iomem *base;
34 const struct omap_dma_reg *reg_map;
35 struct omap_system_dma_plat_info *plat;
36 bool legacy;
37 unsigned dma_requests;
38 spinlock_t irq_lock;
39 uint32_t irq_enable_mask;
40 struct omap_chan *lch_map[OMAP_SDMA_CHANNELS];
41 };
42
43 struct omap_chan {
44 struct virt_dma_chan vc;
45 struct list_head node;
46 void __iomem *channel_base;
47 const struct omap_dma_reg *reg_map;
48 uint32_t ccr;
49
50 struct dma_slave_config cfg;
51 unsigned dma_sig;
52 bool cyclic;
53 bool paused;
54
55 int dma_ch;
56 struct omap_desc *desc;
57 unsigned sgidx;
58 };
59
60 struct omap_sg {
61 dma_addr_t addr;
62 uint32_t en; /* number of elements (24-bit) */
63 uint32_t fn; /* number of frames (16-bit) */
64 };
65
66 struct omap_desc {
67 struct virt_dma_desc vd;
68 enum dma_transfer_direction dir;
69 dma_addr_t dev_addr;
70
71 int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
72 uint8_t es; /* CSDP_DATA_TYPE_xxx */
73 uint32_t ccr; /* CCR value */
74 uint16_t clnk_ctrl; /* CLNK_CTRL value */
75 uint16_t cicr; /* CICR value */
76 uint32_t csdp; /* CSDP value */
77
78 unsigned sglen;
79 struct omap_sg sg[0];
80 };
81
82 enum {
83 CCR_FS = BIT(5),
84 CCR_READ_PRIORITY = BIT(6),
85 CCR_ENABLE = BIT(7),
86 CCR_AUTO_INIT = BIT(8), /* OMAP1 only */
87 CCR_REPEAT = BIT(9), /* OMAP1 only */
88 CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */
89 CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */
90 CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */
91 CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */
92 CCR_SRC_AMODE_CONSTANT = 0 << 12,
93 CCR_SRC_AMODE_POSTINC = 1 << 12,
94 CCR_SRC_AMODE_SGLIDX = 2 << 12,
95 CCR_SRC_AMODE_DBLIDX = 3 << 12,
96 CCR_DST_AMODE_CONSTANT = 0 << 14,
97 CCR_DST_AMODE_POSTINC = 1 << 14,
98 CCR_DST_AMODE_SGLIDX = 2 << 14,
99 CCR_DST_AMODE_DBLIDX = 3 << 14,
100 CCR_CONSTANT_FILL = BIT(16),
101 CCR_TRANSPARENT_COPY = BIT(17),
102 CCR_BS = BIT(18),
103 CCR_SUPERVISOR = BIT(22),
104 CCR_PREFETCH = BIT(23),
105 CCR_TRIGGER_SRC = BIT(24),
106 CCR_BUFFERING_DISABLE = BIT(25),
107 CCR_WRITE_PRIORITY = BIT(26),
108 CCR_SYNC_ELEMENT = 0,
109 CCR_SYNC_FRAME = CCR_FS,
110 CCR_SYNC_BLOCK = CCR_BS,
111 CCR_SYNC_PACKET = CCR_BS | CCR_FS,
112
113 CSDP_DATA_TYPE_8 = 0,
114 CSDP_DATA_TYPE_16 = 1,
115 CSDP_DATA_TYPE_32 = 2,
116 CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */
117 CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */
118 CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */
119 CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */
120 CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */
121 CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */
122 CSDP_SRC_PACKED = BIT(6),
123 CSDP_SRC_BURST_1 = 0 << 7,
124 CSDP_SRC_BURST_16 = 1 << 7,
125 CSDP_SRC_BURST_32 = 2 << 7,
126 CSDP_SRC_BURST_64 = 3 << 7,
127 CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */
128 CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */
129 CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */
130 CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */
131 CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */
132 CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */
133 CSDP_DST_PACKED = BIT(13),
134 CSDP_DST_BURST_1 = 0 << 14,
135 CSDP_DST_BURST_16 = 1 << 14,
136 CSDP_DST_BURST_32 = 2 << 14,
137 CSDP_DST_BURST_64 = 3 << 14,
138
139 CICR_TOUT_IE = BIT(0), /* OMAP1 only */
140 CICR_DROP_IE = BIT(1),
141 CICR_HALF_IE = BIT(2),
142 CICR_FRAME_IE = BIT(3),
143 CICR_LAST_IE = BIT(4),
144 CICR_BLOCK_IE = BIT(5),
145 CICR_PKT_IE = BIT(7), /* OMAP2+ only */
146 CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */
147 CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */
148 CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */
149 CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */
150 CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */
151
152 CLNK_CTRL_ENABLE_LNK = BIT(15),
153 };
154
155 static const unsigned es_bytes[] = {
156 [CSDP_DATA_TYPE_8] = 1,
157 [CSDP_DATA_TYPE_16] = 2,
158 [CSDP_DATA_TYPE_32] = 4,
159 };
160
161 static struct of_dma_filter_info omap_dma_info = {
162 .filter_fn = omap_dma_filter_fn,
163 };
164
to_omap_dma_dev(struct dma_device * d)165 static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
166 {
167 return container_of(d, struct omap_dmadev, ddev);
168 }
169
to_omap_dma_chan(struct dma_chan * c)170 static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
171 {
172 return container_of(c, struct omap_chan, vc.chan);
173 }
174
to_omap_dma_desc(struct dma_async_tx_descriptor * t)175 static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
176 {
177 return container_of(t, struct omap_desc, vd.tx);
178 }
179
omap_dma_desc_free(struct virt_dma_desc * vd)180 static void omap_dma_desc_free(struct virt_dma_desc *vd)
181 {
182 kfree(container_of(vd, struct omap_desc, vd));
183 }
184
omap_dma_write(uint32_t val,unsigned type,void __iomem * addr)185 static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
186 {
187 switch (type) {
188 case OMAP_DMA_REG_16BIT:
189 writew_relaxed(val, addr);
190 break;
191 case OMAP_DMA_REG_2X16BIT:
192 writew_relaxed(val, addr);
193 writew_relaxed(val >> 16, addr + 2);
194 break;
195 case OMAP_DMA_REG_32BIT:
196 writel_relaxed(val, addr);
197 break;
198 default:
199 WARN_ON(1);
200 }
201 }
202
omap_dma_read(unsigned type,void __iomem * addr)203 static unsigned omap_dma_read(unsigned type, void __iomem *addr)
204 {
205 unsigned val;
206
207 switch (type) {
208 case OMAP_DMA_REG_16BIT:
209 val = readw_relaxed(addr);
210 break;
211 case OMAP_DMA_REG_2X16BIT:
212 val = readw_relaxed(addr);
213 val |= readw_relaxed(addr + 2) << 16;
214 break;
215 case OMAP_DMA_REG_32BIT:
216 val = readl_relaxed(addr);
217 break;
218 default:
219 WARN_ON(1);
220 val = 0;
221 }
222
223 return val;
224 }
225
omap_dma_glbl_write(struct omap_dmadev * od,unsigned reg,unsigned val)226 static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
227 {
228 const struct omap_dma_reg *r = od->reg_map + reg;
229
230 WARN_ON(r->stride);
231
232 omap_dma_write(val, r->type, od->base + r->offset);
233 }
234
omap_dma_glbl_read(struct omap_dmadev * od,unsigned reg)235 static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
236 {
237 const struct omap_dma_reg *r = od->reg_map + reg;
238
239 WARN_ON(r->stride);
240
241 return omap_dma_read(r->type, od->base + r->offset);
242 }
243
omap_dma_chan_write(struct omap_chan * c,unsigned reg,unsigned val)244 static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
245 {
246 const struct omap_dma_reg *r = c->reg_map + reg;
247
248 omap_dma_write(val, r->type, c->channel_base + r->offset);
249 }
250
omap_dma_chan_read(struct omap_chan * c,unsigned reg)251 static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
252 {
253 const struct omap_dma_reg *r = c->reg_map + reg;
254
255 return omap_dma_read(r->type, c->channel_base + r->offset);
256 }
257
omap_dma_clear_csr(struct omap_chan * c)258 static void omap_dma_clear_csr(struct omap_chan *c)
259 {
260 if (dma_omap1())
261 omap_dma_chan_read(c, CSR);
262 else
263 omap_dma_chan_write(c, CSR, ~0);
264 }
265
omap_dma_get_csr(struct omap_chan * c)266 static unsigned omap_dma_get_csr(struct omap_chan *c)
267 {
268 unsigned val = omap_dma_chan_read(c, CSR);
269
270 if (!dma_omap1())
271 omap_dma_chan_write(c, CSR, val);
272
273 return val;
274 }
275
omap_dma_assign(struct omap_dmadev * od,struct omap_chan * c,unsigned lch)276 static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
277 unsigned lch)
278 {
279 c->channel_base = od->base + od->plat->channel_stride * lch;
280
281 od->lch_map[lch] = c;
282 }
283
omap_dma_start(struct omap_chan * c,struct omap_desc * d)284 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
285 {
286 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
287
288 if (__dma_omap15xx(od->plat->dma_attr))
289 omap_dma_chan_write(c, CPC, 0);
290 else
291 omap_dma_chan_write(c, CDAC, 0);
292
293 omap_dma_clear_csr(c);
294
295 /* Enable interrupts */
296 omap_dma_chan_write(c, CICR, d->cicr);
297
298 /* Enable channel */
299 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
300 }
301
omap_dma_stop(struct omap_chan * c)302 static void omap_dma_stop(struct omap_chan *c)
303 {
304 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
305 uint32_t val;
306
307 /* disable irq */
308 omap_dma_chan_write(c, CICR, 0);
309
310 omap_dma_clear_csr(c);
311
312 val = omap_dma_chan_read(c, CCR);
313 if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
314 uint32_t sysconfig;
315 unsigned i;
316
317 sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
318 val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
319 val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
320 omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
321
322 val = omap_dma_chan_read(c, CCR);
323 val &= ~CCR_ENABLE;
324 omap_dma_chan_write(c, CCR, val);
325
326 /* Wait for sDMA FIFO to drain */
327 for (i = 0; ; i++) {
328 val = omap_dma_chan_read(c, CCR);
329 if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
330 break;
331
332 if (i > 100)
333 break;
334
335 udelay(5);
336 }
337
338 if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
339 dev_err(c->vc.chan.device->dev,
340 "DMA drain did not complete on lch %d\n",
341 c->dma_ch);
342
343 omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
344 } else {
345 val &= ~CCR_ENABLE;
346 omap_dma_chan_write(c, CCR, val);
347 }
348
349 mb();
350
351 if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
352 val = omap_dma_chan_read(c, CLNK_CTRL);
353
354 if (dma_omap1())
355 val |= 1 << 14; /* set the STOP_LNK bit */
356 else
357 val &= ~CLNK_CTRL_ENABLE_LNK;
358
359 omap_dma_chan_write(c, CLNK_CTRL, val);
360 }
361 }
362
omap_dma_start_sg(struct omap_chan * c,struct omap_desc * d,unsigned idx)363 static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
364 unsigned idx)
365 {
366 struct omap_sg *sg = d->sg + idx;
367 unsigned cxsa, cxei, cxfi;
368
369 if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
370 cxsa = CDSA;
371 cxei = CDEI;
372 cxfi = CDFI;
373 } else {
374 cxsa = CSSA;
375 cxei = CSEI;
376 cxfi = CSFI;
377 }
378
379 omap_dma_chan_write(c, cxsa, sg->addr);
380 omap_dma_chan_write(c, cxei, 0);
381 omap_dma_chan_write(c, cxfi, 0);
382 omap_dma_chan_write(c, CEN, sg->en);
383 omap_dma_chan_write(c, CFN, sg->fn);
384
385 omap_dma_start(c, d);
386 }
387
omap_dma_start_desc(struct omap_chan * c)388 static void omap_dma_start_desc(struct omap_chan *c)
389 {
390 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
391 struct omap_desc *d;
392 unsigned cxsa, cxei, cxfi;
393
394 if (!vd) {
395 c->desc = NULL;
396 return;
397 }
398
399 list_del(&vd->node);
400
401 c->desc = d = to_omap_dma_desc(&vd->tx);
402 c->sgidx = 0;
403
404 /*
405 * This provides the necessary barrier to ensure data held in
406 * DMA coherent memory is visible to the DMA engine prior to
407 * the transfer starting.
408 */
409 mb();
410
411 omap_dma_chan_write(c, CCR, d->ccr);
412 if (dma_omap1())
413 omap_dma_chan_write(c, CCR2, d->ccr >> 16);
414
415 if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
416 cxsa = CSSA;
417 cxei = CSEI;
418 cxfi = CSFI;
419 } else {
420 cxsa = CDSA;
421 cxei = CDEI;
422 cxfi = CDFI;
423 }
424
425 omap_dma_chan_write(c, cxsa, d->dev_addr);
426 omap_dma_chan_write(c, cxei, 0);
427 omap_dma_chan_write(c, cxfi, d->fi);
428 omap_dma_chan_write(c, CSDP, d->csdp);
429 omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
430
431 omap_dma_start_sg(c, d, 0);
432 }
433
omap_dma_callback(int ch,u16 status,void * data)434 static void omap_dma_callback(int ch, u16 status, void *data)
435 {
436 struct omap_chan *c = data;
437 struct omap_desc *d;
438 unsigned long flags;
439
440 spin_lock_irqsave(&c->vc.lock, flags);
441 d = c->desc;
442 if (d) {
443 if (!c->cyclic) {
444 if (++c->sgidx < d->sglen) {
445 omap_dma_start_sg(c, d, c->sgidx);
446 } else {
447 omap_dma_start_desc(c);
448 vchan_cookie_complete(&d->vd);
449 }
450 } else {
451 vchan_cyclic_callback(&d->vd);
452 }
453 }
454 spin_unlock_irqrestore(&c->vc.lock, flags);
455 }
456
457 /*
458 * This callback schedules all pending channels. We could be more
459 * clever here by postponing allocation of the real DMA channels to
460 * this point, and freeing them when our virtual channel becomes idle.
461 *
462 * We would then need to deal with 'all channels in-use'
463 */
omap_dma_sched(unsigned long data)464 static void omap_dma_sched(unsigned long data)
465 {
466 struct omap_dmadev *d = (struct omap_dmadev *)data;
467 LIST_HEAD(head);
468
469 spin_lock_irq(&d->lock);
470 list_splice_tail_init(&d->pending, &head);
471 spin_unlock_irq(&d->lock);
472
473 while (!list_empty(&head)) {
474 struct omap_chan *c = list_first_entry(&head,
475 struct omap_chan, node);
476
477 spin_lock_irq(&c->vc.lock);
478 list_del_init(&c->node);
479 omap_dma_start_desc(c);
480 spin_unlock_irq(&c->vc.lock);
481 }
482 }
483
omap_dma_irq(int irq,void * devid)484 static irqreturn_t omap_dma_irq(int irq, void *devid)
485 {
486 struct omap_dmadev *od = devid;
487 unsigned status, channel;
488
489 spin_lock(&od->irq_lock);
490
491 status = omap_dma_glbl_read(od, IRQSTATUS_L1);
492 status &= od->irq_enable_mask;
493 if (status == 0) {
494 spin_unlock(&od->irq_lock);
495 return IRQ_NONE;
496 }
497
498 while ((channel = ffs(status)) != 0) {
499 unsigned mask, csr;
500 struct omap_chan *c;
501
502 channel -= 1;
503 mask = BIT(channel);
504 status &= ~mask;
505
506 c = od->lch_map[channel];
507 if (c == NULL) {
508 /* This should never happen */
509 dev_err(od->ddev.dev, "invalid channel %u\n", channel);
510 continue;
511 }
512
513 csr = omap_dma_get_csr(c);
514 omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
515
516 omap_dma_callback(channel, csr, c);
517 }
518
519 spin_unlock(&od->irq_lock);
520
521 return IRQ_HANDLED;
522 }
523
omap_dma_alloc_chan_resources(struct dma_chan * chan)524 static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
525 {
526 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
527 struct omap_chan *c = to_omap_dma_chan(chan);
528 int ret;
529
530 if (od->legacy) {
531 ret = omap_request_dma(c->dma_sig, "DMA engine",
532 omap_dma_callback, c, &c->dma_ch);
533 } else {
534 ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL,
535 &c->dma_ch);
536 }
537
538 dev_dbg(od->ddev.dev, "allocating channel %u for %u\n",
539 c->dma_ch, c->dma_sig);
540
541 if (ret >= 0) {
542 omap_dma_assign(od, c, c->dma_ch);
543
544 if (!od->legacy) {
545 unsigned val;
546
547 spin_lock_irq(&od->irq_lock);
548 val = BIT(c->dma_ch);
549 omap_dma_glbl_write(od, IRQSTATUS_L1, val);
550 od->irq_enable_mask |= val;
551 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
552
553 val = omap_dma_glbl_read(od, IRQENABLE_L0);
554 val &= ~BIT(c->dma_ch);
555 omap_dma_glbl_write(od, IRQENABLE_L0, val);
556 spin_unlock_irq(&od->irq_lock);
557 }
558 }
559
560 if (dma_omap1()) {
561 if (__dma_omap16xx(od->plat->dma_attr)) {
562 c->ccr = CCR_OMAP31_DISABLE;
563 /* Duplicate what plat-omap/dma.c does */
564 c->ccr |= c->dma_ch + 1;
565 } else {
566 c->ccr = c->dma_sig & 0x1f;
567 }
568 } else {
569 c->ccr = c->dma_sig & 0x1f;
570 c->ccr |= (c->dma_sig & ~0x1f) << 14;
571 }
572 if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
573 c->ccr |= CCR_BUFFERING_DISABLE;
574
575 return ret;
576 }
577
omap_dma_free_chan_resources(struct dma_chan * chan)578 static void omap_dma_free_chan_resources(struct dma_chan *chan)
579 {
580 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
581 struct omap_chan *c = to_omap_dma_chan(chan);
582
583 if (!od->legacy) {
584 spin_lock_irq(&od->irq_lock);
585 od->irq_enable_mask &= ~BIT(c->dma_ch);
586 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
587 spin_unlock_irq(&od->irq_lock);
588 }
589
590 c->channel_base = NULL;
591 od->lch_map[c->dma_ch] = NULL;
592 vchan_free_chan_resources(&c->vc);
593 omap_free_dma(c->dma_ch);
594
595 dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
596 c->dma_sig = 0;
597 }
598
omap_dma_sg_size(struct omap_sg * sg)599 static size_t omap_dma_sg_size(struct omap_sg *sg)
600 {
601 return sg->en * sg->fn;
602 }
603
omap_dma_desc_size(struct omap_desc * d)604 static size_t omap_dma_desc_size(struct omap_desc *d)
605 {
606 unsigned i;
607 size_t size;
608
609 for (size = i = 0; i < d->sglen; i++)
610 size += omap_dma_sg_size(&d->sg[i]);
611
612 return size * es_bytes[d->es];
613 }
614
omap_dma_desc_size_pos(struct omap_desc * d,dma_addr_t addr)615 static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
616 {
617 unsigned i;
618 size_t size, es_size = es_bytes[d->es];
619
620 for (size = i = 0; i < d->sglen; i++) {
621 size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
622
623 if (size)
624 size += this_size;
625 else if (addr >= d->sg[i].addr &&
626 addr < d->sg[i].addr + this_size)
627 size += d->sg[i].addr + this_size - addr;
628 }
629 return size;
630 }
631
632 /*
633 * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
634 * read before the DMA controller finished disabling the channel.
635 */
omap_dma_chan_read_3_3(struct omap_chan * c,unsigned reg)636 static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
637 {
638 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
639 uint32_t val;
640
641 val = omap_dma_chan_read(c, reg);
642 if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
643 val = omap_dma_chan_read(c, reg);
644
645 return val;
646 }
647
omap_dma_get_src_pos(struct omap_chan * c)648 static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
649 {
650 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
651 dma_addr_t addr, cdac;
652
653 if (__dma_omap15xx(od->plat->dma_attr)) {
654 addr = omap_dma_chan_read(c, CPC);
655 } else {
656 addr = omap_dma_chan_read_3_3(c, CSAC);
657 cdac = omap_dma_chan_read_3_3(c, CDAC);
658
659 /*
660 * CDAC == 0 indicates that the DMA transfer on the channel has
661 * not been started (no data has been transferred so far).
662 * Return the programmed source start address in this case.
663 */
664 if (cdac == 0)
665 addr = omap_dma_chan_read(c, CSSA);
666 }
667
668 if (dma_omap1())
669 addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
670
671 return addr;
672 }
673
omap_dma_get_dst_pos(struct omap_chan * c)674 static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
675 {
676 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
677 dma_addr_t addr;
678
679 if (__dma_omap15xx(od->plat->dma_attr)) {
680 addr = omap_dma_chan_read(c, CPC);
681 } else {
682 addr = omap_dma_chan_read_3_3(c, CDAC);
683
684 /*
685 * CDAC == 0 indicates that the DMA transfer on the channel
686 * has not been started (no data has been transferred so
687 * far). Return the programmed destination start address in
688 * this case.
689 */
690 if (addr == 0)
691 addr = omap_dma_chan_read(c, CDSA);
692 }
693
694 if (dma_omap1())
695 addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
696
697 return addr;
698 }
699
omap_dma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)700 static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
701 dma_cookie_t cookie, struct dma_tx_state *txstate)
702 {
703 struct omap_chan *c = to_omap_dma_chan(chan);
704 struct virt_dma_desc *vd;
705 enum dma_status ret;
706 unsigned long flags;
707
708 ret = dma_cookie_status(chan, cookie, txstate);
709 if (ret == DMA_COMPLETE || !txstate)
710 return ret;
711
712 spin_lock_irqsave(&c->vc.lock, flags);
713 vd = vchan_find_desc(&c->vc, cookie);
714 if (vd) {
715 txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
716 } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
717 struct omap_desc *d = c->desc;
718 dma_addr_t pos;
719
720 if (d->dir == DMA_MEM_TO_DEV)
721 pos = omap_dma_get_src_pos(c);
722 else if (d->dir == DMA_DEV_TO_MEM)
723 pos = omap_dma_get_dst_pos(c);
724 else
725 pos = 0;
726
727 txstate->residue = omap_dma_desc_size_pos(d, pos);
728 } else {
729 txstate->residue = 0;
730 }
731 spin_unlock_irqrestore(&c->vc.lock, flags);
732
733 return ret;
734 }
735
omap_dma_issue_pending(struct dma_chan * chan)736 static void omap_dma_issue_pending(struct dma_chan *chan)
737 {
738 struct omap_chan *c = to_omap_dma_chan(chan);
739 unsigned long flags;
740
741 spin_lock_irqsave(&c->vc.lock, flags);
742 if (vchan_issue_pending(&c->vc) && !c->desc) {
743 /*
744 * c->cyclic is used only by audio and in this case the DMA need
745 * to be started without delay.
746 */
747 if (!c->cyclic) {
748 struct omap_dmadev *d = to_omap_dma_dev(chan->device);
749 spin_lock(&d->lock);
750 if (list_empty(&c->node))
751 list_add_tail(&c->node, &d->pending);
752 spin_unlock(&d->lock);
753 tasklet_schedule(&d->task);
754 } else {
755 omap_dma_start_desc(c);
756 }
757 }
758 spin_unlock_irqrestore(&c->vc.lock, flags);
759 }
760
omap_dma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned sglen,enum dma_transfer_direction dir,unsigned long tx_flags,void * context)761 static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
762 struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
763 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
764 {
765 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
766 struct omap_chan *c = to_omap_dma_chan(chan);
767 enum dma_slave_buswidth dev_width;
768 struct scatterlist *sgent;
769 struct omap_desc *d;
770 dma_addr_t dev_addr;
771 unsigned i, j = 0, es, en, frame_bytes;
772 u32 burst;
773
774 if (dir == DMA_DEV_TO_MEM) {
775 dev_addr = c->cfg.src_addr;
776 dev_width = c->cfg.src_addr_width;
777 burst = c->cfg.src_maxburst;
778 } else if (dir == DMA_MEM_TO_DEV) {
779 dev_addr = c->cfg.dst_addr;
780 dev_width = c->cfg.dst_addr_width;
781 burst = c->cfg.dst_maxburst;
782 } else {
783 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
784 return NULL;
785 }
786
787 /* Bus width translates to the element size (ES) */
788 switch (dev_width) {
789 case DMA_SLAVE_BUSWIDTH_1_BYTE:
790 es = CSDP_DATA_TYPE_8;
791 break;
792 case DMA_SLAVE_BUSWIDTH_2_BYTES:
793 es = CSDP_DATA_TYPE_16;
794 break;
795 case DMA_SLAVE_BUSWIDTH_4_BYTES:
796 es = CSDP_DATA_TYPE_32;
797 break;
798 default: /* not reached */
799 return NULL;
800 }
801
802 /* Now allocate and setup the descriptor. */
803 d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
804 if (!d)
805 return NULL;
806
807 d->dir = dir;
808 d->dev_addr = dev_addr;
809 d->es = es;
810
811 d->ccr = c->ccr | CCR_SYNC_FRAME;
812 if (dir == DMA_DEV_TO_MEM)
813 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
814 else
815 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
816
817 d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
818 d->csdp = es;
819
820 if (dma_omap1()) {
821 d->cicr |= CICR_TOUT_IE;
822
823 if (dir == DMA_DEV_TO_MEM)
824 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
825 else
826 d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
827 } else {
828 if (dir == DMA_DEV_TO_MEM)
829 d->ccr |= CCR_TRIGGER_SRC;
830
831 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
832 }
833 if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
834 d->clnk_ctrl = c->dma_ch;
835
836 /*
837 * Build our scatterlist entries: each contains the address,
838 * the number of elements (EN) in each frame, and the number of
839 * frames (FN). Number of bytes for this entry = ES * EN * FN.
840 *
841 * Burst size translates to number of elements with frame sync.
842 * Note: DMA engine defines burst to be the number of dev-width
843 * transfers.
844 */
845 en = burst;
846 frame_bytes = es_bytes[es] * en;
847 for_each_sg(sgl, sgent, sglen, i) {
848 d->sg[j].addr = sg_dma_address(sgent);
849 d->sg[j].en = en;
850 d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
851 j++;
852 }
853
854 d->sglen = j;
855
856 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
857 }
858
omap_dma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction dir,unsigned long flags)859 static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
860 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
861 size_t period_len, enum dma_transfer_direction dir, unsigned long flags)
862 {
863 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
864 struct omap_chan *c = to_omap_dma_chan(chan);
865 enum dma_slave_buswidth dev_width;
866 struct omap_desc *d;
867 dma_addr_t dev_addr;
868 unsigned es;
869 u32 burst;
870
871 if (dir == DMA_DEV_TO_MEM) {
872 dev_addr = c->cfg.src_addr;
873 dev_width = c->cfg.src_addr_width;
874 burst = c->cfg.src_maxburst;
875 } else if (dir == DMA_MEM_TO_DEV) {
876 dev_addr = c->cfg.dst_addr;
877 dev_width = c->cfg.dst_addr_width;
878 burst = c->cfg.dst_maxburst;
879 } else {
880 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
881 return NULL;
882 }
883
884 /* Bus width translates to the element size (ES) */
885 switch (dev_width) {
886 case DMA_SLAVE_BUSWIDTH_1_BYTE:
887 es = CSDP_DATA_TYPE_8;
888 break;
889 case DMA_SLAVE_BUSWIDTH_2_BYTES:
890 es = CSDP_DATA_TYPE_16;
891 break;
892 case DMA_SLAVE_BUSWIDTH_4_BYTES:
893 es = CSDP_DATA_TYPE_32;
894 break;
895 default: /* not reached */
896 return NULL;
897 }
898
899 /* Now allocate and setup the descriptor. */
900 d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
901 if (!d)
902 return NULL;
903
904 d->dir = dir;
905 d->dev_addr = dev_addr;
906 d->fi = burst;
907 d->es = es;
908 d->sg[0].addr = buf_addr;
909 d->sg[0].en = period_len / es_bytes[es];
910 d->sg[0].fn = buf_len / period_len;
911 d->sglen = 1;
912
913 d->ccr = c->ccr;
914 if (dir == DMA_DEV_TO_MEM)
915 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
916 else
917 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
918
919 d->cicr = CICR_DROP_IE;
920 if (flags & DMA_PREP_INTERRUPT)
921 d->cicr |= CICR_FRAME_IE;
922
923 d->csdp = es;
924
925 if (dma_omap1()) {
926 d->cicr |= CICR_TOUT_IE;
927
928 if (dir == DMA_DEV_TO_MEM)
929 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
930 else
931 d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
932 } else {
933 if (burst)
934 d->ccr |= CCR_SYNC_PACKET;
935 else
936 d->ccr |= CCR_SYNC_ELEMENT;
937
938 if (dir == DMA_DEV_TO_MEM) {
939 d->ccr |= CCR_TRIGGER_SRC;
940 d->csdp |= CSDP_DST_PACKED;
941 } else {
942 d->csdp |= CSDP_SRC_PACKED;
943 }
944
945 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
946
947 d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
948 }
949
950 if (__dma_omap15xx(od->plat->dma_attr))
951 d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
952 else
953 d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
954
955 c->cyclic = true;
956
957 return vchan_tx_prep(&c->vc, &d->vd, flags);
958 }
959
omap_dma_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long tx_flags)960 static struct dma_async_tx_descriptor *omap_dma_prep_dma_memcpy(
961 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
962 size_t len, unsigned long tx_flags)
963 {
964 struct omap_chan *c = to_omap_dma_chan(chan);
965 struct omap_desc *d;
966 uint8_t data_type;
967
968 d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
969 if (!d)
970 return NULL;
971
972 data_type = __ffs((src | dest | len));
973 if (data_type > CSDP_DATA_TYPE_32)
974 data_type = CSDP_DATA_TYPE_32;
975
976 d->dir = DMA_MEM_TO_MEM;
977 d->dev_addr = src;
978 d->fi = 0;
979 d->es = data_type;
980 d->sg[0].en = len / BIT(data_type);
981 d->sg[0].fn = 1;
982 d->sg[0].addr = dest;
983 d->sglen = 1;
984 d->ccr = c->ccr;
985 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC;
986
987 d->cicr = CICR_DROP_IE;
988 if (tx_flags & DMA_PREP_INTERRUPT)
989 d->cicr |= CICR_FRAME_IE;
990
991 d->csdp = data_type;
992
993 if (dma_omap1()) {
994 d->cicr |= CICR_TOUT_IE;
995 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF;
996 } else {
997 d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED;
998 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
999 d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
1000 }
1001
1002 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
1003 }
1004
omap_dma_slave_config(struct dma_chan * chan,struct dma_slave_config * cfg)1005 static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
1006 {
1007 struct omap_chan *c = to_omap_dma_chan(chan);
1008
1009 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
1010 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
1011 return -EINVAL;
1012
1013 memcpy(&c->cfg, cfg, sizeof(c->cfg));
1014
1015 return 0;
1016 }
1017
omap_dma_terminate_all(struct dma_chan * chan)1018 static int omap_dma_terminate_all(struct dma_chan *chan)
1019 {
1020 struct omap_chan *c = to_omap_dma_chan(chan);
1021 struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
1022 unsigned long flags;
1023 LIST_HEAD(head);
1024
1025 spin_lock_irqsave(&c->vc.lock, flags);
1026
1027 /* Prevent this channel being scheduled */
1028 spin_lock(&d->lock);
1029 list_del_init(&c->node);
1030 spin_unlock(&d->lock);
1031
1032 /*
1033 * Stop DMA activity: we assume the callback will not be called
1034 * after omap_dma_stop() returns (even if it does, it will see
1035 * c->desc is NULL and exit.)
1036 */
1037 if (c->desc) {
1038 omap_dma_desc_free(&c->desc->vd);
1039 c->desc = NULL;
1040 /* Avoid stopping the dma twice */
1041 if (!c->paused)
1042 omap_dma_stop(c);
1043 }
1044
1045 if (c->cyclic) {
1046 c->cyclic = false;
1047 c->paused = false;
1048 }
1049
1050 vchan_get_all_descriptors(&c->vc, &head);
1051 spin_unlock_irqrestore(&c->vc.lock, flags);
1052 vchan_dma_desc_free_list(&c->vc, &head);
1053
1054 return 0;
1055 }
1056
omap_dma_pause(struct dma_chan * chan)1057 static int omap_dma_pause(struct dma_chan *chan)
1058 {
1059 struct omap_chan *c = to_omap_dma_chan(chan);
1060
1061 /* Pause/Resume only allowed with cyclic mode */
1062 if (!c->cyclic)
1063 return -EINVAL;
1064
1065 if (!c->paused) {
1066 omap_dma_stop(c);
1067 c->paused = true;
1068 }
1069
1070 return 0;
1071 }
1072
omap_dma_resume(struct dma_chan * chan)1073 static int omap_dma_resume(struct dma_chan *chan)
1074 {
1075 struct omap_chan *c = to_omap_dma_chan(chan);
1076
1077 /* Pause/Resume only allowed with cyclic mode */
1078 if (!c->cyclic)
1079 return -EINVAL;
1080
1081 if (c->paused) {
1082 mb();
1083
1084 /* Restore channel link register */
1085 omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl);
1086
1087 omap_dma_start(c, c->desc);
1088 c->paused = false;
1089 }
1090
1091 return 0;
1092 }
1093
omap_dma_chan_init(struct omap_dmadev * od)1094 static int omap_dma_chan_init(struct omap_dmadev *od)
1095 {
1096 struct omap_chan *c;
1097
1098 c = kzalloc(sizeof(*c), GFP_KERNEL);
1099 if (!c)
1100 return -ENOMEM;
1101
1102 c->reg_map = od->reg_map;
1103 c->vc.desc_free = omap_dma_desc_free;
1104 vchan_init(&c->vc, &od->ddev);
1105 INIT_LIST_HEAD(&c->node);
1106
1107 return 0;
1108 }
1109
omap_dma_free(struct omap_dmadev * od)1110 static void omap_dma_free(struct omap_dmadev *od)
1111 {
1112 tasklet_kill(&od->task);
1113 while (!list_empty(&od->ddev.channels)) {
1114 struct omap_chan *c = list_first_entry(&od->ddev.channels,
1115 struct omap_chan, vc.chan.device_node);
1116
1117 list_del(&c->vc.chan.device_node);
1118 tasklet_kill(&c->vc.task);
1119 kfree(c);
1120 }
1121 }
1122
1123 #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1124 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1125 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1126
omap_dma_probe(struct platform_device * pdev)1127 static int omap_dma_probe(struct platform_device *pdev)
1128 {
1129 struct omap_dmadev *od;
1130 struct resource *res;
1131 int rc, i, irq;
1132
1133 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
1134 if (!od)
1135 return -ENOMEM;
1136
1137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1138 od->base = devm_ioremap_resource(&pdev->dev, res);
1139 if (IS_ERR(od->base))
1140 return PTR_ERR(od->base);
1141
1142 od->plat = omap_get_plat_info();
1143 if (!od->plat)
1144 return -EPROBE_DEFER;
1145
1146 od->reg_map = od->plat->reg_map;
1147
1148 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
1149 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
1150 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
1151 od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
1152 od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
1153 od->ddev.device_tx_status = omap_dma_tx_status;
1154 od->ddev.device_issue_pending = omap_dma_issue_pending;
1155 od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
1156 od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
1157 od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy;
1158 od->ddev.device_config = omap_dma_slave_config;
1159 od->ddev.device_pause = omap_dma_pause;
1160 od->ddev.device_resume = omap_dma_resume;
1161 od->ddev.device_terminate_all = omap_dma_terminate_all;
1162 od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS;
1163 od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS;
1164 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1165 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1166 od->ddev.dev = &pdev->dev;
1167 INIT_LIST_HEAD(&od->ddev.channels);
1168 INIT_LIST_HEAD(&od->pending);
1169 spin_lock_init(&od->lock);
1170 spin_lock_init(&od->irq_lock);
1171
1172 tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
1173
1174 od->dma_requests = OMAP_SDMA_REQUESTS;
1175 if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
1176 "dma-requests",
1177 &od->dma_requests)) {
1178 dev_info(&pdev->dev,
1179 "Missing dma-requests property, using %u.\n",
1180 OMAP_SDMA_REQUESTS);
1181 }
1182
1183 for (i = 0; i < OMAP_SDMA_CHANNELS; i++) {
1184 rc = omap_dma_chan_init(od);
1185 if (rc) {
1186 omap_dma_free(od);
1187 return rc;
1188 }
1189 }
1190
1191 irq = platform_get_irq(pdev, 1);
1192 if (irq <= 0) {
1193 dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
1194 od->legacy = true;
1195 } else {
1196 /* Disable all interrupts */
1197 od->irq_enable_mask = 0;
1198 omap_dma_glbl_write(od, IRQENABLE_L1, 0);
1199
1200 rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
1201 IRQF_SHARED, "omap-dma-engine", od);
1202 if (rc)
1203 return rc;
1204 }
1205
1206 rc = dma_async_device_register(&od->ddev);
1207 if (rc) {
1208 pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
1209 rc);
1210 omap_dma_free(od);
1211 return rc;
1212 }
1213
1214 platform_set_drvdata(pdev, od);
1215
1216 if (pdev->dev.of_node) {
1217 omap_dma_info.dma_cap = od->ddev.cap_mask;
1218
1219 /* Device-tree DMA controller registration */
1220 rc = of_dma_controller_register(pdev->dev.of_node,
1221 of_dma_simple_xlate, &omap_dma_info);
1222 if (rc) {
1223 pr_warn("OMAP-DMA: failed to register DMA controller\n");
1224 dma_async_device_unregister(&od->ddev);
1225 omap_dma_free(od);
1226 }
1227 }
1228
1229 dev_info(&pdev->dev, "OMAP DMA engine driver\n");
1230
1231 return rc;
1232 }
1233
omap_dma_remove(struct platform_device * pdev)1234 static int omap_dma_remove(struct platform_device *pdev)
1235 {
1236 struct omap_dmadev *od = platform_get_drvdata(pdev);
1237
1238 if (pdev->dev.of_node)
1239 of_dma_controller_free(pdev->dev.of_node);
1240
1241 dma_async_device_unregister(&od->ddev);
1242
1243 if (!od->legacy) {
1244 /* Disable all interrupts */
1245 omap_dma_glbl_write(od, IRQENABLE_L0, 0);
1246 }
1247
1248 omap_dma_free(od);
1249
1250 return 0;
1251 }
1252
1253 static const struct of_device_id omap_dma_match[] = {
1254 { .compatible = "ti,omap2420-sdma", },
1255 { .compatible = "ti,omap2430-sdma", },
1256 { .compatible = "ti,omap3430-sdma", },
1257 { .compatible = "ti,omap3630-sdma", },
1258 { .compatible = "ti,omap4430-sdma", },
1259 {},
1260 };
1261 MODULE_DEVICE_TABLE(of, omap_dma_match);
1262
1263 static struct platform_driver omap_dma_driver = {
1264 .probe = omap_dma_probe,
1265 .remove = omap_dma_remove,
1266 .driver = {
1267 .name = "omap-dma-engine",
1268 .of_match_table = of_match_ptr(omap_dma_match),
1269 },
1270 };
1271
omap_dma_filter_fn(struct dma_chan * chan,void * param)1272 bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
1273 {
1274 if (chan->device->dev->driver == &omap_dma_driver.driver) {
1275 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
1276 struct omap_chan *c = to_omap_dma_chan(chan);
1277 unsigned req = *(unsigned *)param;
1278
1279 if (req <= od->dma_requests) {
1280 c->dma_sig = req;
1281 return true;
1282 }
1283 }
1284 return false;
1285 }
1286 EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
1287
omap_dma_init(void)1288 static int omap_dma_init(void)
1289 {
1290 return platform_driver_register(&omap_dma_driver);
1291 }
1292 subsys_initcall(omap_dma_init);
1293
omap_dma_exit(void)1294 static void __exit omap_dma_exit(void)
1295 {
1296 platform_driver_unregister(&omap_dma_driver);
1297 }
1298 module_exit(omap_dma_exit);
1299
1300 MODULE_AUTHOR("Russell King");
1301 MODULE_LICENSE("GPL");
1302