1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/mmc/sdhci-pci-data.h>
29
30 #include "sdhci.h"
31 #include "sdhci-pci.h"
32 #include "sdhci-pci-o2micro.h"
33
34 /*****************************************************************************\
35 * *
36 * Hardware specific quirk handling *
37 * *
38 \*****************************************************************************/
39
ricoh_probe(struct sdhci_pci_chip * chip)40 static int ricoh_probe(struct sdhci_pci_chip *chip)
41 {
42 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
43 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
44 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
45 return 0;
46 }
47
ricoh_mmc_probe_slot(struct sdhci_pci_slot * slot)48 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
49 {
50 slot->host->caps =
51 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
52 & SDHCI_TIMEOUT_CLK_MASK) |
53
54 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
55 & SDHCI_CLOCK_BASE_MASK) |
56
57 SDHCI_TIMEOUT_CLK_UNIT |
58 SDHCI_CAN_VDD_330 |
59 SDHCI_CAN_DO_HISPD |
60 SDHCI_CAN_DO_SDMA;
61 return 0;
62 }
63
ricoh_mmc_resume(struct sdhci_pci_chip * chip)64 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
65 {
66 /* Apply a delay to allow controller to settle */
67 /* Otherwise it becomes confused if card state changed
68 during suspend */
69 msleep(500);
70 return 0;
71 }
72
73 static const struct sdhci_pci_fixes sdhci_ricoh = {
74 .probe = ricoh_probe,
75 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
76 SDHCI_QUIRK_FORCE_DMA |
77 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
78 };
79
80 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
81 .probe_slot = ricoh_mmc_probe_slot,
82 .resume = ricoh_mmc_resume,
83 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
84 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
85 SDHCI_QUIRK_NO_CARD_NO_RESET |
86 SDHCI_QUIRK_MISSING_CAPS
87 };
88
89 static const struct sdhci_pci_fixes sdhci_ene_712 = {
90 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_BROKEN_DMA,
92 };
93
94 static const struct sdhci_pci_fixes sdhci_ene_714 = {
95 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
96 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
97 SDHCI_QUIRK_BROKEN_DMA,
98 };
99
100 static const struct sdhci_pci_fixes sdhci_cafe = {
101 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
102 SDHCI_QUIRK_NO_BUSY_IRQ |
103 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
104 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
105 };
106
107 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
108 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
109 };
110
mrst_hc_probe_slot(struct sdhci_pci_slot * slot)111 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
112 {
113 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
114 return 0;
115 }
116
117 /*
118 * ADMA operation is disabled for Moorestown platform due to
119 * hardware bugs.
120 */
mrst_hc_probe(struct sdhci_pci_chip * chip)121 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
122 {
123 /*
124 * slots number is fixed here for MRST as SDIO3/5 are never used and
125 * have hardware bugs.
126 */
127 chip->num_slots = 1;
128 return 0;
129 }
130
pch_hc_probe_slot(struct sdhci_pci_slot * slot)131 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
132 {
133 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
134 return 0;
135 }
136
137 #ifdef CONFIG_PM
138
sdhci_pci_sd_cd(int irq,void * dev_id)139 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
140 {
141 struct sdhci_pci_slot *slot = dev_id;
142 struct sdhci_host *host = slot->host;
143
144 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
145 return IRQ_HANDLED;
146 }
147
sdhci_pci_add_own_cd(struct sdhci_pci_slot * slot)148 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
149 {
150 int err, irq, gpio = slot->cd_gpio;
151
152 slot->cd_gpio = -EINVAL;
153 slot->cd_irq = -EINVAL;
154
155 if (!gpio_is_valid(gpio))
156 return;
157
158 err = gpio_request(gpio, "sd_cd");
159 if (err < 0)
160 goto out;
161
162 err = gpio_direction_input(gpio);
163 if (err < 0)
164 goto out_free;
165
166 irq = gpio_to_irq(gpio);
167 if (irq < 0)
168 goto out_free;
169
170 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
171 IRQF_TRIGGER_FALLING, "sd_cd", slot);
172 if (err)
173 goto out_free;
174
175 slot->cd_gpio = gpio;
176 slot->cd_irq = irq;
177
178 return;
179
180 out_free:
181 gpio_free(gpio);
182 out:
183 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
184 }
185
sdhci_pci_remove_own_cd(struct sdhci_pci_slot * slot)186 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
187 {
188 if (slot->cd_irq >= 0)
189 free_irq(slot->cd_irq, slot);
190 if (gpio_is_valid(slot->cd_gpio))
191 gpio_free(slot->cd_gpio);
192 }
193
194 #else
195
sdhci_pci_add_own_cd(struct sdhci_pci_slot * slot)196 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
197 {
198 }
199
sdhci_pci_remove_own_cd(struct sdhci_pci_slot * slot)200 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
201 {
202 }
203
204 #endif
205
mfd_emmc_probe_slot(struct sdhci_pci_slot * slot)206 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
207 {
208 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
209 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
210 MMC_CAP2_HC_ERASE_SZ;
211 return 0;
212 }
213
mfd_sdio_probe_slot(struct sdhci_pci_slot * slot)214 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
215 {
216 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
217 return 0;
218 }
219
220 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
221 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
222 .probe_slot = mrst_hc_probe_slot,
223 };
224
225 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
226 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
227 .probe = mrst_hc_probe,
228 };
229
230 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
231 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
232 .allow_runtime_pm = true,
233 .own_cd_for_runtime_pm = true,
234 };
235
236 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
237 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
238 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
239 .allow_runtime_pm = true,
240 .probe_slot = mfd_sdio_probe_slot,
241 };
242
243 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
245 .allow_runtime_pm = true,
246 .probe_slot = mfd_emmc_probe_slot,
247 };
248
249 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
250 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
251 .probe_slot = pch_hc_probe_slot,
252 };
253
sdhci_pci_int_hw_reset(struct sdhci_host * host)254 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
255 {
256 u8 reg;
257
258 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
259 reg |= 0x10;
260 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
261 /* For eMMC, minimum is 1us but give it 9us for good measure */
262 udelay(9);
263 reg &= ~0x10;
264 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
265 /* For eMMC, minimum is 200us but give it 300us for good measure */
266 usleep_range(300, 1000);
267 }
268
byt_emmc_probe_slot(struct sdhci_pci_slot * slot)269 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
270 {
271 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
272 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
273 MMC_CAP_BUS_WIDTH_TEST |
274 MMC_CAP_WAIT_WHILE_BUSY;
275 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
276 slot->hw_reset = sdhci_pci_int_hw_reset;
277 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
278 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
279 return 0;
280 }
281
byt_sdio_probe_slot(struct sdhci_pci_slot * slot)282 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
283 {
284 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
285 MMC_CAP_BUS_WIDTH_TEST |
286 MMC_CAP_WAIT_WHILE_BUSY;
287 return 0;
288 }
289
byt_sd_probe_slot(struct sdhci_pci_slot * slot)290 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
291 {
292 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
293 MMC_CAP_WAIT_WHILE_BUSY;
294 slot->cd_con_id = NULL;
295 slot->cd_idx = 0;
296 slot->cd_override_level = true;
297 return 0;
298 }
299
300 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
301 .allow_runtime_pm = true,
302 .probe_slot = byt_emmc_probe_slot,
303 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
304 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
305 SDHCI_QUIRK2_STOP_WITH_TC,
306 };
307
308 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
309 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
310 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
311 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
312 .allow_runtime_pm = true,
313 .probe_slot = byt_sdio_probe_slot,
314 };
315
316 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
317 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
318 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
319 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
320 SDHCI_QUIRK2_STOP_WITH_TC,
321 .allow_runtime_pm = true,
322 .own_cd_for_runtime_pm = true,
323 .probe_slot = byt_sd_probe_slot,
324 };
325
326 /* Define Host controllers for Intel Merrifield platform */
327 #define INTEL_MRFL_EMMC_0 0
328 #define INTEL_MRFL_EMMC_1 1
329
intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot * slot)330 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
331 {
332 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
333 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
334 /* SD support is not ready yet */
335 return -ENODEV;
336
337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
338 MMC_CAP_1_8V_DDR;
339
340 return 0;
341 }
342
343 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
344 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
345 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
346 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
347 .allow_runtime_pm = true,
348 .probe_slot = intel_mrfl_mmc_probe_slot,
349 };
350
351 /* O2Micro extra registers */
352 #define O2_SD_LOCK_WP 0xD3
353 #define O2_SD_MULTI_VCC3V 0xEE
354 #define O2_SD_CLKREQ 0xEC
355 #define O2_SD_CAPS 0xE0
356 #define O2_SD_ADMA1 0xE2
357 #define O2_SD_ADMA2 0xE7
358 #define O2_SD_INF_MOD 0xF1
359
jmicron_pmos(struct sdhci_pci_chip * chip,int on)360 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
361 {
362 u8 scratch;
363 int ret;
364
365 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
366 if (ret)
367 return ret;
368
369 /*
370 * Turn PMOS on [bit 0], set over current detection to 2.4 V
371 * [bit 1:2] and enable over current debouncing [bit 6].
372 */
373 if (on)
374 scratch |= 0x47;
375 else
376 scratch &= ~0x47;
377
378 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
379 if (ret)
380 return ret;
381
382 return 0;
383 }
384
jmicron_probe(struct sdhci_pci_chip * chip)385 static int jmicron_probe(struct sdhci_pci_chip *chip)
386 {
387 int ret;
388 u16 mmcdev = 0;
389
390 if (chip->pdev->revision == 0) {
391 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
392 SDHCI_QUIRK_32BIT_DMA_SIZE |
393 SDHCI_QUIRK_32BIT_ADMA_SIZE |
394 SDHCI_QUIRK_RESET_AFTER_REQUEST |
395 SDHCI_QUIRK_BROKEN_SMALL_PIO;
396 }
397
398 /*
399 * JMicron chips can have two interfaces to the same hardware
400 * in order to work around limitations in Microsoft's driver.
401 * We need to make sure we only bind to one of them.
402 *
403 * This code assumes two things:
404 *
405 * 1. The PCI code adds subfunctions in order.
406 *
407 * 2. The MMC interface has a lower subfunction number
408 * than the SD interface.
409 */
410 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
411 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
412 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
413 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
414
415 if (mmcdev) {
416 struct pci_dev *sd_dev;
417
418 sd_dev = NULL;
419 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
420 mmcdev, sd_dev)) != NULL) {
421 if ((PCI_SLOT(chip->pdev->devfn) ==
422 PCI_SLOT(sd_dev->devfn)) &&
423 (chip->pdev->bus == sd_dev->bus))
424 break;
425 }
426
427 if (sd_dev) {
428 pci_dev_put(sd_dev);
429 dev_info(&chip->pdev->dev, "Refusing to bind to "
430 "secondary interface.\n");
431 return -ENODEV;
432 }
433 }
434
435 /*
436 * JMicron chips need a bit of a nudge to enable the power
437 * output pins.
438 */
439 ret = jmicron_pmos(chip, 1);
440 if (ret) {
441 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
442 return ret;
443 }
444
445 /* quirk for unsable RO-detection on JM388 chips */
446 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
447 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
448 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
449
450 return 0;
451 }
452
jmicron_enable_mmc(struct sdhci_host * host,int on)453 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
454 {
455 u8 scratch;
456
457 scratch = readb(host->ioaddr + 0xC0);
458
459 if (on)
460 scratch |= 0x01;
461 else
462 scratch &= ~0x01;
463
464 writeb(scratch, host->ioaddr + 0xC0);
465 }
466
jmicron_probe_slot(struct sdhci_pci_slot * slot)467 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
468 {
469 if (slot->chip->pdev->revision == 0) {
470 u16 version;
471
472 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
473 version = (version & SDHCI_VENDOR_VER_MASK) >>
474 SDHCI_VENDOR_VER_SHIFT;
475
476 /*
477 * Older versions of the chip have lots of nasty glitches
478 * in the ADMA engine. It's best just to avoid it
479 * completely.
480 */
481 if (version < 0xAC)
482 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
483 }
484
485 /* JM388 MMC doesn't support 1.8V while SD supports it */
486 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
487 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
488 MMC_VDD_29_30 | MMC_VDD_30_31 |
489 MMC_VDD_165_195; /* allow 1.8V */
490 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
491 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
492 }
493
494 /*
495 * The secondary interface requires a bit set to get the
496 * interrupts.
497 */
498 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
499 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
500 jmicron_enable_mmc(slot->host, 1);
501
502 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
503
504 return 0;
505 }
506
jmicron_remove_slot(struct sdhci_pci_slot * slot,int dead)507 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
508 {
509 if (dead)
510 return;
511
512 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
514 jmicron_enable_mmc(slot->host, 0);
515 }
516
jmicron_suspend(struct sdhci_pci_chip * chip)517 static int jmicron_suspend(struct sdhci_pci_chip *chip)
518 {
519 int i;
520
521 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
522 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
523 for (i = 0; i < chip->num_slots; i++)
524 jmicron_enable_mmc(chip->slots[i]->host, 0);
525 }
526
527 return 0;
528 }
529
jmicron_resume(struct sdhci_pci_chip * chip)530 static int jmicron_resume(struct sdhci_pci_chip *chip)
531 {
532 int ret, i;
533
534 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
535 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
536 for (i = 0; i < chip->num_slots; i++)
537 jmicron_enable_mmc(chip->slots[i]->host, 1);
538 }
539
540 ret = jmicron_pmos(chip, 1);
541 if (ret) {
542 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
543 return ret;
544 }
545
546 return 0;
547 }
548
549 static const struct sdhci_pci_fixes sdhci_o2 = {
550 .probe = sdhci_pci_o2_probe,
551 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
552 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
553 .probe_slot = sdhci_pci_o2_probe_slot,
554 .resume = sdhci_pci_o2_resume,
555 };
556
557 static const struct sdhci_pci_fixes sdhci_jmicron = {
558 .probe = jmicron_probe,
559
560 .probe_slot = jmicron_probe_slot,
561 .remove_slot = jmicron_remove_slot,
562
563 .suspend = jmicron_suspend,
564 .resume = jmicron_resume,
565 };
566
567 /* SysKonnect CardBus2SDIO extra registers */
568 #define SYSKT_CTRL 0x200
569 #define SYSKT_RDFIFO_STAT 0x204
570 #define SYSKT_WRFIFO_STAT 0x208
571 #define SYSKT_POWER_DATA 0x20c
572 #define SYSKT_POWER_330 0xef
573 #define SYSKT_POWER_300 0xf8
574 #define SYSKT_POWER_184 0xcc
575 #define SYSKT_POWER_CMD 0x20d
576 #define SYSKT_POWER_START (1 << 7)
577 #define SYSKT_POWER_STATUS 0x20e
578 #define SYSKT_POWER_STATUS_OK (1 << 0)
579 #define SYSKT_BOARD_REV 0x210
580 #define SYSKT_CHIP_REV 0x211
581 #define SYSKT_CONF_DATA 0x212
582 #define SYSKT_CONF_DATA_1V8 (1 << 2)
583 #define SYSKT_CONF_DATA_2V5 (1 << 1)
584 #define SYSKT_CONF_DATA_3V3 (1 << 0)
585
syskt_probe(struct sdhci_pci_chip * chip)586 static int syskt_probe(struct sdhci_pci_chip *chip)
587 {
588 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
589 chip->pdev->class &= ~0x0000FF;
590 chip->pdev->class |= PCI_SDHCI_IFDMA;
591 }
592 return 0;
593 }
594
syskt_probe_slot(struct sdhci_pci_slot * slot)595 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
596 {
597 int tm, ps;
598
599 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
600 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
601 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
602 "board rev %d.%d, chip rev %d.%d\n",
603 board_rev >> 4, board_rev & 0xf,
604 chip_rev >> 4, chip_rev & 0xf);
605 if (chip_rev >= 0x20)
606 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
607
608 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
609 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
610 udelay(50);
611 tm = 10; /* Wait max 1 ms */
612 do {
613 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
614 if (ps & SYSKT_POWER_STATUS_OK)
615 break;
616 udelay(100);
617 } while (--tm);
618 if (!tm) {
619 dev_err(&slot->chip->pdev->dev,
620 "power regulator never stabilized");
621 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
622 return -ENODEV;
623 }
624
625 return 0;
626 }
627
628 static const struct sdhci_pci_fixes sdhci_syskt = {
629 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
630 .probe = syskt_probe,
631 .probe_slot = syskt_probe_slot,
632 };
633
via_probe(struct sdhci_pci_chip * chip)634 static int via_probe(struct sdhci_pci_chip *chip)
635 {
636 if (chip->pdev->revision == 0x10)
637 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
638
639 return 0;
640 }
641
642 static const struct sdhci_pci_fixes sdhci_via = {
643 .probe = via_probe,
644 };
645
rtsx_probe_slot(struct sdhci_pci_slot * slot)646 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
647 {
648 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
649 return 0;
650 }
651
652 static const struct sdhci_pci_fixes sdhci_rtsx = {
653 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
654 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
655 SDHCI_QUIRK2_BROKEN_DDR50,
656 .probe_slot = rtsx_probe_slot,
657 };
658
amd_probe(struct sdhci_pci_chip * chip)659 static int amd_probe(struct sdhci_pci_chip *chip)
660 {
661 struct pci_dev *smbus_dev;
662
663 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
664 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
665
666 if (smbus_dev && (smbus_dev->revision < 0x51)) {
667 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
668 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
669 }
670
671 return 0;
672 }
673
674 static const struct sdhci_pci_fixes sdhci_amd = {
675 .probe = amd_probe,
676 };
677
678 static const struct pci_device_id pci_ids[] = {
679 {
680 .vendor = PCI_VENDOR_ID_RICOH,
681 .device = PCI_DEVICE_ID_RICOH_R5C822,
682 .subvendor = PCI_ANY_ID,
683 .subdevice = PCI_ANY_ID,
684 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
685 },
686
687 {
688 .vendor = PCI_VENDOR_ID_RICOH,
689 .device = 0x843,
690 .subvendor = PCI_ANY_ID,
691 .subdevice = PCI_ANY_ID,
692 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
693 },
694
695 {
696 .vendor = PCI_VENDOR_ID_RICOH,
697 .device = 0xe822,
698 .subvendor = PCI_ANY_ID,
699 .subdevice = PCI_ANY_ID,
700 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
701 },
702
703 {
704 .vendor = PCI_VENDOR_ID_RICOH,
705 .device = 0xe823,
706 .subvendor = PCI_ANY_ID,
707 .subdevice = PCI_ANY_ID,
708 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
709 },
710
711 {
712 .vendor = PCI_VENDOR_ID_ENE,
713 .device = PCI_DEVICE_ID_ENE_CB712_SD,
714 .subvendor = PCI_ANY_ID,
715 .subdevice = PCI_ANY_ID,
716 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
717 },
718
719 {
720 .vendor = PCI_VENDOR_ID_ENE,
721 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
722 .subvendor = PCI_ANY_ID,
723 .subdevice = PCI_ANY_ID,
724 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
725 },
726
727 {
728 .vendor = PCI_VENDOR_ID_ENE,
729 .device = PCI_DEVICE_ID_ENE_CB714_SD,
730 .subvendor = PCI_ANY_ID,
731 .subdevice = PCI_ANY_ID,
732 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
733 },
734
735 {
736 .vendor = PCI_VENDOR_ID_ENE,
737 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
738 .subvendor = PCI_ANY_ID,
739 .subdevice = PCI_ANY_ID,
740 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
741 },
742
743 {
744 .vendor = PCI_VENDOR_ID_MARVELL,
745 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
746 .subvendor = PCI_ANY_ID,
747 .subdevice = PCI_ANY_ID,
748 .driver_data = (kernel_ulong_t)&sdhci_cafe,
749 },
750
751 {
752 .vendor = PCI_VENDOR_ID_JMICRON,
753 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
754 .subvendor = PCI_ANY_ID,
755 .subdevice = PCI_ANY_ID,
756 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
757 },
758
759 {
760 .vendor = PCI_VENDOR_ID_JMICRON,
761 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
762 .subvendor = PCI_ANY_ID,
763 .subdevice = PCI_ANY_ID,
764 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
765 },
766
767 {
768 .vendor = PCI_VENDOR_ID_JMICRON,
769 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
770 .subvendor = PCI_ANY_ID,
771 .subdevice = PCI_ANY_ID,
772 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
773 },
774
775 {
776 .vendor = PCI_VENDOR_ID_JMICRON,
777 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
778 .subvendor = PCI_ANY_ID,
779 .subdevice = PCI_ANY_ID,
780 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
781 },
782
783 {
784 .vendor = PCI_VENDOR_ID_SYSKONNECT,
785 .device = 0x8000,
786 .subvendor = PCI_ANY_ID,
787 .subdevice = PCI_ANY_ID,
788 .driver_data = (kernel_ulong_t)&sdhci_syskt,
789 },
790
791 {
792 .vendor = PCI_VENDOR_ID_VIA,
793 .device = 0x95d0,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .driver_data = (kernel_ulong_t)&sdhci_via,
797 },
798
799 {
800 .vendor = PCI_VENDOR_ID_REALTEK,
801 .device = 0x5250,
802 .subvendor = PCI_ANY_ID,
803 .subdevice = PCI_ANY_ID,
804 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
805 },
806
807 {
808 .vendor = PCI_VENDOR_ID_INTEL,
809 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
810 .subvendor = PCI_ANY_ID,
811 .subdevice = PCI_ANY_ID,
812 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
813 },
814
815 {
816 .vendor = PCI_VENDOR_ID_INTEL,
817 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
818 .subvendor = PCI_ANY_ID,
819 .subdevice = PCI_ANY_ID,
820 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
821 },
822
823 {
824 .vendor = PCI_VENDOR_ID_INTEL,
825 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
826 .subvendor = PCI_ANY_ID,
827 .subdevice = PCI_ANY_ID,
828 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
829 },
830
831 {
832 .vendor = PCI_VENDOR_ID_INTEL,
833 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
834 .subvendor = PCI_ANY_ID,
835 .subdevice = PCI_ANY_ID,
836 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
837 },
838
839 {
840 .vendor = PCI_VENDOR_ID_INTEL,
841 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
842 .subvendor = PCI_ANY_ID,
843 .subdevice = PCI_ANY_ID,
844 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
845 },
846
847 {
848 .vendor = PCI_VENDOR_ID_INTEL,
849 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
850 .subvendor = PCI_ANY_ID,
851 .subdevice = PCI_ANY_ID,
852 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
853 },
854
855 {
856 .vendor = PCI_VENDOR_ID_INTEL,
857 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
858 .subvendor = PCI_ANY_ID,
859 .subdevice = PCI_ANY_ID,
860 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
861 },
862
863 {
864 .vendor = PCI_VENDOR_ID_INTEL,
865 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
866 .subvendor = PCI_ANY_ID,
867 .subdevice = PCI_ANY_ID,
868 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
869 },
870
871 {
872 .vendor = PCI_VENDOR_ID_INTEL,
873 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
874 .subvendor = PCI_ANY_ID,
875 .subdevice = PCI_ANY_ID,
876 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
877 },
878
879 {
880 .vendor = PCI_VENDOR_ID_INTEL,
881 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
882 .subvendor = PCI_ANY_ID,
883 .subdevice = PCI_ANY_ID,
884 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
885 },
886
887 {
888 .vendor = PCI_VENDOR_ID_INTEL,
889 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
890 .subvendor = PCI_ANY_ID,
891 .subdevice = PCI_ANY_ID,
892 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
893 },
894
895 {
896 .vendor = PCI_VENDOR_ID_INTEL,
897 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
898 .subvendor = PCI_ANY_ID,
899 .subdevice = PCI_ANY_ID,
900 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
901 },
902
903 {
904 .vendor = PCI_VENDOR_ID_INTEL,
905 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
906 .subvendor = PCI_ANY_ID,
907 .subdevice = PCI_ANY_ID,
908 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
909 },
910
911 {
912 .vendor = PCI_VENDOR_ID_INTEL,
913 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
914 .subvendor = PCI_ANY_ID,
915 .subdevice = PCI_ANY_ID,
916 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
917 },
918
919 {
920 .vendor = PCI_VENDOR_ID_INTEL,
921 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
922 .subvendor = PCI_ANY_ID,
923 .subdevice = PCI_ANY_ID,
924 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
925 },
926
927 {
928 .vendor = PCI_VENDOR_ID_INTEL,
929 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
930 .subvendor = PCI_ANY_ID,
931 .subdevice = PCI_ANY_ID,
932 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
933 },
934
935 {
936 .vendor = PCI_VENDOR_ID_INTEL,
937 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
938 .subvendor = PCI_ANY_ID,
939 .subdevice = PCI_ANY_ID,
940 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
941 },
942
943 {
944 .vendor = PCI_VENDOR_ID_INTEL,
945 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
946 .subvendor = PCI_ANY_ID,
947 .subdevice = PCI_ANY_ID,
948 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
949 },
950
951 {
952 .vendor = PCI_VENDOR_ID_INTEL,
953 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
957 },
958
959 {
960 .vendor = PCI_VENDOR_ID_INTEL,
961 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
965 },
966
967 {
968 .vendor = PCI_VENDOR_ID_INTEL,
969 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
970 .subvendor = PCI_ANY_ID,
971 .subdevice = PCI_ANY_ID,
972 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
973 },
974
975 {
976 .vendor = PCI_VENDOR_ID_INTEL,
977 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
978 .subvendor = PCI_ANY_ID,
979 .subdevice = PCI_ANY_ID,
980 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
981 },
982
983 {
984 .vendor = PCI_VENDOR_ID_INTEL,
985 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
986 .subvendor = PCI_ANY_ID,
987 .subdevice = PCI_ANY_ID,
988 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
989 },
990
991 {
992 .vendor = PCI_VENDOR_ID_INTEL,
993 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
997 },
998
999 {
1000 .vendor = PCI_VENDOR_ID_INTEL,
1001 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1002 .subvendor = PCI_ANY_ID,
1003 .subdevice = PCI_ANY_ID,
1004 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1005 },
1006
1007 {
1008 .vendor = PCI_VENDOR_ID_INTEL,
1009 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1010 .subvendor = PCI_ANY_ID,
1011 .subdevice = PCI_ANY_ID,
1012 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1013 },
1014
1015 {
1016 .vendor = PCI_VENDOR_ID_INTEL,
1017 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1018 .subvendor = PCI_ANY_ID,
1019 .subdevice = PCI_ANY_ID,
1020 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1021 },
1022
1023 {
1024 .vendor = PCI_VENDOR_ID_O2,
1025 .device = PCI_DEVICE_ID_O2_8120,
1026 .subvendor = PCI_ANY_ID,
1027 .subdevice = PCI_ANY_ID,
1028 .driver_data = (kernel_ulong_t)&sdhci_o2,
1029 },
1030
1031 {
1032 .vendor = PCI_VENDOR_ID_O2,
1033 .device = PCI_DEVICE_ID_O2_8220,
1034 .subvendor = PCI_ANY_ID,
1035 .subdevice = PCI_ANY_ID,
1036 .driver_data = (kernel_ulong_t)&sdhci_o2,
1037 },
1038
1039 {
1040 .vendor = PCI_VENDOR_ID_O2,
1041 .device = PCI_DEVICE_ID_O2_8221,
1042 .subvendor = PCI_ANY_ID,
1043 .subdevice = PCI_ANY_ID,
1044 .driver_data = (kernel_ulong_t)&sdhci_o2,
1045 },
1046
1047 {
1048 .vendor = PCI_VENDOR_ID_O2,
1049 .device = PCI_DEVICE_ID_O2_8320,
1050 .subvendor = PCI_ANY_ID,
1051 .subdevice = PCI_ANY_ID,
1052 .driver_data = (kernel_ulong_t)&sdhci_o2,
1053 },
1054
1055 {
1056 .vendor = PCI_VENDOR_ID_O2,
1057 .device = PCI_DEVICE_ID_O2_8321,
1058 .subvendor = PCI_ANY_ID,
1059 .subdevice = PCI_ANY_ID,
1060 .driver_data = (kernel_ulong_t)&sdhci_o2,
1061 },
1062
1063 {
1064 .vendor = PCI_VENDOR_ID_O2,
1065 .device = PCI_DEVICE_ID_O2_FUJIN2,
1066 .subvendor = PCI_ANY_ID,
1067 .subdevice = PCI_ANY_ID,
1068 .driver_data = (kernel_ulong_t)&sdhci_o2,
1069 },
1070
1071 {
1072 .vendor = PCI_VENDOR_ID_O2,
1073 .device = PCI_DEVICE_ID_O2_SDS0,
1074 .subvendor = PCI_ANY_ID,
1075 .subdevice = PCI_ANY_ID,
1076 .driver_data = (kernel_ulong_t)&sdhci_o2,
1077 },
1078
1079 {
1080 .vendor = PCI_VENDOR_ID_O2,
1081 .device = PCI_DEVICE_ID_O2_SDS1,
1082 .subvendor = PCI_ANY_ID,
1083 .subdevice = PCI_ANY_ID,
1084 .driver_data = (kernel_ulong_t)&sdhci_o2,
1085 },
1086
1087 {
1088 .vendor = PCI_VENDOR_ID_O2,
1089 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1090 .subvendor = PCI_ANY_ID,
1091 .subdevice = PCI_ANY_ID,
1092 .driver_data = (kernel_ulong_t)&sdhci_o2,
1093 },
1094
1095 {
1096 .vendor = PCI_VENDOR_ID_O2,
1097 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .driver_data = (kernel_ulong_t)&sdhci_o2,
1101 },
1102 {
1103 .vendor = PCI_VENDOR_ID_AMD,
1104 .device = PCI_ANY_ID,
1105 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1106 .class_mask = 0xFFFF00,
1107 .subvendor = PCI_ANY_ID,
1108 .subdevice = PCI_ANY_ID,
1109 .driver_data = (kernel_ulong_t)&sdhci_amd,
1110 },
1111 { /* Generic SD host controller */
1112 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1113 },
1114
1115 { /* end: all zeroes */ },
1116 };
1117
1118 MODULE_DEVICE_TABLE(pci, pci_ids);
1119
1120 /*****************************************************************************\
1121 * *
1122 * SDHCI core callbacks *
1123 * *
1124 \*****************************************************************************/
1125
sdhci_pci_enable_dma(struct sdhci_host * host)1126 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1127 {
1128 struct sdhci_pci_slot *slot;
1129 struct pci_dev *pdev;
1130 int ret = -1;
1131
1132 slot = sdhci_priv(host);
1133 pdev = slot->chip->pdev;
1134
1135 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1136 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1137 (host->flags & SDHCI_USE_SDMA)) {
1138 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1139 "doesn't fully claim to support it.\n");
1140 }
1141
1142 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1143 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1144 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1145 } else {
1146 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1147 if (ret)
1148 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1149 }
1150 }
1151 if (ret)
1152 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1153 if (ret)
1154 return ret;
1155
1156 pci_set_master(pdev);
1157
1158 return 0;
1159 }
1160
sdhci_pci_set_bus_width(struct sdhci_host * host,int width)1161 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1162 {
1163 u8 ctrl;
1164
1165 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1166
1167 switch (width) {
1168 case MMC_BUS_WIDTH_8:
1169 ctrl |= SDHCI_CTRL_8BITBUS;
1170 ctrl &= ~SDHCI_CTRL_4BITBUS;
1171 break;
1172 case MMC_BUS_WIDTH_4:
1173 ctrl |= SDHCI_CTRL_4BITBUS;
1174 ctrl &= ~SDHCI_CTRL_8BITBUS;
1175 break;
1176 default:
1177 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1178 break;
1179 }
1180
1181 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1182 }
1183
sdhci_pci_gpio_hw_reset(struct sdhci_host * host)1184 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1185 {
1186 struct sdhci_pci_slot *slot = sdhci_priv(host);
1187 int rst_n_gpio = slot->rst_n_gpio;
1188
1189 if (!gpio_is_valid(rst_n_gpio))
1190 return;
1191 gpio_set_value_cansleep(rst_n_gpio, 0);
1192 /* For eMMC, minimum is 1us but give it 10us for good measure */
1193 udelay(10);
1194 gpio_set_value_cansleep(rst_n_gpio, 1);
1195 /* For eMMC, minimum is 200us but give it 300us for good measure */
1196 usleep_range(300, 1000);
1197 }
1198
sdhci_pci_hw_reset(struct sdhci_host * host)1199 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1200 {
1201 struct sdhci_pci_slot *slot = sdhci_priv(host);
1202
1203 if (slot->hw_reset)
1204 slot->hw_reset(host);
1205 }
1206
1207 static const struct sdhci_ops sdhci_pci_ops = {
1208 .set_clock = sdhci_set_clock,
1209 .enable_dma = sdhci_pci_enable_dma,
1210 .set_bus_width = sdhci_pci_set_bus_width,
1211 .reset = sdhci_reset,
1212 .set_uhs_signaling = sdhci_set_uhs_signaling,
1213 .hw_reset = sdhci_pci_hw_reset,
1214 };
1215
1216 /*****************************************************************************\
1217 * *
1218 * Suspend/resume *
1219 * *
1220 \*****************************************************************************/
1221
1222 #ifdef CONFIG_PM
1223
sdhci_pci_suspend(struct device * dev)1224 static int sdhci_pci_suspend(struct device *dev)
1225 {
1226 struct pci_dev *pdev = to_pci_dev(dev);
1227 struct sdhci_pci_chip *chip;
1228 struct sdhci_pci_slot *slot;
1229 mmc_pm_flag_t slot_pm_flags;
1230 mmc_pm_flag_t pm_flags = 0;
1231 int i, ret;
1232
1233 chip = pci_get_drvdata(pdev);
1234 if (!chip)
1235 return 0;
1236
1237 for (i = 0; i < chip->num_slots; i++) {
1238 slot = chip->slots[i];
1239 if (!slot)
1240 continue;
1241
1242 ret = sdhci_suspend_host(slot->host);
1243
1244 if (ret)
1245 goto err_pci_suspend;
1246
1247 slot_pm_flags = slot->host->mmc->pm_flags;
1248 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1249 sdhci_enable_irq_wakeups(slot->host);
1250
1251 pm_flags |= slot_pm_flags;
1252 }
1253
1254 if (chip->fixes && chip->fixes->suspend) {
1255 ret = chip->fixes->suspend(chip);
1256 if (ret)
1257 goto err_pci_suspend;
1258 }
1259
1260 if (pm_flags & MMC_PM_KEEP_POWER) {
1261 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1262 device_init_wakeup(dev, true);
1263 else
1264 device_init_wakeup(dev, false);
1265 } else
1266 device_init_wakeup(dev, false);
1267
1268 return 0;
1269
1270 err_pci_suspend:
1271 while (--i >= 0)
1272 sdhci_resume_host(chip->slots[i]->host);
1273 return ret;
1274 }
1275
sdhci_pci_resume(struct device * dev)1276 static int sdhci_pci_resume(struct device *dev)
1277 {
1278 struct pci_dev *pdev = to_pci_dev(dev);
1279 struct sdhci_pci_chip *chip;
1280 struct sdhci_pci_slot *slot;
1281 int i, ret;
1282
1283 chip = pci_get_drvdata(pdev);
1284 if (!chip)
1285 return 0;
1286
1287 if (chip->fixes && chip->fixes->resume) {
1288 ret = chip->fixes->resume(chip);
1289 if (ret)
1290 return ret;
1291 }
1292
1293 for (i = 0; i < chip->num_slots; i++) {
1294 slot = chip->slots[i];
1295 if (!slot)
1296 continue;
1297
1298 ret = sdhci_resume_host(slot->host);
1299 if (ret)
1300 return ret;
1301 }
1302
1303 return 0;
1304 }
1305
sdhci_pci_runtime_suspend(struct device * dev)1306 static int sdhci_pci_runtime_suspend(struct device *dev)
1307 {
1308 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1309 struct sdhci_pci_chip *chip;
1310 struct sdhci_pci_slot *slot;
1311 int i, ret;
1312
1313 chip = pci_get_drvdata(pdev);
1314 if (!chip)
1315 return 0;
1316
1317 for (i = 0; i < chip->num_slots; i++) {
1318 slot = chip->slots[i];
1319 if (!slot)
1320 continue;
1321
1322 ret = sdhci_runtime_suspend_host(slot->host);
1323
1324 if (ret)
1325 goto err_pci_runtime_suspend;
1326 }
1327
1328 if (chip->fixes && chip->fixes->suspend) {
1329 ret = chip->fixes->suspend(chip);
1330 if (ret)
1331 goto err_pci_runtime_suspend;
1332 }
1333
1334 return 0;
1335
1336 err_pci_runtime_suspend:
1337 while (--i >= 0)
1338 sdhci_runtime_resume_host(chip->slots[i]->host);
1339 return ret;
1340 }
1341
sdhci_pci_runtime_resume(struct device * dev)1342 static int sdhci_pci_runtime_resume(struct device *dev)
1343 {
1344 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1345 struct sdhci_pci_chip *chip;
1346 struct sdhci_pci_slot *slot;
1347 int i, ret;
1348
1349 chip = pci_get_drvdata(pdev);
1350 if (!chip)
1351 return 0;
1352
1353 if (chip->fixes && chip->fixes->resume) {
1354 ret = chip->fixes->resume(chip);
1355 if (ret)
1356 return ret;
1357 }
1358
1359 for (i = 0; i < chip->num_slots; i++) {
1360 slot = chip->slots[i];
1361 if (!slot)
1362 continue;
1363
1364 ret = sdhci_runtime_resume_host(slot->host);
1365 if (ret)
1366 return ret;
1367 }
1368
1369 return 0;
1370 }
1371
1372 #else /* CONFIG_PM */
1373
1374 #define sdhci_pci_suspend NULL
1375 #define sdhci_pci_resume NULL
1376
1377 #endif /* CONFIG_PM */
1378
1379 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1380 .suspend = sdhci_pci_suspend,
1381 .resume = sdhci_pci_resume,
1382 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1383 sdhci_pci_runtime_resume, NULL)
1384 };
1385
1386 /*****************************************************************************\
1387 * *
1388 * Device probing/removal *
1389 * *
1390 \*****************************************************************************/
1391
sdhci_pci_probe_slot(struct pci_dev * pdev,struct sdhci_pci_chip * chip,int first_bar,int slotno)1392 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1393 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1394 int slotno)
1395 {
1396 struct sdhci_pci_slot *slot;
1397 struct sdhci_host *host;
1398 int ret, bar = first_bar + slotno;
1399
1400 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1401 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1402 return ERR_PTR(-ENODEV);
1403 }
1404
1405 if (pci_resource_len(pdev, bar) < 0x100) {
1406 dev_err(&pdev->dev, "Invalid iomem size. You may "
1407 "experience problems.\n");
1408 }
1409
1410 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1411 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1412 return ERR_PTR(-ENODEV);
1413 }
1414
1415 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1416 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1417 return ERR_PTR(-ENODEV);
1418 }
1419
1420 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1421 if (IS_ERR(host)) {
1422 dev_err(&pdev->dev, "cannot allocate host\n");
1423 return ERR_CAST(host);
1424 }
1425
1426 slot = sdhci_priv(host);
1427
1428 slot->chip = chip;
1429 slot->host = host;
1430 slot->pci_bar = bar;
1431 slot->rst_n_gpio = -EINVAL;
1432 slot->cd_gpio = -EINVAL;
1433 slot->cd_idx = -1;
1434
1435 /* Retrieve platform data if there is any */
1436 if (*sdhci_pci_get_data)
1437 slot->data = sdhci_pci_get_data(pdev, slotno);
1438
1439 if (slot->data) {
1440 if (slot->data->setup) {
1441 ret = slot->data->setup(slot->data);
1442 if (ret) {
1443 dev_err(&pdev->dev, "platform setup failed\n");
1444 goto free;
1445 }
1446 }
1447 slot->rst_n_gpio = slot->data->rst_n_gpio;
1448 slot->cd_gpio = slot->data->cd_gpio;
1449 }
1450
1451 host->hw_name = "PCI";
1452 host->ops = &sdhci_pci_ops;
1453 host->quirks = chip->quirks;
1454 host->quirks2 = chip->quirks2;
1455
1456 host->irq = pdev->irq;
1457
1458 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1459 if (ret) {
1460 dev_err(&pdev->dev, "cannot request region\n");
1461 goto cleanup;
1462 }
1463
1464 host->ioaddr = pci_ioremap_bar(pdev, bar);
1465 if (!host->ioaddr) {
1466 dev_err(&pdev->dev, "failed to remap registers\n");
1467 ret = -ENOMEM;
1468 goto release;
1469 }
1470
1471 if (chip->fixes && chip->fixes->probe_slot) {
1472 ret = chip->fixes->probe_slot(slot);
1473 if (ret)
1474 goto unmap;
1475 }
1476
1477 if (gpio_is_valid(slot->rst_n_gpio)) {
1478 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1479 gpio_direction_output(slot->rst_n_gpio, 1);
1480 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1481 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1482 } else {
1483 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1484 slot->rst_n_gpio = -EINVAL;
1485 }
1486 }
1487
1488 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1489 host->mmc->slotno = slotno;
1490 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1491
1492 if (slot->cd_idx >= 0 &&
1493 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1494 slot->cd_override_level, 0, NULL)) {
1495 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1496 slot->cd_idx = -1;
1497 }
1498
1499 ret = sdhci_add_host(host);
1500 if (ret)
1501 goto remove;
1502
1503 sdhci_pci_add_own_cd(slot);
1504
1505 /*
1506 * Check if the chip needs a separate GPIO for card detect to wake up
1507 * from runtime suspend. If it is not there, don't allow runtime PM.
1508 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1509 */
1510 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1511 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1512 chip->allow_runtime_pm = false;
1513
1514 return slot;
1515
1516 remove:
1517 if (gpio_is_valid(slot->rst_n_gpio))
1518 gpio_free(slot->rst_n_gpio);
1519
1520 if (chip->fixes && chip->fixes->remove_slot)
1521 chip->fixes->remove_slot(slot, 0);
1522
1523 unmap:
1524 iounmap(host->ioaddr);
1525
1526 release:
1527 pci_release_region(pdev, bar);
1528
1529 cleanup:
1530 if (slot->data && slot->data->cleanup)
1531 slot->data->cleanup(slot->data);
1532
1533 free:
1534 sdhci_free_host(host);
1535
1536 return ERR_PTR(ret);
1537 }
1538
sdhci_pci_remove_slot(struct sdhci_pci_slot * slot)1539 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1540 {
1541 int dead;
1542 u32 scratch;
1543
1544 sdhci_pci_remove_own_cd(slot);
1545
1546 dead = 0;
1547 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1548 if (scratch == (u32)-1)
1549 dead = 1;
1550
1551 sdhci_remove_host(slot->host, dead);
1552
1553 if (gpio_is_valid(slot->rst_n_gpio))
1554 gpio_free(slot->rst_n_gpio);
1555
1556 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1557 slot->chip->fixes->remove_slot(slot, dead);
1558
1559 if (slot->data && slot->data->cleanup)
1560 slot->data->cleanup(slot->data);
1561
1562 pci_release_region(slot->chip->pdev, slot->pci_bar);
1563
1564 sdhci_free_host(slot->host);
1565 }
1566
sdhci_pci_runtime_pm_allow(struct device * dev)1567 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1568 {
1569 pm_runtime_put_noidle(dev);
1570 pm_runtime_allow(dev);
1571 pm_runtime_set_autosuspend_delay(dev, 50);
1572 pm_runtime_use_autosuspend(dev);
1573 pm_suspend_ignore_children(dev, 1);
1574 }
1575
sdhci_pci_runtime_pm_forbid(struct device * dev)1576 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1577 {
1578 pm_runtime_forbid(dev);
1579 pm_runtime_get_noresume(dev);
1580 }
1581
sdhci_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1582 static int sdhci_pci_probe(struct pci_dev *pdev,
1583 const struct pci_device_id *ent)
1584 {
1585 struct sdhci_pci_chip *chip;
1586 struct sdhci_pci_slot *slot;
1587
1588 u8 slots, first_bar;
1589 int ret, i;
1590
1591 BUG_ON(pdev == NULL);
1592 BUG_ON(ent == NULL);
1593
1594 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1595 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1596
1597 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1598 if (ret)
1599 return ret;
1600
1601 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1602 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1603 if (slots == 0)
1604 return -ENODEV;
1605
1606 BUG_ON(slots > MAX_SLOTS);
1607
1608 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1609 if (ret)
1610 return ret;
1611
1612 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1613
1614 if (first_bar > 5) {
1615 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1616 return -ENODEV;
1617 }
1618
1619 ret = pci_enable_device(pdev);
1620 if (ret)
1621 return ret;
1622
1623 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1624 if (!chip) {
1625 ret = -ENOMEM;
1626 goto err;
1627 }
1628
1629 chip->pdev = pdev;
1630 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1631 if (chip->fixes) {
1632 chip->quirks = chip->fixes->quirks;
1633 chip->quirks2 = chip->fixes->quirks2;
1634 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1635 }
1636 chip->num_slots = slots;
1637
1638 pci_set_drvdata(pdev, chip);
1639
1640 if (chip->fixes && chip->fixes->probe) {
1641 ret = chip->fixes->probe(chip);
1642 if (ret)
1643 goto free;
1644 }
1645
1646 slots = chip->num_slots; /* Quirk may have changed this */
1647
1648 for (i = 0; i < slots; i++) {
1649 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1650 if (IS_ERR(slot)) {
1651 for (i--; i >= 0; i--)
1652 sdhci_pci_remove_slot(chip->slots[i]);
1653 ret = PTR_ERR(slot);
1654 goto free;
1655 }
1656
1657 chip->slots[i] = slot;
1658 }
1659
1660 if (chip->allow_runtime_pm)
1661 sdhci_pci_runtime_pm_allow(&pdev->dev);
1662
1663 return 0;
1664
1665 free:
1666 pci_set_drvdata(pdev, NULL);
1667 kfree(chip);
1668
1669 err:
1670 pci_disable_device(pdev);
1671 return ret;
1672 }
1673
sdhci_pci_remove(struct pci_dev * pdev)1674 static void sdhci_pci_remove(struct pci_dev *pdev)
1675 {
1676 int i;
1677 struct sdhci_pci_chip *chip;
1678
1679 chip = pci_get_drvdata(pdev);
1680
1681 if (chip) {
1682 if (chip->allow_runtime_pm)
1683 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1684
1685 for (i = 0; i < chip->num_slots; i++)
1686 sdhci_pci_remove_slot(chip->slots[i]);
1687
1688 pci_set_drvdata(pdev, NULL);
1689 kfree(chip);
1690 }
1691
1692 pci_disable_device(pdev);
1693 }
1694
1695 static struct pci_driver sdhci_driver = {
1696 .name = "sdhci-pci",
1697 .id_table = pci_ids,
1698 .probe = sdhci_pci_probe,
1699 .remove = sdhci_pci_remove,
1700 .driver = {
1701 .pm = &sdhci_pci_pm_ops
1702 },
1703 };
1704
1705 module_pci_driver(sdhci_driver);
1706
1707 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1708 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1709 MODULE_LICENSE("GPL");
1710