1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "dport.h"
25 #include "outpdp.h"
26 #include "nv50.h"
27
28 #include <subdev/bios.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/i2c.h>
31
32 #include <nvif/class.h>
33
34 /******************************************************************************
35 * link training
36 *****************************************************************************/
37 struct dp_state {
38 struct nvkm_output_dp *outp;
39 int link_nr;
40 u32 link_bw;
41 u8 stat[6];
42 u8 conf[4];
43 bool pc2;
44 u8 pc2stat;
45 u8 pc2conf[2];
46 };
47
48 static int
dp_set_link_config(struct dp_state * dp)49 dp_set_link_config(struct dp_state *dp)
50 {
51 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
52 struct nvkm_output_dp *outp = dp->outp;
53 struct nvkm_disp *disp = nvkm_disp(outp);
54 struct nvkm_bios *bios = nvkm_bios(disp);
55 struct nvbios_init init = {
56 .subdev = nv_subdev(disp),
57 .bios = bios,
58 .offset = 0x0000,
59 .outp = &outp->base.info,
60 .crtc = -1,
61 .execute = 1,
62 };
63 u32 lnkcmp;
64 u8 sink[2];
65 int ret;
66
67 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
68
69 /* set desired link configuration on the source */
70 if ((lnkcmp = dp->outp->info.lnkcmp)) {
71 if (outp->version < 0x30) {
72 while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
73 lnkcmp += 4;
74 init.offset = nv_ro16(bios, lnkcmp + 2);
75 } else {
76 while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
77 lnkcmp += 3;
78 init.offset = nv_ro16(bios, lnkcmp + 1);
79 }
80
81 nvbios_exec(&init);
82 }
83
84 ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
85 outp->dpcd[DPCD_RC02] &
86 DPCD_RC02_ENHANCED_FRAME_CAP);
87 if (ret) {
88 if (ret < 0)
89 ERR("lnk_ctl failed with %d\n", ret);
90 return ret;
91 }
92
93 impl->lnk_pwr(outp, dp->link_nr);
94
95 /* set desired link configuration on the sink */
96 sink[0] = dp->link_bw / 27000;
97 sink[1] = dp->link_nr;
98 if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
99 sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
100
101 return nv_wraux(outp->base.edid, DPCD_LC00_LINK_BW_SET, sink, 2);
102 }
103
104 static void
dp_set_training_pattern(struct dp_state * dp,u8 pattern)105 dp_set_training_pattern(struct dp_state *dp, u8 pattern)
106 {
107 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
108 struct nvkm_output_dp *outp = dp->outp;
109 u8 sink_tp;
110
111 DBG("training pattern %d\n", pattern);
112 impl->pattern(outp, pattern);
113
114 nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
115 sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
116 sink_tp |= pattern;
117 nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
118 }
119
120 static int
dp_link_train_commit(struct dp_state * dp,bool pc)121 dp_link_train_commit(struct dp_state *dp, bool pc)
122 {
123 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
124 struct nvkm_output_dp *outp = dp->outp;
125 int ret, i;
126
127 for (i = 0; i < dp->link_nr; i++) {
128 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
129 u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3;
130 u8 lpre = (lane & 0x0c) >> 2;
131 u8 lvsw = (lane & 0x03) >> 0;
132 u8 hivs = 3 - lpre;
133 u8 hipe = 3;
134 u8 hipc = 3;
135
136 if (lpc2 >= hipc)
137 lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
138 if (lpre >= hipe) {
139 lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
140 lvsw = hivs = 3 - (lpre & 3);
141 } else
142 if (lvsw >= hivs) {
143 lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
144 }
145
146 dp->conf[i] = (lpre << 3) | lvsw;
147 dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
148
149 DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2);
150 impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3);
151 }
152
153 ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4);
154 if (ret)
155 return ret;
156
157 if (pc) {
158 ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2);
159 if (ret)
160 return ret;
161 }
162
163 return 0;
164 }
165
166 static int
dp_link_train_update(struct dp_state * dp,bool pc,u32 delay)167 dp_link_train_update(struct dp_state *dp, bool pc, u32 delay)
168 {
169 struct nvkm_output_dp *outp = dp->outp;
170 int ret;
171
172 if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
173 mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
174 else
175 udelay(delay);
176
177 ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6);
178 if (ret)
179 return ret;
180
181 if (pc) {
182 ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1);
183 if (ret)
184 dp->pc2stat = 0x00;
185 DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat);
186 } else {
187 DBG("status %6ph\n", dp->stat);
188 }
189
190 return 0;
191 }
192
193 static int
dp_link_train_cr(struct dp_state * dp)194 dp_link_train_cr(struct dp_state *dp)
195 {
196 bool cr_done = false, abort = false;
197 int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
198 int tries = 0, i;
199
200 dp_set_training_pattern(dp, 1);
201
202 do {
203 if (dp_link_train_commit(dp, false) ||
204 dp_link_train_update(dp, false, 100))
205 break;
206
207 cr_done = true;
208 for (i = 0; i < dp->link_nr; i++) {
209 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
210 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
211 cr_done = false;
212 if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
213 abort = true;
214 break;
215 }
216 }
217
218 if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
219 voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
220 tries = 0;
221 }
222 } while (!cr_done && !abort && ++tries < 5);
223
224 return cr_done ? 0 : -1;
225 }
226
227 static int
dp_link_train_eq(struct dp_state * dp)228 dp_link_train_eq(struct dp_state *dp)
229 {
230 struct nvkm_output_dp *outp = dp->outp;
231 bool eq_done = false, cr_done = true;
232 int tries = 0, i;
233
234 if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)
235 dp_set_training_pattern(dp, 3);
236 else
237 dp_set_training_pattern(dp, 2);
238
239 do {
240 if ((tries &&
241 dp_link_train_commit(dp, dp->pc2)) ||
242 dp_link_train_update(dp, dp->pc2, 400))
243 break;
244
245 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
246 for (i = 0; i < dp->link_nr && eq_done; i++) {
247 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
248 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
249 cr_done = false;
250 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
251 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
252 eq_done = false;
253 }
254 } while (!eq_done && cr_done && ++tries <= 5);
255
256 return eq_done ? 0 : -1;
257 }
258
259 static void
dp_link_train_init(struct dp_state * dp,bool spread)260 dp_link_train_init(struct dp_state *dp, bool spread)
261 {
262 struct nvkm_output_dp *outp = dp->outp;
263 struct nvkm_disp *disp = nvkm_disp(outp);
264 struct nvkm_bios *bios = nvkm_bios(disp);
265 struct nvbios_init init = {
266 .subdev = nv_subdev(disp),
267 .bios = bios,
268 .outp = &outp->base.info,
269 .crtc = -1,
270 .execute = 1,
271 };
272
273 /* set desired spread */
274 if (spread)
275 init.offset = outp->info.script[2];
276 else
277 init.offset = outp->info.script[3];
278 nvbios_exec(&init);
279
280 /* pre-train script */
281 init.offset = outp->info.script[0];
282 nvbios_exec(&init);
283 }
284
285 static void
dp_link_train_fini(struct dp_state * dp)286 dp_link_train_fini(struct dp_state *dp)
287 {
288 struct nvkm_output_dp *outp = dp->outp;
289 struct nvkm_disp *disp = nvkm_disp(outp);
290 struct nvkm_bios *bios = nvkm_bios(disp);
291 struct nvbios_init init = {
292 .subdev = nv_subdev(disp),
293 .bios = bios,
294 .outp = &outp->base.info,
295 .crtc = -1,
296 .execute = 1,
297 };
298
299 /* post-train script */
300 init.offset = outp->info.script[1],
301 nvbios_exec(&init);
302 }
303
304 static const struct dp_rates {
305 u32 rate;
306 u8 bw;
307 u8 nr;
308 } nvkm_dp_rates[] = {
309 { 2160000, 0x14, 4 },
310 { 1080000, 0x0a, 4 },
311 { 1080000, 0x14, 2 },
312 { 648000, 0x06, 4 },
313 { 540000, 0x0a, 2 },
314 { 540000, 0x14, 1 },
315 { 324000, 0x06, 2 },
316 { 270000, 0x0a, 1 },
317 { 162000, 0x06, 1 },
318 {}
319 };
320
321 void
nvkm_dp_train(struct work_struct * w)322 nvkm_dp_train(struct work_struct *w)
323 {
324 struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
325 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
326 const struct dp_rates *cfg = nvkm_dp_rates;
327 struct dp_state _dp = {
328 .outp = outp,
329 }, *dp = &_dp;
330 u32 datarate = 0;
331 int ret;
332
333 if (!outp->base.info.location && priv->sor.magic)
334 priv->sor.magic(&outp->base);
335
336 /* bring capabilities within encoder limits */
337 if (nv_mclass(priv) < GF110_DISP)
338 outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
339 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
340 outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
341 outp->dpcd[2] |= outp->base.info.dpconf.link_nr;
342 }
343 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw)
344 outp->dpcd[1] = outp->base.info.dpconf.link_bw;
345 dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED;
346
347 /* restrict link config to the lowest required rate, if requested */
348 if (datarate) {
349 datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */
350 while (cfg[1].rate >= datarate)
351 cfg++;
352 }
353 cfg--;
354
355 /* disable link interrupt handling during link training */
356 nvkm_notify_put(&outp->irq);
357
358 /* enable down-spreading and execute pre-train script from vbios */
359 dp_link_train_init(dp, outp->dpcd[3] & 0x01);
360
361 while (ret = -EIO, (++cfg)->rate) {
362 /* select next configuration supported by encoder and sink */
363 while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) ||
364 cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE]))
365 cfg++;
366 dp->link_bw = cfg->bw * 27000;
367 dp->link_nr = cfg->nr;
368
369 /* program selected link configuration */
370 ret = dp_set_link_config(dp);
371 if (ret == 0) {
372 /* attempt to train the link at this configuration */
373 memset(dp->stat, 0x00, sizeof(dp->stat));
374 if (!dp_link_train_cr(dp) &&
375 !dp_link_train_eq(dp))
376 break;
377 } else
378 if (ret) {
379 /* dp_set_link_config() handled training, or
380 * we failed to communicate with the sink.
381 */
382 break;
383 }
384 }
385
386 /* finish link training and execute post-train script from vbios */
387 dp_set_training_pattern(dp, 0);
388 if (ret < 0)
389 ERR("link training failed\n");
390
391 dp_link_train_fini(dp);
392
393 /* signal completion and enable link interrupt handling */
394 DBG("training complete\n");
395 atomic_set(&outp->lt.done, 1);
396 wake_up(&outp->lt.wait);
397 nvkm_notify_get(&outp->irq);
398 }
399