1 /*
2 * AD7190 AD7192 AD7195 SPI ADC driver
3 *
4 * Copyright 2011-2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
27
28 #include "ad7192.h"
29
30 /* Registers */
31 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
33 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
34 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
35 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
36 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
37 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
38 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
39 * (AD7792)/24-bit (AD7192)) */
40 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
41 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
42
43 /* Communications Register Bit Designations (AD7192_REG_COMM) */
44 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
45 #define AD7192_COMM_WRITE 0 /* Write Operation */
46 #define AD7192_COMM_READ BIT(6) /* Read Operation */
47 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
48 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
49
50 /* Status Register Bit Designations (AD7192_REG_STAT) */
51 #define AD7192_STAT_RDY BIT(7) /* Ready */
52 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
53 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
54 #define AD7192_STAT_PARITY BIT(4) /* Parity */
55 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
56 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
57 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
58
59 /* Mode Register Bit Designations (AD7192_REG_MODE) */
60 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
61 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
62 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
66 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
71
72 /* Mode Register: AD7192_MODE_SEL options */
73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
74 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
75 #define AD7192_MODE_IDLE 2 /* Idle Mode */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
77 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
81
82 /* Mode Register: AD7192_MODE_CLKSRC options */
83 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
84 * from MCLK1 to MCLK2 */
85 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
86 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
87 * available at the MCLK2 pin */
88 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
89 * at the MCLK2 pin */
90
91
92 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
93
94 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
95 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
96 #define AD7192_CONF_CHAN(x) (((1 << (x)) & 0xFF) << 8) /* Channel select */
97 #define AD7192_CONF_CHAN_MASK (0xFF << 8) /* Channel select mask */
98 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
99 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
100 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
101 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
102 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
103
104 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
105 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
106 #define AD7192_CH_TEMP 2 /* Temp Sensor */
107 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
108 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
109 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
110 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
111 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
112
113 /* ID Register Bit Designations (AD7192_REG_ID) */
114 #define ID_AD7190 0x4
115 #define ID_AD7192 0x0
116 #define ID_AD7195 0x6
117 #define AD7192_ID_MASK 0x0F
118
119 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
120 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
121 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
122 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
123 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
124 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
125 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
126 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
127
128 #define AD7192_INT_FREQ_MHz 4915200
129
130 /* NOTE:
131 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
132 * In order to avoid contentions on the SPI bus, it's therefore necessary
133 * to use spi bus locking.
134 *
135 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
136 */
137
138 struct ad7192_state {
139 struct regulator *reg;
140 u16 int_vref_mv;
141 u32 mclk;
142 u32 f_order;
143 u32 mode;
144 u32 conf;
145 u32 scale_avail[8][2];
146 u8 gpocon;
147 u8 devid;
148
149 struct ad_sigma_delta sd;
150 };
151
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)152 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
153 {
154 return container_of(sd, struct ad7192_state, sd);
155 }
156
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)157 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
158 {
159 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
160
161 st->conf &= ~AD7192_CONF_CHAN_MASK;
162 st->conf |= AD7192_CONF_CHAN(channel);
163
164 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
165 }
166
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)167 static int ad7192_set_mode(struct ad_sigma_delta *sd,
168 enum ad_sigma_delta_mode mode)
169 {
170 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
171
172 st->mode &= ~AD7192_MODE_SEL_MASK;
173 st->mode |= AD7192_MODE_SEL(mode);
174
175 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
176 }
177
178 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
179 .set_channel = ad7192_set_channel,
180 .set_mode = ad7192_set_mode,
181 .has_registers = true,
182 .addr_shift = 3,
183 .read_mask = BIT(6),
184 };
185
186 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
187 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
188 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
189 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
190 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
191 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
192 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
193 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
194 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
195 };
196
ad7192_calibrate_all(struct ad7192_state * st)197 static int ad7192_calibrate_all(struct ad7192_state *st)
198 {
199 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
200 ARRAY_SIZE(ad7192_calib_arr));
201 }
202
ad7192_setup(struct ad7192_state * st,const struct ad7192_platform_data * pdata)203 static int ad7192_setup(struct ad7192_state *st,
204 const struct ad7192_platform_data *pdata)
205 {
206 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
207 unsigned long long scale_uv;
208 int i, ret, id;
209 u8 ones[6];
210
211 /* reset the serial interface */
212 memset(&ones, 0xFF, 6);
213 ret = spi_write(st->sd.spi, &ones, 6);
214 if (ret < 0)
215 goto out;
216 usleep_range(500, 1000); /* Wait for at least 500us */
217
218 /* write/read test for device presence */
219 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
220 if (ret)
221 goto out;
222
223 id &= AD7192_ID_MASK;
224
225 if (id != st->devid)
226 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
227 id);
228
229 switch (pdata->clock_source_sel) {
230 case AD7192_CLK_EXT_MCLK1_2:
231 case AD7192_CLK_EXT_MCLK2:
232 st->mclk = AD7192_INT_FREQ_MHz;
233 break;
234 case AD7192_CLK_INT:
235 case AD7192_CLK_INT_CO:
236 if (pdata->ext_clk_Hz)
237 st->mclk = pdata->ext_clk_Hz;
238 else
239 st->mclk = AD7192_INT_FREQ_MHz;
240 break;
241 default:
242 ret = -EINVAL;
243 goto out;
244 }
245
246 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
247 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
248 AD7192_MODE_RATE(480);
249
250 st->conf = AD7192_CONF_GAIN(0);
251
252 if (pdata->rej60_en)
253 st->mode |= AD7192_MODE_REJ60;
254
255 if (pdata->sinc3_en)
256 st->mode |= AD7192_MODE_SINC3;
257
258 if (pdata->refin2_en && (st->devid != ID_AD7195))
259 st->conf |= AD7192_CONF_REFSEL;
260
261 if (pdata->chop_en) {
262 st->conf |= AD7192_CONF_CHOP;
263 if (pdata->sinc3_en)
264 st->f_order = 3; /* SINC 3rd order */
265 else
266 st->f_order = 4; /* SINC 4th order */
267 } else {
268 st->f_order = 1;
269 }
270
271 if (pdata->buf_en)
272 st->conf |= AD7192_CONF_BUF;
273
274 if (pdata->unipolar_en)
275 st->conf |= AD7192_CONF_UNIPOLAR;
276
277 if (pdata->burnout_curr_en)
278 st->conf |= AD7192_CONF_BURN;
279
280 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
281 if (ret)
282 goto out;
283
284 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
285 if (ret)
286 goto out;
287
288 ret = ad7192_calibrate_all(st);
289 if (ret)
290 goto out;
291
292 /* Populate available ADC input ranges */
293 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
294 scale_uv = ((u64)st->int_vref_mv * 100000000)
295 >> (indio_dev->channels[0].scan_type.realbits -
296 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
297 scale_uv >>= i;
298
299 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
300 st->scale_avail[i][0] = scale_uv;
301 }
302
303 return 0;
304 out:
305 dev_err(&st->sd.spi->dev, "setup failed\n");
306 return ret;
307 }
308
ad7192_read_frequency(struct device * dev,struct device_attribute * attr,char * buf)309 static ssize_t ad7192_read_frequency(struct device *dev,
310 struct device_attribute *attr,
311 char *buf)
312 {
313 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
314 struct ad7192_state *st = iio_priv(indio_dev);
315
316 return sprintf(buf, "%d\n", st->mclk /
317 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
318 }
319
ad7192_write_frequency(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)320 static ssize_t ad7192_write_frequency(struct device *dev,
321 struct device_attribute *attr,
322 const char *buf,
323 size_t len)
324 {
325 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
326 struct ad7192_state *st = iio_priv(indio_dev);
327 unsigned long lval;
328 int div, ret;
329
330 ret = kstrtoul(buf, 10, &lval);
331 if (ret)
332 return ret;
333 if (lval == 0)
334 return -EINVAL;
335
336 mutex_lock(&indio_dev->mlock);
337 if (iio_buffer_enabled(indio_dev)) {
338 mutex_unlock(&indio_dev->mlock);
339 return -EBUSY;
340 }
341
342 div = st->mclk / (lval * st->f_order * 1024);
343 if (div < 1 || div > 1023) {
344 ret = -EINVAL;
345 goto out;
346 }
347
348 st->mode &= ~AD7192_MODE_RATE(-1);
349 st->mode |= AD7192_MODE_RATE(div);
350 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
351
352 out:
353 mutex_unlock(&indio_dev->mlock);
354
355 return ret ? ret : len;
356 }
357
358 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
359 ad7192_read_frequency,
360 ad7192_write_frequency);
361
ad7192_show_scale_available(struct device * dev,struct device_attribute * attr,char * buf)362 static ssize_t ad7192_show_scale_available(struct device *dev,
363 struct device_attribute *attr, char *buf)
364 {
365 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
366 struct ad7192_state *st = iio_priv(indio_dev);
367 int i, len = 0;
368
369 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
370 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
371 st->scale_avail[i][1]);
372
373 len += sprintf(buf + len, "\n");
374
375 return len;
376 }
377
378 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
379 in_voltage-voltage_scale_available,
380 S_IRUGO, ad7192_show_scale_available, NULL, 0);
381
382 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
383 ad7192_show_scale_available, NULL, 0);
384
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)385 static ssize_t ad7192_show_ac_excitation(struct device *dev,
386 struct device_attribute *attr,
387 char *buf)
388 {
389 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
390 struct ad7192_state *st = iio_priv(indio_dev);
391
392 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
393 }
394
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)395 static ssize_t ad7192_show_bridge_switch(struct device *dev,
396 struct device_attribute *attr,
397 char *buf)
398 {
399 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
400 struct ad7192_state *st = iio_priv(indio_dev);
401
402 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
403 }
404
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)405 static ssize_t ad7192_set(struct device *dev,
406 struct device_attribute *attr,
407 const char *buf,
408 size_t len)
409 {
410 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
411 struct ad7192_state *st = iio_priv(indio_dev);
412 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
413 int ret;
414 bool val;
415
416 ret = strtobool(buf, &val);
417 if (ret < 0)
418 return ret;
419
420 mutex_lock(&indio_dev->mlock);
421 if (iio_buffer_enabled(indio_dev)) {
422 mutex_unlock(&indio_dev->mlock);
423 return -EBUSY;
424 }
425
426 switch ((u32) this_attr->address) {
427 case AD7192_REG_GPOCON:
428 if (val)
429 st->gpocon |= AD7192_GPOCON_BPDSW;
430 else
431 st->gpocon &= ~AD7192_GPOCON_BPDSW;
432
433 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
434 break;
435 case AD7192_REG_MODE:
436 if (val)
437 st->mode |= AD7192_MODE_ACX;
438 else
439 st->mode &= ~AD7192_MODE_ACX;
440
441 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
442 break;
443 default:
444 ret = -EINVAL;
445 }
446
447 mutex_unlock(&indio_dev->mlock);
448
449 return ret ? ret : len;
450 }
451
452 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
453 ad7192_show_bridge_switch, ad7192_set,
454 AD7192_REG_GPOCON);
455
456 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
457 ad7192_show_ac_excitation, ad7192_set,
458 AD7192_REG_MODE);
459
460 static struct attribute *ad7192_attributes[] = {
461 &iio_dev_attr_sampling_frequency.dev_attr.attr,
462 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
463 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
464 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
465 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
466 NULL
467 };
468
469 static const struct attribute_group ad7192_attribute_group = {
470 .attrs = ad7192_attributes,
471 };
472
473 static struct attribute *ad7195_attributes[] = {
474 &iio_dev_attr_sampling_frequency.dev_attr.attr,
475 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
476 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
477 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
478 NULL
479 };
480
481 static const struct attribute_group ad7195_attribute_group = {
482 .attrs = ad7195_attributes,
483 };
484
ad7192_get_temp_scale(bool unipolar)485 static unsigned int ad7192_get_temp_scale(bool unipolar)
486 {
487 return unipolar ? 2815 * 2 : 2815;
488 }
489
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)490 static int ad7192_read_raw(struct iio_dev *indio_dev,
491 struct iio_chan_spec const *chan,
492 int *val,
493 int *val2,
494 long m)
495 {
496 struct ad7192_state *st = iio_priv(indio_dev);
497 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
498
499 switch (m) {
500 case IIO_CHAN_INFO_RAW:
501 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
502 case IIO_CHAN_INFO_SCALE:
503 switch (chan->type) {
504 case IIO_VOLTAGE:
505 mutex_lock(&indio_dev->mlock);
506 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
507 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
508 mutex_unlock(&indio_dev->mlock);
509 return IIO_VAL_INT_PLUS_NANO;
510 case IIO_TEMP:
511 *val = 0;
512 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
513 return IIO_VAL_INT_PLUS_NANO;
514 default:
515 return -EINVAL;
516 }
517 case IIO_CHAN_INFO_OFFSET:
518 if (!unipolar)
519 *val = -(1 << (chan->scan_type.realbits - 1));
520 else
521 *val = 0;
522 /* Kelvin to Celsius */
523 if (chan->type == IIO_TEMP)
524 *val -= 273 * ad7192_get_temp_scale(unipolar);
525 return IIO_VAL_INT;
526 }
527
528 return -EINVAL;
529 }
530
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)531 static int ad7192_write_raw(struct iio_dev *indio_dev,
532 struct iio_chan_spec const *chan,
533 int val,
534 int val2,
535 long mask)
536 {
537 struct ad7192_state *st = iio_priv(indio_dev);
538 int ret, i;
539 unsigned int tmp;
540
541 mutex_lock(&indio_dev->mlock);
542 if (iio_buffer_enabled(indio_dev)) {
543 mutex_unlock(&indio_dev->mlock);
544 return -EBUSY;
545 }
546
547 switch (mask) {
548 case IIO_CHAN_INFO_SCALE:
549 ret = -EINVAL;
550 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
551 if (val2 == st->scale_avail[i][1]) {
552 ret = 0;
553 tmp = st->conf;
554 st->conf &= ~AD7192_CONF_GAIN(-1);
555 st->conf |= AD7192_CONF_GAIN(i);
556 if (tmp == st->conf)
557 break;
558 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
559 3, st->conf);
560 ad7192_calibrate_all(st);
561 break;
562 }
563 break;
564 default:
565 ret = -EINVAL;
566 }
567
568 mutex_unlock(&indio_dev->mlock);
569
570 return ret;
571 }
572
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)573 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
574 struct iio_chan_spec const *chan,
575 long mask)
576 {
577 return IIO_VAL_INT_PLUS_NANO;
578 }
579
580 static const struct iio_info ad7192_info = {
581 .read_raw = &ad7192_read_raw,
582 .write_raw = &ad7192_write_raw,
583 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
584 .attrs = &ad7192_attribute_group,
585 .validate_trigger = ad_sd_validate_trigger,
586 .driver_module = THIS_MODULE,
587 };
588
589 static const struct iio_info ad7195_info = {
590 .read_raw = &ad7192_read_raw,
591 .write_raw = &ad7192_write_raw,
592 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
593 .attrs = &ad7195_attribute_group,
594 .validate_trigger = ad_sd_validate_trigger,
595 .driver_module = THIS_MODULE,
596 };
597
598 static const struct iio_chan_spec ad7192_channels[] = {
599 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
600 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
601 AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
602 AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
603 AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
604 AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
605 AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
606 AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
607 IIO_CHAN_SOFT_TIMESTAMP(8),
608 };
609
ad7192_probe(struct spi_device * spi)610 static int ad7192_probe(struct spi_device *spi)
611 {
612 const struct ad7192_platform_data *pdata = spi->dev.platform_data;
613 struct ad7192_state *st;
614 struct iio_dev *indio_dev;
615 int ret, voltage_uv = 0;
616
617 if (!pdata) {
618 dev_err(&spi->dev, "no platform data?\n");
619 return -ENODEV;
620 }
621
622 if (!spi->irq) {
623 dev_err(&spi->dev, "no IRQ?\n");
624 return -ENODEV;
625 }
626
627 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
628 if (indio_dev == NULL)
629 return -ENOMEM;
630
631 st = iio_priv(indio_dev);
632
633 st->reg = devm_regulator_get(&spi->dev, "vcc");
634 if (!IS_ERR(st->reg)) {
635 ret = regulator_enable(st->reg);
636 if (ret)
637 return ret;
638
639 voltage_uv = regulator_get_voltage(st->reg);
640 }
641
642 if (pdata && pdata->vref_mv)
643 st->int_vref_mv = pdata->vref_mv;
644 else if (voltage_uv)
645 st->int_vref_mv = voltage_uv / 1000;
646 else
647 dev_warn(&spi->dev, "reference voltage undefined\n");
648
649 spi_set_drvdata(spi, indio_dev);
650 st->devid = spi_get_device_id(spi)->driver_data;
651 indio_dev->dev.parent = &spi->dev;
652 indio_dev->name = spi_get_device_id(spi)->name;
653 indio_dev->modes = INDIO_DIRECT_MODE;
654 indio_dev->channels = ad7192_channels;
655 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
656 if (st->devid == ID_AD7195)
657 indio_dev->info = &ad7195_info;
658 else
659 indio_dev->info = &ad7192_info;
660
661 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
662
663 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
664 if (ret)
665 goto error_disable_reg;
666
667 ret = ad7192_setup(st, pdata);
668 if (ret)
669 goto error_remove_trigger;
670
671 ret = iio_device_register(indio_dev);
672 if (ret < 0)
673 goto error_remove_trigger;
674 return 0;
675
676 error_remove_trigger:
677 ad_sd_cleanup_buffer_and_trigger(indio_dev);
678 error_disable_reg:
679 if (!IS_ERR(st->reg))
680 regulator_disable(st->reg);
681
682 return ret;
683 }
684
ad7192_remove(struct spi_device * spi)685 static int ad7192_remove(struct spi_device *spi)
686 {
687 struct iio_dev *indio_dev = spi_get_drvdata(spi);
688 struct ad7192_state *st = iio_priv(indio_dev);
689
690 iio_device_unregister(indio_dev);
691 ad_sd_cleanup_buffer_and_trigger(indio_dev);
692
693 if (!IS_ERR(st->reg))
694 regulator_disable(st->reg);
695
696 return 0;
697 }
698
699 static const struct spi_device_id ad7192_id[] = {
700 {"ad7190", ID_AD7190},
701 {"ad7192", ID_AD7192},
702 {"ad7195", ID_AD7195},
703 {}
704 };
705 MODULE_DEVICE_TABLE(spi, ad7192_id);
706
707 static struct spi_driver ad7192_driver = {
708 .driver = {
709 .name = "ad7192",
710 .owner = THIS_MODULE,
711 },
712 .probe = ad7192_probe,
713 .remove = ad7192_remove,
714 .id_table = ad7192_id,
715 };
716 module_spi_driver(ad7192_driver);
717
718 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
719 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
720 MODULE_LICENSE("GPL v2");
721