1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/of.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #include "sh-sci.h"
60
61 /* Offsets into the sci_port->irqs array */
62 enum {
63 SCIx_ERI_IRQ,
64 SCIx_RXI_IRQ,
65 SCIx_TXI_IRQ,
66 SCIx_BRI_IRQ,
67 SCIx_NR_IRQS,
68
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
70 };
71
72 #define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
77
78 struct sci_port {
79 struct uart_port port;
80
81 /* Platform configuration */
82 struct plat_sci_port *cfg;
83 unsigned int overrun_reg;
84 unsigned int overrun_mask;
85 unsigned int error_mask;
86 unsigned int error_clear;
87 unsigned int sampling_rate;
88 resource_size_t reg_size;
89
90 /* Break timer */
91 struct timer_list break_timer;
92 int break_flag;
93
94 /* Interface clock */
95 struct clk *iclk;
96 /* Function clock */
97 struct clk *fclk;
98
99 int irqs[SCIx_NR_IRQS];
100 char *irqstr[SCIx_NR_IRQS];
101
102 struct dma_chan *chan_tx;
103 struct dma_chan *chan_rx;
104
105 #ifdef CONFIG_SERIAL_SH_SCI_DMA
106 dma_cookie_t cookie_tx;
107 dma_cookie_t cookie_rx[2];
108 dma_cookie_t active_rx;
109 dma_addr_t tx_dma_addr;
110 unsigned int tx_dma_len;
111 struct scatterlist sg_rx[2];
112 void *rx_buf[2];
113 size_t buf_len_rx;
114 struct work_struct work_tx;
115 struct timer_list rx_timer;
116 unsigned int rx_timeout;
117 #endif
118 };
119
120 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
121
122 static struct sci_port sci_ports[SCI_NPORTS];
123 static struct uart_driver sci_uart_driver;
124
125 static inline struct sci_port *
to_sci_port(struct uart_port * uart)126 to_sci_port(struct uart_port *uart)
127 {
128 return container_of(uart, struct sci_port, port);
129 }
130
131 struct plat_sci_reg {
132 u8 offset, size;
133 };
134
135 /* Helper for invalidating specific entries of an inherited map. */
136 #define sci_reg_invalid { .offset = 0, .size = 0 }
137
138 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
139 [SCIx_PROBE_REGTYPE] = {
140 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
141 },
142
143 /*
144 * Common SCI definitions, dependent on the port's regshift
145 * value.
146 */
147 [SCIx_SCI_REGTYPE] = {
148 [SCSMR] = { 0x00, 8 },
149 [SCBRR] = { 0x01, 8 },
150 [SCSCR] = { 0x02, 8 },
151 [SCxTDR] = { 0x03, 8 },
152 [SCxSR] = { 0x04, 8 },
153 [SCxRDR] = { 0x05, 8 },
154 [SCFCR] = sci_reg_invalid,
155 [SCFDR] = sci_reg_invalid,
156 [SCTFDR] = sci_reg_invalid,
157 [SCRFDR] = sci_reg_invalid,
158 [SCSPTR] = sci_reg_invalid,
159 [SCLSR] = sci_reg_invalid,
160 [HSSRR] = sci_reg_invalid,
161 [SCPCR] = sci_reg_invalid,
162 [SCPDR] = sci_reg_invalid,
163 },
164
165 /*
166 * Common definitions for legacy IrDA ports, dependent on
167 * regshift value.
168 */
169 [SCIx_IRDA_REGTYPE] = {
170 [SCSMR] = { 0x00, 8 },
171 [SCBRR] = { 0x01, 8 },
172 [SCSCR] = { 0x02, 8 },
173 [SCxTDR] = { 0x03, 8 },
174 [SCxSR] = { 0x04, 8 },
175 [SCxRDR] = { 0x05, 8 },
176 [SCFCR] = { 0x06, 8 },
177 [SCFDR] = { 0x07, 16 },
178 [SCTFDR] = sci_reg_invalid,
179 [SCRFDR] = sci_reg_invalid,
180 [SCSPTR] = sci_reg_invalid,
181 [SCLSR] = sci_reg_invalid,
182 [HSSRR] = sci_reg_invalid,
183 [SCPCR] = sci_reg_invalid,
184 [SCPDR] = sci_reg_invalid,
185 },
186
187 /*
188 * Common SCIFA definitions.
189 */
190 [SCIx_SCIFA_REGTYPE] = {
191 [SCSMR] = { 0x00, 16 },
192 [SCBRR] = { 0x04, 8 },
193 [SCSCR] = { 0x08, 16 },
194 [SCxTDR] = { 0x20, 8 },
195 [SCxSR] = { 0x14, 16 },
196 [SCxRDR] = { 0x24, 8 },
197 [SCFCR] = { 0x18, 16 },
198 [SCFDR] = { 0x1c, 16 },
199 [SCTFDR] = sci_reg_invalid,
200 [SCRFDR] = sci_reg_invalid,
201 [SCSPTR] = sci_reg_invalid,
202 [SCLSR] = sci_reg_invalid,
203 [HSSRR] = sci_reg_invalid,
204 [SCPCR] = { 0x30, 16 },
205 [SCPDR] = { 0x34, 16 },
206 },
207
208 /*
209 * Common SCIFB definitions.
210 */
211 [SCIx_SCIFB_REGTYPE] = {
212 [SCSMR] = { 0x00, 16 },
213 [SCBRR] = { 0x04, 8 },
214 [SCSCR] = { 0x08, 16 },
215 [SCxTDR] = { 0x40, 8 },
216 [SCxSR] = { 0x14, 16 },
217 [SCxRDR] = { 0x60, 8 },
218 [SCFCR] = { 0x18, 16 },
219 [SCFDR] = sci_reg_invalid,
220 [SCTFDR] = { 0x38, 16 },
221 [SCRFDR] = { 0x3c, 16 },
222 [SCSPTR] = sci_reg_invalid,
223 [SCLSR] = sci_reg_invalid,
224 [HSSRR] = sci_reg_invalid,
225 [SCPCR] = { 0x30, 16 },
226 [SCPDR] = { 0x34, 16 },
227 },
228
229 /*
230 * Common SH-2(A) SCIF definitions for ports with FIFO data
231 * count registers.
232 */
233 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
234 [SCSMR] = { 0x00, 16 },
235 [SCBRR] = { 0x04, 8 },
236 [SCSCR] = { 0x08, 16 },
237 [SCxTDR] = { 0x0c, 8 },
238 [SCxSR] = { 0x10, 16 },
239 [SCxRDR] = { 0x14, 8 },
240 [SCFCR] = { 0x18, 16 },
241 [SCFDR] = { 0x1c, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = { 0x20, 16 },
245 [SCLSR] = { 0x24, 16 },
246 [HSSRR] = sci_reg_invalid,
247 [SCPCR] = sci_reg_invalid,
248 [SCPDR] = sci_reg_invalid,
249 },
250
251 /*
252 * Common SH-3 SCIF definitions.
253 */
254 [SCIx_SH3_SCIF_REGTYPE] = {
255 [SCSMR] = { 0x00, 8 },
256 [SCBRR] = { 0x02, 8 },
257 [SCSCR] = { 0x04, 8 },
258 [SCxTDR] = { 0x06, 8 },
259 [SCxSR] = { 0x08, 16 },
260 [SCxRDR] = { 0x0a, 8 },
261 [SCFCR] = { 0x0c, 8 },
262 [SCFDR] = { 0x0e, 16 },
263 [SCTFDR] = sci_reg_invalid,
264 [SCRFDR] = sci_reg_invalid,
265 [SCSPTR] = sci_reg_invalid,
266 [SCLSR] = sci_reg_invalid,
267 [HSSRR] = sci_reg_invalid,
268 [SCPCR] = sci_reg_invalid,
269 [SCPDR] = sci_reg_invalid,
270 },
271
272 /*
273 * Common SH-4(A) SCIF(B) definitions.
274 */
275 [SCIx_SH4_SCIF_REGTYPE] = {
276 [SCSMR] = { 0x00, 16 },
277 [SCBRR] = { 0x04, 8 },
278 [SCSCR] = { 0x08, 16 },
279 [SCxTDR] = { 0x0c, 8 },
280 [SCxSR] = { 0x10, 16 },
281 [SCxRDR] = { 0x14, 8 },
282 [SCFCR] = { 0x18, 16 },
283 [SCFDR] = { 0x1c, 16 },
284 [SCTFDR] = sci_reg_invalid,
285 [SCRFDR] = sci_reg_invalid,
286 [SCSPTR] = { 0x20, 16 },
287 [SCLSR] = { 0x24, 16 },
288 [HSSRR] = sci_reg_invalid,
289 [SCPCR] = sci_reg_invalid,
290 [SCPDR] = sci_reg_invalid,
291 },
292
293 /*
294 * Common HSCIF definitions.
295 */
296 [SCIx_HSCIF_REGTYPE] = {
297 [SCSMR] = { 0x00, 16 },
298 [SCBRR] = { 0x04, 8 },
299 [SCSCR] = { 0x08, 16 },
300 [SCxTDR] = { 0x0c, 8 },
301 [SCxSR] = { 0x10, 16 },
302 [SCxRDR] = { 0x14, 8 },
303 [SCFCR] = { 0x18, 16 },
304 [SCFDR] = { 0x1c, 16 },
305 [SCTFDR] = sci_reg_invalid,
306 [SCRFDR] = sci_reg_invalid,
307 [SCSPTR] = { 0x20, 16 },
308 [SCLSR] = { 0x24, 16 },
309 [HSSRR] = { 0x40, 16 },
310 [SCPCR] = sci_reg_invalid,
311 [SCPDR] = sci_reg_invalid,
312 },
313
314 /*
315 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
316 * register.
317 */
318 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
319 [SCSMR] = { 0x00, 16 },
320 [SCBRR] = { 0x04, 8 },
321 [SCSCR] = { 0x08, 16 },
322 [SCxTDR] = { 0x0c, 8 },
323 [SCxSR] = { 0x10, 16 },
324 [SCxRDR] = { 0x14, 8 },
325 [SCFCR] = { 0x18, 16 },
326 [SCFDR] = { 0x1c, 16 },
327 [SCTFDR] = sci_reg_invalid,
328 [SCRFDR] = sci_reg_invalid,
329 [SCSPTR] = sci_reg_invalid,
330 [SCLSR] = { 0x24, 16 },
331 [HSSRR] = sci_reg_invalid,
332 [SCPCR] = sci_reg_invalid,
333 [SCPDR] = sci_reg_invalid,
334 },
335
336 /*
337 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
338 * count registers.
339 */
340 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
350 [SCRFDR] = { 0x20, 16 },
351 [SCSPTR] = { 0x24, 16 },
352 [SCLSR] = { 0x28, 16 },
353 [HSSRR] = sci_reg_invalid,
354 [SCPCR] = sci_reg_invalid,
355 [SCPDR] = sci_reg_invalid,
356 },
357
358 /*
359 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
360 * registers.
361 */
362 [SCIx_SH7705_SCIF_REGTYPE] = {
363 [SCSMR] = { 0x00, 16 },
364 [SCBRR] = { 0x04, 8 },
365 [SCSCR] = { 0x08, 16 },
366 [SCxTDR] = { 0x20, 8 },
367 [SCxSR] = { 0x14, 16 },
368 [SCxRDR] = { 0x24, 8 },
369 [SCFCR] = { 0x18, 16 },
370 [SCFDR] = { 0x1c, 16 },
371 [SCTFDR] = sci_reg_invalid,
372 [SCRFDR] = sci_reg_invalid,
373 [SCSPTR] = sci_reg_invalid,
374 [SCLSR] = sci_reg_invalid,
375 [HSSRR] = sci_reg_invalid,
376 [SCPCR] = sci_reg_invalid,
377 [SCPDR] = sci_reg_invalid,
378 },
379 };
380
381 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
382
383 /*
384 * The "offset" here is rather misleading, in that it refers to an enum
385 * value relative to the port mapping rather than the fixed offset
386 * itself, which needs to be manually retrieved from the platform's
387 * register map for the given port.
388 */
sci_serial_in(struct uart_port * p,int offset)389 static unsigned int sci_serial_in(struct uart_port *p, int offset)
390 {
391 const struct plat_sci_reg *reg = sci_getreg(p, offset);
392
393 if (reg->size == 8)
394 return ioread8(p->membase + (reg->offset << p->regshift));
395 else if (reg->size == 16)
396 return ioread16(p->membase + (reg->offset << p->regshift));
397 else
398 WARN(1, "Invalid register access\n");
399
400 return 0;
401 }
402
sci_serial_out(struct uart_port * p,int offset,int value)403 static void sci_serial_out(struct uart_port *p, int offset, int value)
404 {
405 const struct plat_sci_reg *reg = sci_getreg(p, offset);
406
407 if (reg->size == 8)
408 iowrite8(value, p->membase + (reg->offset << p->regshift));
409 else if (reg->size == 16)
410 iowrite16(value, p->membase + (reg->offset << p->regshift));
411 else
412 WARN(1, "Invalid register access\n");
413 }
414
sci_probe_regmap(struct plat_sci_port * cfg)415 static int sci_probe_regmap(struct plat_sci_port *cfg)
416 {
417 switch (cfg->type) {
418 case PORT_SCI:
419 cfg->regtype = SCIx_SCI_REGTYPE;
420 break;
421 case PORT_IRDA:
422 cfg->regtype = SCIx_IRDA_REGTYPE;
423 break;
424 case PORT_SCIFA:
425 cfg->regtype = SCIx_SCIFA_REGTYPE;
426 break;
427 case PORT_SCIFB:
428 cfg->regtype = SCIx_SCIFB_REGTYPE;
429 break;
430 case PORT_SCIF:
431 /*
432 * The SH-4 is a bit of a misnomer here, although that's
433 * where this particular port layout originated. This
434 * configuration (or some slight variation thereof)
435 * remains the dominant model for all SCIFs.
436 */
437 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
438 break;
439 case PORT_HSCIF:
440 cfg->regtype = SCIx_HSCIF_REGTYPE;
441 break;
442 default:
443 pr_err("Can't probe register map for given port\n");
444 return -EINVAL;
445 }
446
447 return 0;
448 }
449
sci_port_enable(struct sci_port * sci_port)450 static void sci_port_enable(struct sci_port *sci_port)
451 {
452 if (!sci_port->port.dev)
453 return;
454
455 pm_runtime_get_sync(sci_port->port.dev);
456
457 clk_prepare_enable(sci_port->iclk);
458 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
459 clk_prepare_enable(sci_port->fclk);
460 }
461
sci_port_disable(struct sci_port * sci_port)462 static void sci_port_disable(struct sci_port *sci_port)
463 {
464 if (!sci_port->port.dev)
465 return;
466
467 /* Cancel the break timer to ensure that the timer handler will not try
468 * to access the hardware with clocks and power disabled. Reset the
469 * break flag to make the break debouncing state machine ready for the
470 * next break.
471 */
472 del_timer_sync(&sci_port->break_timer);
473 sci_port->break_flag = 0;
474
475 clk_disable_unprepare(sci_port->fclk);
476 clk_disable_unprepare(sci_port->iclk);
477
478 pm_runtime_put_sync(sci_port->port.dev);
479 }
480
port_rx_irq_mask(struct uart_port * port)481 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
482 {
483 /*
484 * Not all ports (such as SCIFA) will support REIE. Rather than
485 * special-casing the port type, we check the port initialization
486 * IRQ enable mask to see whether the IRQ is desired at all. If
487 * it's unset, it's logically inferred that there's no point in
488 * testing for it.
489 */
490 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
491 }
492
sci_start_tx(struct uart_port * port)493 static void sci_start_tx(struct uart_port *port)
494 {
495 struct sci_port *s = to_sci_port(port);
496 unsigned short ctrl;
497
498 #ifdef CONFIG_SERIAL_SH_SCI_DMA
499 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
500 u16 new, scr = serial_port_in(port, SCSCR);
501 if (s->chan_tx)
502 new = scr | SCSCR_TDRQE;
503 else
504 new = scr & ~SCSCR_TDRQE;
505 if (new != scr)
506 serial_port_out(port, SCSCR, new);
507 }
508
509 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
510 dma_submit_error(s->cookie_tx)) {
511 s->cookie_tx = 0;
512 schedule_work(&s->work_tx);
513 }
514 #endif
515
516 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
517 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
518 ctrl = serial_port_in(port, SCSCR);
519 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
520 }
521 }
522
sci_stop_tx(struct uart_port * port)523 static void sci_stop_tx(struct uart_port *port)
524 {
525 unsigned short ctrl;
526
527 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
528 ctrl = serial_port_in(port, SCSCR);
529
530 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
531 ctrl &= ~SCSCR_TDRQE;
532
533 ctrl &= ~SCSCR_TIE;
534
535 serial_port_out(port, SCSCR, ctrl);
536 }
537
sci_start_rx(struct uart_port * port)538 static void sci_start_rx(struct uart_port *port)
539 {
540 unsigned short ctrl;
541
542 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
543
544 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
545 ctrl &= ~SCSCR_RDRQE;
546
547 serial_port_out(port, SCSCR, ctrl);
548 }
549
sci_stop_rx(struct uart_port * port)550 static void sci_stop_rx(struct uart_port *port)
551 {
552 unsigned short ctrl;
553
554 ctrl = serial_port_in(port, SCSCR);
555
556 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
557 ctrl &= ~SCSCR_RDRQE;
558
559 ctrl &= ~port_rx_irq_mask(port);
560
561 serial_port_out(port, SCSCR, ctrl);
562 }
563
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)564 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
565 {
566 if (port->type == PORT_SCI) {
567 /* Just store the mask */
568 serial_port_out(port, SCxSR, mask);
569 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
570 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
571 /* Only clear the status bits we want to clear */
572 serial_port_out(port, SCxSR,
573 serial_port_in(port, SCxSR) & mask);
574 } else {
575 /* Store the mask, clear parity/framing errors */
576 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
577 }
578 }
579
580 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
581
582 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)583 static int sci_poll_get_char(struct uart_port *port)
584 {
585 unsigned short status;
586 int c;
587
588 do {
589 status = serial_port_in(port, SCxSR);
590 if (status & SCxSR_ERRORS(port)) {
591 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
592 continue;
593 }
594 break;
595 } while (1);
596
597 if (!(status & SCxSR_RDxF(port)))
598 return NO_POLL_CHAR;
599
600 c = serial_port_in(port, SCxRDR);
601
602 /* Dummy read */
603 serial_port_in(port, SCxSR);
604 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
605
606 return c;
607 }
608 #endif
609
sci_poll_put_char(struct uart_port * port,unsigned char c)610 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
611 {
612 unsigned short status;
613
614 do {
615 status = serial_port_in(port, SCxSR);
616 } while (!(status & SCxSR_TDxE(port)));
617
618 serial_port_out(port, SCxTDR, c);
619 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
620 }
621 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
622
sci_init_pins(struct uart_port * port,unsigned int cflag)623 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
624 {
625 struct sci_port *s = to_sci_port(port);
626 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
627
628 /*
629 * Use port-specific handler if provided.
630 */
631 if (s->cfg->ops && s->cfg->ops->init_pins) {
632 s->cfg->ops->init_pins(port, cflag);
633 return;
634 }
635
636 /*
637 * For the generic path SCSPTR is necessary. Bail out if that's
638 * unavailable, too.
639 */
640 if (!reg->size)
641 return;
642
643 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
644 ((!(cflag & CRTSCTS)))) {
645 unsigned short status;
646
647 status = serial_port_in(port, SCSPTR);
648 status &= ~SCSPTR_CTSIO;
649 status |= SCSPTR_RTSIO;
650 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
651 }
652 }
653
sci_txfill(struct uart_port * port)654 static int sci_txfill(struct uart_port *port)
655 {
656 const struct plat_sci_reg *reg;
657
658 reg = sci_getreg(port, SCTFDR);
659 if (reg->size)
660 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
661
662 reg = sci_getreg(port, SCFDR);
663 if (reg->size)
664 return serial_port_in(port, SCFDR) >> 8;
665
666 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
667 }
668
sci_txroom(struct uart_port * port)669 static int sci_txroom(struct uart_port *port)
670 {
671 return port->fifosize - sci_txfill(port);
672 }
673
sci_rxfill(struct uart_port * port)674 static int sci_rxfill(struct uart_port *port)
675 {
676 const struct plat_sci_reg *reg;
677
678 reg = sci_getreg(port, SCRFDR);
679 if (reg->size)
680 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
681
682 reg = sci_getreg(port, SCFDR);
683 if (reg->size)
684 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
685
686 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
687 }
688
689 /*
690 * SCI helper for checking the state of the muxed port/RXD pins.
691 */
sci_rxd_in(struct uart_port * port)692 static inline int sci_rxd_in(struct uart_port *port)
693 {
694 struct sci_port *s = to_sci_port(port);
695
696 if (s->cfg->port_reg <= 0)
697 return 1;
698
699 /* Cast for ARM damage */
700 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
701 }
702
703 /* ********************************************************************** *
704 * the interrupt related routines *
705 * ********************************************************************** */
706
sci_transmit_chars(struct uart_port * port)707 static void sci_transmit_chars(struct uart_port *port)
708 {
709 struct circ_buf *xmit = &port->state->xmit;
710 unsigned int stopped = uart_tx_stopped(port);
711 unsigned short status;
712 unsigned short ctrl;
713 int count;
714
715 status = serial_port_in(port, SCxSR);
716 if (!(status & SCxSR_TDxE(port))) {
717 ctrl = serial_port_in(port, SCSCR);
718 if (uart_circ_empty(xmit))
719 ctrl &= ~SCSCR_TIE;
720 else
721 ctrl |= SCSCR_TIE;
722 serial_port_out(port, SCSCR, ctrl);
723 return;
724 }
725
726 count = sci_txroom(port);
727
728 do {
729 unsigned char c;
730
731 if (port->x_char) {
732 c = port->x_char;
733 port->x_char = 0;
734 } else if (!uart_circ_empty(xmit) && !stopped) {
735 c = xmit->buf[xmit->tail];
736 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
737 } else {
738 break;
739 }
740
741 serial_port_out(port, SCxTDR, c);
742
743 port->icount.tx++;
744 } while (--count > 0);
745
746 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
747
748 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
749 uart_write_wakeup(port);
750 if (uart_circ_empty(xmit)) {
751 sci_stop_tx(port);
752 } else {
753 ctrl = serial_port_in(port, SCSCR);
754
755 if (port->type != PORT_SCI) {
756 serial_port_in(port, SCxSR); /* Dummy read */
757 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
758 }
759
760 ctrl |= SCSCR_TIE;
761 serial_port_out(port, SCSCR, ctrl);
762 }
763 }
764
765 /* On SH3, SCIF may read end-of-break as a space->mark char */
766 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
767
sci_receive_chars(struct uart_port * port)768 static void sci_receive_chars(struct uart_port *port)
769 {
770 struct sci_port *sci_port = to_sci_port(port);
771 struct tty_port *tport = &port->state->port;
772 int i, count, copied = 0;
773 unsigned short status;
774 unsigned char flag;
775
776 status = serial_port_in(port, SCxSR);
777 if (!(status & SCxSR_RDxF(port)))
778 return;
779
780 while (1) {
781 /* Don't copy more bytes than there is room for in the buffer */
782 count = tty_buffer_request_room(tport, sci_rxfill(port));
783
784 /* If for any reason we can't copy more data, we're done! */
785 if (count == 0)
786 break;
787
788 if (port->type == PORT_SCI) {
789 char c = serial_port_in(port, SCxRDR);
790 if (uart_handle_sysrq_char(port, c) ||
791 sci_port->break_flag)
792 count = 0;
793 else
794 tty_insert_flip_char(tport, c, TTY_NORMAL);
795 } else {
796 for (i = 0; i < count; i++) {
797 char c = serial_port_in(port, SCxRDR);
798
799 status = serial_port_in(port, SCxSR);
800 #if defined(CONFIG_CPU_SH3)
801 /* Skip "chars" during break */
802 if (sci_port->break_flag) {
803 if ((c == 0) &&
804 (status & SCxSR_FER(port))) {
805 count--; i--;
806 continue;
807 }
808
809 /* Nonzero => end-of-break */
810 dev_dbg(port->dev, "debounce<%02x>\n", c);
811 sci_port->break_flag = 0;
812
813 if (STEPFN(c)) {
814 count--; i--;
815 continue;
816 }
817 }
818 #endif /* CONFIG_CPU_SH3 */
819 if (uart_handle_sysrq_char(port, c)) {
820 count--; i--;
821 continue;
822 }
823
824 /* Store data and status */
825 if (status & SCxSR_FER(port)) {
826 flag = TTY_FRAME;
827 port->icount.frame++;
828 dev_notice(port->dev, "frame error\n");
829 } else if (status & SCxSR_PER(port)) {
830 flag = TTY_PARITY;
831 port->icount.parity++;
832 dev_notice(port->dev, "parity error\n");
833 } else
834 flag = TTY_NORMAL;
835
836 tty_insert_flip_char(tport, c, flag);
837 }
838 }
839
840 serial_port_in(port, SCxSR); /* dummy read */
841 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
842
843 copied += count;
844 port->icount.rx += count;
845 }
846
847 if (copied) {
848 /* Tell the rest of the system the news. New characters! */
849 tty_flip_buffer_push(tport);
850 } else {
851 serial_port_in(port, SCxSR); /* dummy read */
852 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
853 }
854 }
855
856 #define SCI_BREAK_JIFFIES (HZ/20)
857
858 /*
859 * The sci generates interrupts during the break,
860 * 1 per millisecond or so during the break period, for 9600 baud.
861 * So dont bother disabling interrupts.
862 * But dont want more than 1 break event.
863 * Use a kernel timer to periodically poll the rx line until
864 * the break is finished.
865 */
sci_schedule_break_timer(struct sci_port * port)866 static inline void sci_schedule_break_timer(struct sci_port *port)
867 {
868 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
869 }
870
871 /* Ensure that two consecutive samples find the break over. */
sci_break_timer(unsigned long data)872 static void sci_break_timer(unsigned long data)
873 {
874 struct sci_port *port = (struct sci_port *)data;
875
876 if (sci_rxd_in(&port->port) == 0) {
877 port->break_flag = 1;
878 sci_schedule_break_timer(port);
879 } else if (port->break_flag == 1) {
880 /* break is over. */
881 port->break_flag = 2;
882 sci_schedule_break_timer(port);
883 } else
884 port->break_flag = 0;
885 }
886
sci_handle_errors(struct uart_port * port)887 static int sci_handle_errors(struct uart_port *port)
888 {
889 int copied = 0;
890 unsigned short status = serial_port_in(port, SCxSR);
891 struct tty_port *tport = &port->state->port;
892 struct sci_port *s = to_sci_port(port);
893
894 /* Handle overruns */
895 if (status & s->overrun_mask) {
896 port->icount.overrun++;
897
898 /* overrun error */
899 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
900 copied++;
901
902 dev_notice(port->dev, "overrun error\n");
903 }
904
905 if (status & SCxSR_FER(port)) {
906 if (sci_rxd_in(port) == 0) {
907 /* Notify of BREAK */
908 struct sci_port *sci_port = to_sci_port(port);
909
910 if (!sci_port->break_flag) {
911 port->icount.brk++;
912
913 sci_port->break_flag = 1;
914 sci_schedule_break_timer(sci_port);
915
916 /* Do sysrq handling. */
917 if (uart_handle_break(port))
918 return 0;
919
920 dev_dbg(port->dev, "BREAK detected\n");
921
922 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
923 copied++;
924 }
925
926 } else {
927 /* frame error */
928 port->icount.frame++;
929
930 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
931 copied++;
932
933 dev_notice(port->dev, "frame error\n");
934 }
935 }
936
937 if (status & SCxSR_PER(port)) {
938 /* parity error */
939 port->icount.parity++;
940
941 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
942 copied++;
943
944 dev_notice(port->dev, "parity error\n");
945 }
946
947 if (copied)
948 tty_flip_buffer_push(tport);
949
950 return copied;
951 }
952
sci_handle_fifo_overrun(struct uart_port * port)953 static int sci_handle_fifo_overrun(struct uart_port *port)
954 {
955 struct tty_port *tport = &port->state->port;
956 struct sci_port *s = to_sci_port(port);
957 const struct plat_sci_reg *reg;
958 int copied = 0;
959 u16 status;
960
961 reg = sci_getreg(port, s->overrun_reg);
962 if (!reg->size)
963 return 0;
964
965 status = serial_port_in(port, s->overrun_reg);
966 if (status & s->overrun_mask) {
967 status &= ~s->overrun_mask;
968 serial_port_out(port, s->overrun_reg, status);
969
970 port->icount.overrun++;
971
972 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
973 tty_flip_buffer_push(tport);
974
975 dev_dbg(port->dev, "overrun error\n");
976 copied++;
977 }
978
979 return copied;
980 }
981
sci_handle_breaks(struct uart_port * port)982 static int sci_handle_breaks(struct uart_port *port)
983 {
984 int copied = 0;
985 unsigned short status = serial_port_in(port, SCxSR);
986 struct tty_port *tport = &port->state->port;
987 struct sci_port *s = to_sci_port(port);
988
989 if (uart_handle_break(port))
990 return 0;
991
992 if (!s->break_flag && status & SCxSR_BRK(port)) {
993 #if defined(CONFIG_CPU_SH3)
994 /* Debounce break */
995 s->break_flag = 1;
996 #endif
997
998 port->icount.brk++;
999
1000 /* Notify of BREAK */
1001 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1002 copied++;
1003
1004 dev_dbg(port->dev, "BREAK detected\n");
1005 }
1006
1007 if (copied)
1008 tty_flip_buffer_push(tport);
1009
1010 copied += sci_handle_fifo_overrun(port);
1011
1012 return copied;
1013 }
1014
1015 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1016 static void sci_dma_tx_complete(void *arg)
1017 {
1018 struct sci_port *s = arg;
1019 struct uart_port *port = &s->port;
1020 struct circ_buf *xmit = &port->state->xmit;
1021 unsigned long flags;
1022
1023 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1024
1025 spin_lock_irqsave(&port->lock, flags);
1026
1027 xmit->tail += s->tx_dma_len;
1028 xmit->tail &= UART_XMIT_SIZE - 1;
1029
1030 port->icount.tx += s->tx_dma_len;
1031
1032 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1033 uart_write_wakeup(port);
1034
1035 if (!uart_circ_empty(xmit)) {
1036 s->cookie_tx = 0;
1037 schedule_work(&s->work_tx);
1038 } else {
1039 s->cookie_tx = -EINVAL;
1040 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1041 u16 ctrl = serial_port_in(port, SCSCR);
1042 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1043 }
1044 }
1045
1046 spin_unlock_irqrestore(&port->lock, flags);
1047 }
1048
1049 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1050 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1051 {
1052 struct uart_port *port = &s->port;
1053 struct tty_port *tport = &port->state->port;
1054 int copied;
1055
1056 copied = tty_insert_flip_string(tport, buf, count);
1057 if (copied < count) {
1058 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1059 count - copied);
1060 port->icount.buf_overrun++;
1061 }
1062
1063 port->icount.rx += copied;
1064
1065 return copied;
1066 }
1067
sci_dma_rx_find_active(struct sci_port * s)1068 static int sci_dma_rx_find_active(struct sci_port *s)
1069 {
1070 unsigned int i;
1071
1072 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1073 if (s->active_rx == s->cookie_rx[i])
1074 return i;
1075
1076 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1077 s->active_rx);
1078 return -1;
1079 }
1080
sci_rx_dma_release(struct sci_port * s,bool enable_pio)1081 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1082 {
1083 struct dma_chan *chan = s->chan_rx;
1084 struct uart_port *port = &s->port;
1085 unsigned long flags;
1086
1087 spin_lock_irqsave(&port->lock, flags);
1088 s->chan_rx = NULL;
1089 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1090 spin_unlock_irqrestore(&port->lock, flags);
1091 dmaengine_terminate_all(chan);
1092 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1093 sg_dma_address(&s->sg_rx[0]));
1094 dma_release_channel(chan);
1095 if (enable_pio)
1096 sci_start_rx(port);
1097 }
1098
sci_dma_rx_complete(void * arg)1099 static void sci_dma_rx_complete(void *arg)
1100 {
1101 struct sci_port *s = arg;
1102 struct dma_chan *chan = s->chan_rx;
1103 struct uart_port *port = &s->port;
1104 struct dma_async_tx_descriptor *desc;
1105 unsigned long flags;
1106 int active, count = 0;
1107
1108 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1109 s->active_rx);
1110
1111 spin_lock_irqsave(&port->lock, flags);
1112
1113 active = sci_dma_rx_find_active(s);
1114 if (active >= 0)
1115 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1116
1117 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1118
1119 if (count)
1120 tty_flip_buffer_push(&port->state->port);
1121
1122 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1123 DMA_DEV_TO_MEM,
1124 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1125 if (!desc)
1126 goto fail;
1127
1128 desc->callback = sci_dma_rx_complete;
1129 desc->callback_param = s;
1130 s->cookie_rx[active] = dmaengine_submit(desc);
1131 if (dma_submit_error(s->cookie_rx[active]))
1132 goto fail;
1133
1134 s->active_rx = s->cookie_rx[!active];
1135
1136 dma_async_issue_pending(chan);
1137
1138 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1139 __func__, s->cookie_rx[active], active, s->active_rx);
1140 spin_unlock_irqrestore(&port->lock, flags);
1141 return;
1142
1143 fail:
1144 spin_unlock_irqrestore(&port->lock, flags);
1145 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1146 sci_rx_dma_release(s, true);
1147 }
1148
sci_tx_dma_release(struct sci_port * s,bool enable_pio)1149 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1150 {
1151 struct dma_chan *chan = s->chan_tx;
1152 struct uart_port *port = &s->port;
1153 unsigned long flags;
1154
1155 spin_lock_irqsave(&port->lock, flags);
1156 s->chan_tx = NULL;
1157 s->cookie_tx = -EINVAL;
1158 spin_unlock_irqrestore(&port->lock, flags);
1159 dmaengine_terminate_all(chan);
1160 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1161 DMA_TO_DEVICE);
1162 dma_release_channel(chan);
1163 if (enable_pio)
1164 sci_start_tx(port);
1165 }
1166
sci_submit_rx(struct sci_port * s)1167 static void sci_submit_rx(struct sci_port *s)
1168 {
1169 struct dma_chan *chan = s->chan_rx;
1170 int i;
1171
1172 for (i = 0; i < 2; i++) {
1173 struct scatterlist *sg = &s->sg_rx[i];
1174 struct dma_async_tx_descriptor *desc;
1175
1176 desc = dmaengine_prep_slave_sg(chan,
1177 sg, 1, DMA_DEV_TO_MEM,
1178 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1179 if (!desc)
1180 goto fail;
1181
1182 desc->callback = sci_dma_rx_complete;
1183 desc->callback_param = s;
1184 s->cookie_rx[i] = dmaengine_submit(desc);
1185 if (dma_submit_error(s->cookie_rx[i]))
1186 goto fail;
1187
1188 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1189 s->cookie_rx[i], i);
1190 }
1191
1192 s->active_rx = s->cookie_rx[0];
1193
1194 dma_async_issue_pending(chan);
1195 return;
1196
1197 fail:
1198 if (i)
1199 dmaengine_terminate_all(chan);
1200 for (i = 0; i < 2; i++)
1201 s->cookie_rx[i] = -EINVAL;
1202 s->active_rx = -EINVAL;
1203 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1204 sci_rx_dma_release(s, true);
1205 }
1206
work_fn_tx(struct work_struct * work)1207 static void work_fn_tx(struct work_struct *work)
1208 {
1209 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1210 struct dma_async_tx_descriptor *desc;
1211 struct dma_chan *chan = s->chan_tx;
1212 struct uart_port *port = &s->port;
1213 struct circ_buf *xmit = &port->state->xmit;
1214 dma_addr_t buf;
1215
1216 /*
1217 * DMA is idle now.
1218 * Port xmit buffer is already mapped, and it is one page... Just adjust
1219 * offsets and lengths. Since it is a circular buffer, we have to
1220 * transmit till the end, and then the rest. Take the port lock to get a
1221 * consistent xmit buffer state.
1222 */
1223 spin_lock_irq(&port->lock);
1224 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1225 s->tx_dma_len = min_t(unsigned int,
1226 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1227 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1228 spin_unlock_irq(&port->lock);
1229
1230 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1231 DMA_MEM_TO_DEV,
1232 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1233 if (!desc) {
1234 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1235 /* switch to PIO */
1236 sci_tx_dma_release(s, true);
1237 return;
1238 }
1239
1240 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1241 DMA_TO_DEVICE);
1242
1243 spin_lock_irq(&port->lock);
1244 desc->callback = sci_dma_tx_complete;
1245 desc->callback_param = s;
1246 spin_unlock_irq(&port->lock);
1247 s->cookie_tx = dmaengine_submit(desc);
1248 if (dma_submit_error(s->cookie_tx)) {
1249 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1250 /* switch to PIO */
1251 sci_tx_dma_release(s, true);
1252 return;
1253 }
1254
1255 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1256 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1257
1258 dma_async_issue_pending(chan);
1259 }
1260
rx_timer_fn(unsigned long arg)1261 static void rx_timer_fn(unsigned long arg)
1262 {
1263 struct sci_port *s = (struct sci_port *)arg;
1264 struct dma_chan *chan = s->chan_rx;
1265 struct uart_port *port = &s->port;
1266 struct dma_tx_state state;
1267 enum dma_status status;
1268 unsigned long flags;
1269 unsigned int read;
1270 int active, count;
1271 u16 scr;
1272
1273 spin_lock_irqsave(&port->lock, flags);
1274
1275 dev_dbg(port->dev, "DMA Rx timed out\n");
1276
1277 active = sci_dma_rx_find_active(s);
1278 if (active < 0) {
1279 spin_unlock_irqrestore(&port->lock, flags);
1280 return;
1281 }
1282
1283 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1284 if (status == DMA_COMPLETE) {
1285 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1286 s->active_rx, active);
1287 spin_unlock_irqrestore(&port->lock, flags);
1288
1289 /* Let packet complete handler take care of the packet */
1290 return;
1291 }
1292
1293 dmaengine_pause(chan);
1294
1295 /*
1296 * sometimes DMA transfer doesn't stop even if it is stopped and
1297 * data keeps on coming until transaction is complete so check
1298 * for DMA_COMPLETE again
1299 * Let packet complete handler take care of the packet
1300 */
1301 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1302 if (status == DMA_COMPLETE) {
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1305 return;
1306 }
1307
1308 /* Handle incomplete DMA receive */
1309 dmaengine_terminate_all(s->chan_rx);
1310 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1311 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1312 s->active_rx);
1313
1314 if (read) {
1315 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1316 if (count)
1317 tty_flip_buffer_push(&port->state->port);
1318 }
1319
1320 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1321 sci_submit_rx(s);
1322
1323 /* Direct new serial port interrupts back to CPU */
1324 scr = serial_port_in(port, SCSCR);
1325 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1326 scr &= ~SCSCR_RDRQE;
1327 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1328 }
1329 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1330
1331 spin_unlock_irqrestore(&port->lock, flags);
1332 }
1333
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir,unsigned int id)1334 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1335 enum dma_transfer_direction dir,
1336 unsigned int id)
1337 {
1338 dma_cap_mask_t mask;
1339 struct dma_chan *chan;
1340 struct dma_slave_config cfg;
1341 int ret;
1342
1343 dma_cap_zero(mask);
1344 dma_cap_set(DMA_SLAVE, mask);
1345
1346 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1347 (void *)(unsigned long)id, port->dev,
1348 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1349 if (!chan) {
1350 dev_warn(port->dev,
1351 "dma_request_slave_channel_compat failed\n");
1352 return NULL;
1353 }
1354
1355 memset(&cfg, 0, sizeof(cfg));
1356 cfg.direction = dir;
1357 if (dir == DMA_MEM_TO_DEV) {
1358 cfg.dst_addr = port->mapbase +
1359 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1360 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1361 } else {
1362 cfg.src_addr = port->mapbase +
1363 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1364 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1365 }
1366
1367 ret = dmaengine_slave_config(chan, &cfg);
1368 if (ret) {
1369 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1370 dma_release_channel(chan);
1371 return NULL;
1372 }
1373
1374 return chan;
1375 }
1376
sci_request_dma(struct uart_port * port)1377 static void sci_request_dma(struct uart_port *port)
1378 {
1379 struct sci_port *s = to_sci_port(port);
1380 struct dma_chan *chan;
1381
1382 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1383
1384 if (!port->dev->of_node &&
1385 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1386 return;
1387
1388 s->cookie_tx = -EINVAL;
1389 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1390 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1391 if (chan) {
1392 s->chan_tx = chan;
1393 /* UART circular tx buffer is an aligned page. */
1394 s->tx_dma_addr = dma_map_single(chan->device->dev,
1395 port->state->xmit.buf,
1396 UART_XMIT_SIZE,
1397 DMA_TO_DEVICE);
1398 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1399 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1400 dma_release_channel(chan);
1401 s->chan_tx = NULL;
1402 } else {
1403 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1404 __func__, UART_XMIT_SIZE,
1405 port->state->xmit.buf, &s->tx_dma_addr);
1406 }
1407
1408 INIT_WORK(&s->work_tx, work_fn_tx);
1409 }
1410
1411 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1412 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1413 if (chan) {
1414 unsigned int i;
1415 dma_addr_t dma;
1416 void *buf;
1417
1418 s->chan_rx = chan;
1419
1420 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1421 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1422 &dma, GFP_KERNEL);
1423 if (!buf) {
1424 dev_warn(port->dev,
1425 "Failed to allocate Rx dma buffer, using PIO\n");
1426 dma_release_channel(chan);
1427 s->chan_rx = NULL;
1428 return;
1429 }
1430
1431 for (i = 0; i < 2; i++) {
1432 struct scatterlist *sg = &s->sg_rx[i];
1433
1434 sg_init_table(sg, 1);
1435 s->rx_buf[i] = buf;
1436 sg_dma_address(sg) = dma;
1437 sg_dma_len(sg) = s->buf_len_rx;
1438
1439 buf += s->buf_len_rx;
1440 dma += s->buf_len_rx;
1441 }
1442
1443 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1444
1445 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1446 sci_submit_rx(s);
1447 }
1448 }
1449
sci_free_dma(struct uart_port * port)1450 static void sci_free_dma(struct uart_port *port)
1451 {
1452 struct sci_port *s = to_sci_port(port);
1453
1454 if (s->chan_tx)
1455 sci_tx_dma_release(s, false);
1456 if (s->chan_rx)
1457 sci_rx_dma_release(s, false);
1458 }
1459 #else
sci_request_dma(struct uart_port * port)1460 static inline void sci_request_dma(struct uart_port *port)
1461 {
1462 }
1463
sci_free_dma(struct uart_port * port)1464 static inline void sci_free_dma(struct uart_port *port)
1465 {
1466 }
1467 #endif
1468
sci_rx_interrupt(int irq,void * ptr)1469 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1470 {
1471 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1472 struct uart_port *port = ptr;
1473 struct sci_port *s = to_sci_port(port);
1474
1475 if (s->chan_rx) {
1476 u16 scr = serial_port_in(port, SCSCR);
1477 u16 ssr = serial_port_in(port, SCxSR);
1478
1479 /* Disable future Rx interrupts */
1480 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1481 disable_irq_nosync(irq);
1482 scr |= SCSCR_RDRQE;
1483 } else {
1484 scr &= ~SCSCR_RIE;
1485 sci_submit_rx(s);
1486 }
1487 serial_port_out(port, SCSCR, scr);
1488 /* Clear current interrupt */
1489 serial_port_out(port, SCxSR,
1490 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1491 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1492 jiffies, s->rx_timeout);
1493 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1494
1495 return IRQ_HANDLED;
1496 }
1497 #endif
1498
1499 /* I think sci_receive_chars has to be called irrespective
1500 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1501 * to be disabled?
1502 */
1503 sci_receive_chars(ptr);
1504
1505 return IRQ_HANDLED;
1506 }
1507
sci_tx_interrupt(int irq,void * ptr)1508 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1509 {
1510 struct uart_port *port = ptr;
1511 unsigned long flags;
1512
1513 spin_lock_irqsave(&port->lock, flags);
1514 sci_transmit_chars(port);
1515 spin_unlock_irqrestore(&port->lock, flags);
1516
1517 return IRQ_HANDLED;
1518 }
1519
sci_er_interrupt(int irq,void * ptr)1520 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1521 {
1522 struct uart_port *port = ptr;
1523 struct sci_port *s = to_sci_port(port);
1524
1525 /* Handle errors */
1526 if (port->type == PORT_SCI) {
1527 if (sci_handle_errors(port)) {
1528 /* discard character in rx buffer */
1529 serial_port_in(port, SCxSR);
1530 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1531 }
1532 } else {
1533 sci_handle_fifo_overrun(port);
1534 if (!s->chan_rx)
1535 sci_receive_chars(ptr);
1536 }
1537
1538 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1539
1540 /* Kick the transmission */
1541 if (!s->chan_tx)
1542 sci_tx_interrupt(irq, ptr);
1543
1544 return IRQ_HANDLED;
1545 }
1546
sci_br_interrupt(int irq,void * ptr)1547 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1548 {
1549 struct uart_port *port = ptr;
1550
1551 /* Handle BREAKs */
1552 sci_handle_breaks(port);
1553 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1554
1555 return IRQ_HANDLED;
1556 }
1557
sci_mpxed_interrupt(int irq,void * ptr)1558 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1559 {
1560 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1561 struct uart_port *port = ptr;
1562 struct sci_port *s = to_sci_port(port);
1563 irqreturn_t ret = IRQ_NONE;
1564
1565 ssr_status = serial_port_in(port, SCxSR);
1566 scr_status = serial_port_in(port, SCSCR);
1567 if (s->overrun_reg == SCxSR)
1568 orer_status = ssr_status;
1569 else {
1570 if (sci_getreg(port, s->overrun_reg)->size)
1571 orer_status = serial_port_in(port, s->overrun_reg);
1572 }
1573
1574 err_enabled = scr_status & port_rx_irq_mask(port);
1575
1576 /* Tx Interrupt */
1577 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1578 !s->chan_tx)
1579 ret = sci_tx_interrupt(irq, ptr);
1580
1581 /*
1582 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1583 * DR flags
1584 */
1585 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1586 (scr_status & SCSCR_RIE))
1587 ret = sci_rx_interrupt(irq, ptr);
1588
1589 /* Error Interrupt */
1590 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1591 ret = sci_er_interrupt(irq, ptr);
1592
1593 /* Break Interrupt */
1594 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1595 ret = sci_br_interrupt(irq, ptr);
1596
1597 /* Overrun Interrupt */
1598 if (orer_status & s->overrun_mask) {
1599 sci_handle_fifo_overrun(port);
1600 ret = IRQ_HANDLED;
1601 }
1602
1603 return ret;
1604 }
1605
1606 static const struct sci_irq_desc {
1607 const char *desc;
1608 irq_handler_t handler;
1609 } sci_irq_desc[] = {
1610 /*
1611 * Split out handlers, the default case.
1612 */
1613 [SCIx_ERI_IRQ] = {
1614 .desc = "rx err",
1615 .handler = sci_er_interrupt,
1616 },
1617
1618 [SCIx_RXI_IRQ] = {
1619 .desc = "rx full",
1620 .handler = sci_rx_interrupt,
1621 },
1622
1623 [SCIx_TXI_IRQ] = {
1624 .desc = "tx empty",
1625 .handler = sci_tx_interrupt,
1626 },
1627
1628 [SCIx_BRI_IRQ] = {
1629 .desc = "break",
1630 .handler = sci_br_interrupt,
1631 },
1632
1633 /*
1634 * Special muxed handler.
1635 */
1636 [SCIx_MUX_IRQ] = {
1637 .desc = "mux",
1638 .handler = sci_mpxed_interrupt,
1639 },
1640 };
1641
sci_request_irq(struct sci_port * port)1642 static int sci_request_irq(struct sci_port *port)
1643 {
1644 struct uart_port *up = &port->port;
1645 int i, j, ret = 0;
1646
1647 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1648 const struct sci_irq_desc *desc;
1649 int irq;
1650
1651 if (SCIx_IRQ_IS_MUXED(port)) {
1652 i = SCIx_MUX_IRQ;
1653 irq = up->irq;
1654 } else {
1655 irq = port->irqs[i];
1656
1657 /*
1658 * Certain port types won't support all of the
1659 * available interrupt sources.
1660 */
1661 if (unlikely(irq < 0))
1662 continue;
1663 }
1664
1665 desc = sci_irq_desc + i;
1666 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1667 dev_name(up->dev), desc->desc);
1668 if (!port->irqstr[j])
1669 goto out_nomem;
1670
1671 ret = request_irq(irq, desc->handler, up->irqflags,
1672 port->irqstr[j], port);
1673 if (unlikely(ret)) {
1674 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1675 goto out_noirq;
1676 }
1677 }
1678
1679 return 0;
1680
1681 out_noirq:
1682 while (--i >= 0)
1683 free_irq(port->irqs[i], port);
1684
1685 out_nomem:
1686 while (--j >= 0)
1687 kfree(port->irqstr[j]);
1688
1689 return ret;
1690 }
1691
sci_free_irq(struct sci_port * port)1692 static void sci_free_irq(struct sci_port *port)
1693 {
1694 int i;
1695
1696 /*
1697 * Intentionally in reverse order so we iterate over the muxed
1698 * IRQ first.
1699 */
1700 for (i = 0; i < SCIx_NR_IRQS; i++) {
1701 int irq = port->irqs[i];
1702
1703 /*
1704 * Certain port types won't support all of the available
1705 * interrupt sources.
1706 */
1707 if (unlikely(irq < 0))
1708 continue;
1709
1710 free_irq(port->irqs[i], port);
1711 kfree(port->irqstr[i]);
1712
1713 if (SCIx_IRQ_IS_MUXED(port)) {
1714 /* If there's only one IRQ, we're done. */
1715 return;
1716 }
1717 }
1718 }
1719
sci_tx_empty(struct uart_port * port)1720 static unsigned int sci_tx_empty(struct uart_port *port)
1721 {
1722 unsigned short status = serial_port_in(port, SCxSR);
1723 unsigned short in_tx_fifo = sci_txfill(port);
1724
1725 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1726 }
1727
1728 /*
1729 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1730 * CTS/RTS is supported in hardware by at least one port and controlled
1731 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1732 * handled via the ->init_pins() op, which is a bit of a one-way street,
1733 * lacking any ability to defer pin control -- this will later be
1734 * converted over to the GPIO framework).
1735 *
1736 * Other modes (such as loopback) are supported generically on certain
1737 * port types, but not others. For these it's sufficient to test for the
1738 * existence of the support register and simply ignore the port type.
1739 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)1740 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1741 {
1742 if (mctrl & TIOCM_LOOP) {
1743 const struct plat_sci_reg *reg;
1744
1745 /*
1746 * Standard loopback mode for SCFCR ports.
1747 */
1748 reg = sci_getreg(port, SCFCR);
1749 if (reg->size)
1750 serial_port_out(port, SCFCR,
1751 serial_port_in(port, SCFCR) |
1752 SCFCR_LOOP);
1753 }
1754 }
1755
sci_get_mctrl(struct uart_port * port)1756 static unsigned int sci_get_mctrl(struct uart_port *port)
1757 {
1758 /*
1759 * CTS/RTS is handled in hardware when supported, while nothing
1760 * else is wired up. Keep it simple and simply assert DSR/CAR.
1761 */
1762 return TIOCM_DSR | TIOCM_CAR;
1763 }
1764
sci_break_ctl(struct uart_port * port,int break_state)1765 static void sci_break_ctl(struct uart_port *port, int break_state)
1766 {
1767 struct sci_port *s = to_sci_port(port);
1768 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1769 unsigned short scscr, scsptr;
1770
1771 /* check wheter the port has SCSPTR */
1772 if (!reg->size) {
1773 /*
1774 * Not supported by hardware. Most parts couple break and rx
1775 * interrupts together, with break detection always enabled.
1776 */
1777 return;
1778 }
1779
1780 scsptr = serial_port_in(port, SCSPTR);
1781 scscr = serial_port_in(port, SCSCR);
1782
1783 if (break_state == -1) {
1784 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1785 scscr &= ~SCSCR_TE;
1786 } else {
1787 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1788 scscr |= SCSCR_TE;
1789 }
1790
1791 serial_port_out(port, SCSPTR, scsptr);
1792 serial_port_out(port, SCSCR, scscr);
1793 }
1794
sci_startup(struct uart_port * port)1795 static int sci_startup(struct uart_port *port)
1796 {
1797 struct sci_port *s = to_sci_port(port);
1798 unsigned long flags;
1799 int ret;
1800
1801 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1802
1803 ret = sci_request_irq(s);
1804 if (unlikely(ret < 0))
1805 return ret;
1806
1807 sci_request_dma(port);
1808
1809 spin_lock_irqsave(&port->lock, flags);
1810 sci_start_tx(port);
1811 sci_start_rx(port);
1812 spin_unlock_irqrestore(&port->lock, flags);
1813
1814 return 0;
1815 }
1816
sci_shutdown(struct uart_port * port)1817 static void sci_shutdown(struct uart_port *port)
1818 {
1819 struct sci_port *s = to_sci_port(port);
1820 unsigned long flags;
1821
1822 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1823
1824 spin_lock_irqsave(&port->lock, flags);
1825 sci_stop_rx(port);
1826 sci_stop_tx(port);
1827 spin_unlock_irqrestore(&port->lock, flags);
1828
1829 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1830 if (s->chan_rx) {
1831 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1832 port->line);
1833 del_timer_sync(&s->rx_timer);
1834 }
1835 #endif
1836
1837 sci_free_dma(port);
1838 sci_free_irq(s);
1839 }
1840
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned long freq)1841 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1842 unsigned long freq)
1843 {
1844 if (s->sampling_rate)
1845 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1846
1847 /* Warn, but use a safe default */
1848 WARN_ON(1);
1849
1850 return ((freq + 16 * bps) / (32 * bps) - 1);
1851 }
1852
1853 /* calculate frame length from SMR */
sci_baud_calc_frame_len(unsigned int smr_val)1854 static int sci_baud_calc_frame_len(unsigned int smr_val)
1855 {
1856 int len = 10;
1857
1858 if (smr_val & SCSMR_CHR)
1859 len--;
1860 if (smr_val & SCSMR_PE)
1861 len++;
1862 if (smr_val & SCSMR_STOP)
1863 len++;
1864
1865 return len;
1866 }
1867
1868
1869 /* calculate sample rate, BRR, and clock select for HSCIF */
sci_baud_calc_hscif(unsigned int bps,unsigned long freq,int * brr,unsigned int * srr,unsigned int * cks,int frame_len)1870 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1871 int *brr, unsigned int *srr,
1872 unsigned int *cks, int frame_len)
1873 {
1874 int sr, c, br, err, recv_margin;
1875 int min_err = 1000; /* 100% */
1876 int recv_max_margin = 0;
1877
1878 /* Find the combination of sample rate and clock select with the
1879 smallest deviation from the desired baud rate. */
1880 for (sr = 8; sr <= 32; sr++) {
1881 for (c = 0; c <= 3; c++) {
1882 /* integerized formulas from HSCIF documentation */
1883 br = DIV_ROUND_CLOSEST(freq, (sr *
1884 (1 << (2 * c + 1)) * bps)) - 1;
1885 br = clamp(br, 0, 255);
1886 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1887 (1 << (2 * c + 1)) / 1000)) -
1888 1000;
1889 /* Calc recv margin
1890 * M: Receive margin (%)
1891 * N: Ratio of bit rate to clock (N = sampling rate)
1892 * D: Clock duty (D = 0 to 1.0)
1893 * L: Frame length (L = 9 to 12)
1894 * F: Absolute value of clock frequency deviation
1895 *
1896 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1897 * (|D - 0.5| / N * (1 + F))|
1898 * NOTE: Usually, treat D for 0.5, F is 0 by this
1899 * calculation.
1900 */
1901 recv_margin = abs((500 -
1902 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1903 if (abs(min_err) > abs(err)) {
1904 min_err = err;
1905 recv_max_margin = recv_margin;
1906 } else if ((min_err == err) &&
1907 (recv_margin > recv_max_margin))
1908 recv_max_margin = recv_margin;
1909 else
1910 continue;
1911
1912 *brr = br;
1913 *srr = sr - 1;
1914 *cks = c;
1915 }
1916 }
1917
1918 if (min_err == 1000) {
1919 WARN_ON(1);
1920 /* use defaults */
1921 *brr = 255;
1922 *srr = 15;
1923 *cks = 0;
1924 }
1925 }
1926
sci_reset(struct uart_port * port)1927 static void sci_reset(struct uart_port *port)
1928 {
1929 const struct plat_sci_reg *reg;
1930 unsigned int status;
1931
1932 do {
1933 status = serial_port_in(port, SCxSR);
1934 } while (!(status & SCxSR_TEND(port)));
1935
1936 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1937
1938 reg = sci_getreg(port, SCFCR);
1939 if (reg->size)
1940 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1941 }
1942
sci_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1943 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1944 struct ktermios *old)
1945 {
1946 struct sci_port *s = to_sci_port(port);
1947 const struct plat_sci_reg *reg;
1948 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1949 int t = -1;
1950 unsigned int srr = 15;
1951
1952 if ((termios->c_cflag & CSIZE) == CS7)
1953 smr_val |= SCSMR_CHR;
1954 if (termios->c_cflag & PARENB)
1955 smr_val |= SCSMR_PE;
1956 if (termios->c_cflag & PARODD)
1957 smr_val |= SCSMR_PE | SCSMR_ODD;
1958 if (termios->c_cflag & CSTOPB)
1959 smr_val |= SCSMR_STOP;
1960
1961 /*
1962 * earlyprintk comes here early on with port->uartclk set to zero.
1963 * the clock framework is not up and running at this point so here
1964 * we assume that 115200 is the maximum baud rate. please note that
1965 * the baud rate is not programmed during earlyprintk - it is assumed
1966 * that the previous boot loader has enabled required clocks and
1967 * setup the baud rate generator hardware for us already.
1968 */
1969 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1970
1971 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1972 if (likely(baud && port->uartclk)) {
1973 if (s->cfg->type == PORT_HSCIF) {
1974 int frame_len = sci_baud_calc_frame_len(smr_val);
1975 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1976 &cks, frame_len);
1977 } else {
1978 t = sci_scbrr_calc(s, baud, port->uartclk);
1979 for (cks = 0; t >= 256 && cks <= 3; cks++)
1980 t >>= 2;
1981 }
1982 }
1983
1984 sci_port_enable(s);
1985
1986 sci_reset(port);
1987
1988 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1989
1990 uart_update_timeout(port, termios->c_cflag, baud);
1991
1992 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1993 __func__, smr_val, cks, t, s->cfg->scscr);
1994
1995 if (t >= 0) {
1996 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1997 serial_port_out(port, SCBRR, t);
1998 reg = sci_getreg(port, HSSRR);
1999 if (reg->size)
2000 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2001 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
2002 } else
2003 serial_port_out(port, SCSMR, smr_val);
2004
2005 sci_init_pins(port, termios->c_cflag);
2006
2007 reg = sci_getreg(port, SCFCR);
2008 if (reg->size) {
2009 unsigned short ctrl = serial_port_in(port, SCFCR);
2010
2011 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2012 if (termios->c_cflag & CRTSCTS)
2013 ctrl |= SCFCR_MCE;
2014 else
2015 ctrl &= ~SCFCR_MCE;
2016 }
2017
2018 /*
2019 * As we've done a sci_reset() above, ensure we don't
2020 * interfere with the FIFOs while toggling MCE. As the
2021 * reset values could still be set, simply mask them out.
2022 */
2023 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2024
2025 serial_port_out(port, SCFCR, ctrl);
2026 }
2027
2028 serial_port_out(port, SCSCR, s->cfg->scscr);
2029
2030 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2031 /*
2032 * Calculate delay for 2 DMA buffers (4 FIFO).
2033 * See serial_core.c::uart_update_timeout().
2034 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2035 * function calculates 1 jiffie for the data plus 5 jiffies for the
2036 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2037 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2038 * value obtained by this formula is too small. Therefore, if the value
2039 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2040 */
2041 if (s->chan_rx) {
2042 unsigned int bits;
2043
2044 /* byte size and parity */
2045 switch (termios->c_cflag & CSIZE) {
2046 case CS5:
2047 bits = 7;
2048 break;
2049 case CS6:
2050 bits = 8;
2051 break;
2052 case CS7:
2053 bits = 9;
2054 break;
2055 default:
2056 bits = 10;
2057 break;
2058 }
2059
2060 if (termios->c_cflag & CSTOPB)
2061 bits++;
2062 if (termios->c_cflag & PARENB)
2063 bits++;
2064 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2065 (baud / 10), 10);
2066 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2067 s->rx_timeout * 1000 / HZ, port->timeout);
2068 if (s->rx_timeout < msecs_to_jiffies(20))
2069 s->rx_timeout = msecs_to_jiffies(20);
2070 }
2071 #endif
2072
2073 if ((termios->c_cflag & CREAD) != 0)
2074 sci_start_rx(port);
2075
2076 sci_port_disable(s);
2077 }
2078
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2079 static void sci_pm(struct uart_port *port, unsigned int state,
2080 unsigned int oldstate)
2081 {
2082 struct sci_port *sci_port = to_sci_port(port);
2083
2084 switch (state) {
2085 case UART_PM_STATE_OFF:
2086 sci_port_disable(sci_port);
2087 break;
2088 default:
2089 sci_port_enable(sci_port);
2090 break;
2091 }
2092 }
2093
sci_type(struct uart_port * port)2094 static const char *sci_type(struct uart_port *port)
2095 {
2096 switch (port->type) {
2097 case PORT_IRDA:
2098 return "irda";
2099 case PORT_SCI:
2100 return "sci";
2101 case PORT_SCIF:
2102 return "scif";
2103 case PORT_SCIFA:
2104 return "scifa";
2105 case PORT_SCIFB:
2106 return "scifb";
2107 case PORT_HSCIF:
2108 return "hscif";
2109 }
2110
2111 return NULL;
2112 }
2113
sci_remap_port(struct uart_port * port)2114 static int sci_remap_port(struct uart_port *port)
2115 {
2116 struct sci_port *sport = to_sci_port(port);
2117
2118 /*
2119 * Nothing to do if there's already an established membase.
2120 */
2121 if (port->membase)
2122 return 0;
2123
2124 if (port->flags & UPF_IOREMAP) {
2125 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2126 if (unlikely(!port->membase)) {
2127 dev_err(port->dev, "can't remap port#%d\n", port->line);
2128 return -ENXIO;
2129 }
2130 } else {
2131 /*
2132 * For the simple (and majority of) cases where we don't
2133 * need to do any remapping, just cast the cookie
2134 * directly.
2135 */
2136 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2137 }
2138
2139 return 0;
2140 }
2141
sci_release_port(struct uart_port * port)2142 static void sci_release_port(struct uart_port *port)
2143 {
2144 struct sci_port *sport = to_sci_port(port);
2145
2146 if (port->flags & UPF_IOREMAP) {
2147 iounmap(port->membase);
2148 port->membase = NULL;
2149 }
2150
2151 release_mem_region(port->mapbase, sport->reg_size);
2152 }
2153
sci_request_port(struct uart_port * port)2154 static int sci_request_port(struct uart_port *port)
2155 {
2156 struct resource *res;
2157 struct sci_port *sport = to_sci_port(port);
2158 int ret;
2159
2160 res = request_mem_region(port->mapbase, sport->reg_size,
2161 dev_name(port->dev));
2162 if (unlikely(res == NULL)) {
2163 dev_err(port->dev, "request_mem_region failed.");
2164 return -EBUSY;
2165 }
2166
2167 ret = sci_remap_port(port);
2168 if (unlikely(ret != 0)) {
2169 release_resource(res);
2170 return ret;
2171 }
2172
2173 return 0;
2174 }
2175
sci_config_port(struct uart_port * port,int flags)2176 static void sci_config_port(struct uart_port *port, int flags)
2177 {
2178 if (flags & UART_CONFIG_TYPE) {
2179 struct sci_port *sport = to_sci_port(port);
2180
2181 port->type = sport->cfg->type;
2182 sci_request_port(port);
2183 }
2184 }
2185
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2186 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2187 {
2188 if (ser->baud_base < 2400)
2189 /* No paper tape reader for Mitch.. */
2190 return -EINVAL;
2191
2192 return 0;
2193 }
2194
2195 static struct uart_ops sci_uart_ops = {
2196 .tx_empty = sci_tx_empty,
2197 .set_mctrl = sci_set_mctrl,
2198 .get_mctrl = sci_get_mctrl,
2199 .start_tx = sci_start_tx,
2200 .stop_tx = sci_stop_tx,
2201 .stop_rx = sci_stop_rx,
2202 .break_ctl = sci_break_ctl,
2203 .startup = sci_startup,
2204 .shutdown = sci_shutdown,
2205 .set_termios = sci_set_termios,
2206 .pm = sci_pm,
2207 .type = sci_type,
2208 .release_port = sci_release_port,
2209 .request_port = sci_request_port,
2210 .config_port = sci_config_port,
2211 .verify_port = sci_verify_port,
2212 #ifdef CONFIG_CONSOLE_POLL
2213 .poll_get_char = sci_poll_get_char,
2214 .poll_put_char = sci_poll_put_char,
2215 #endif
2216 };
2217
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,struct plat_sci_port * p,bool early)2218 static int sci_init_single(struct platform_device *dev,
2219 struct sci_port *sci_port, unsigned int index,
2220 struct plat_sci_port *p, bool early)
2221 {
2222 struct uart_port *port = &sci_port->port;
2223 const struct resource *res;
2224 unsigned int i;
2225 int ret;
2226
2227 sci_port->cfg = p;
2228
2229 port->ops = &sci_uart_ops;
2230 port->iotype = UPIO_MEM;
2231 port->line = index;
2232
2233 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2234 if (res == NULL)
2235 return -ENOMEM;
2236
2237 port->mapbase = res->start;
2238 sci_port->reg_size = resource_size(res);
2239
2240 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2241 sci_port->irqs[i] = platform_get_irq(dev, i);
2242
2243 /* The SCI generates several interrupts. They can be muxed together or
2244 * connected to different interrupt lines. In the muxed case only one
2245 * interrupt resource is specified. In the non-muxed case three or four
2246 * interrupt resources are specified, as the BRI interrupt is optional.
2247 */
2248 if (sci_port->irqs[0] < 0)
2249 return -ENXIO;
2250
2251 if (sci_port->irqs[1] < 0) {
2252 sci_port->irqs[1] = sci_port->irqs[0];
2253 sci_port->irqs[2] = sci_port->irqs[0];
2254 sci_port->irqs[3] = sci_port->irqs[0];
2255 }
2256
2257 if (p->regtype == SCIx_PROBE_REGTYPE) {
2258 ret = sci_probe_regmap(p);
2259 if (unlikely(ret))
2260 return ret;
2261 }
2262
2263 switch (p->type) {
2264 case PORT_SCIFB:
2265 port->fifosize = 256;
2266 sci_port->overrun_reg = SCxSR;
2267 sci_port->overrun_mask = SCIFA_ORER;
2268 sci_port->sampling_rate = 16;
2269 break;
2270 case PORT_HSCIF:
2271 port->fifosize = 128;
2272 sci_port->overrun_reg = SCLSR;
2273 sci_port->overrun_mask = SCLSR_ORER;
2274 sci_port->sampling_rate = 0;
2275 break;
2276 case PORT_SCIFA:
2277 port->fifosize = 64;
2278 sci_port->overrun_reg = SCxSR;
2279 sci_port->overrun_mask = SCIFA_ORER;
2280 sci_port->sampling_rate = 16;
2281 break;
2282 case PORT_SCIF:
2283 port->fifosize = 16;
2284 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2285 sci_port->overrun_reg = SCxSR;
2286 sci_port->overrun_mask = SCIFA_ORER;
2287 sci_port->sampling_rate = 16;
2288 } else {
2289 sci_port->overrun_reg = SCLSR;
2290 sci_port->overrun_mask = SCLSR_ORER;
2291 sci_port->sampling_rate = 32;
2292 }
2293 break;
2294 default:
2295 port->fifosize = 1;
2296 sci_port->overrun_reg = SCxSR;
2297 sci_port->overrun_mask = SCI_ORER;
2298 sci_port->sampling_rate = 32;
2299 break;
2300 }
2301
2302 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2303 * match the SoC datasheet, this should be investigated. Let platform
2304 * data override the sampling rate for now.
2305 */
2306 if (p->sampling_rate)
2307 sci_port->sampling_rate = p->sampling_rate;
2308
2309 if (!early) {
2310 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2311 if (IS_ERR(sci_port->iclk)) {
2312 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2313 if (IS_ERR(sci_port->iclk)) {
2314 dev_err(&dev->dev, "can't get iclk\n");
2315 return PTR_ERR(sci_port->iclk);
2316 }
2317 }
2318
2319 /*
2320 * The function clock is optional, ignore it if we can't
2321 * find it.
2322 */
2323 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2324 if (IS_ERR(sci_port->fclk))
2325 sci_port->fclk = NULL;
2326
2327 port->dev = &dev->dev;
2328
2329 pm_runtime_enable(&dev->dev);
2330 }
2331
2332 sci_port->break_timer.data = (unsigned long)sci_port;
2333 sci_port->break_timer.function = sci_break_timer;
2334 init_timer(&sci_port->break_timer);
2335
2336 /*
2337 * Establish some sensible defaults for the error detection.
2338 */
2339 if (p->type == PORT_SCI) {
2340 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2341 sci_port->error_clear = SCI_ERROR_CLEAR;
2342 } else {
2343 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2344 sci_port->error_clear = SCIF_ERROR_CLEAR;
2345 }
2346
2347 /*
2348 * Make the error mask inclusive of overrun detection, if
2349 * supported.
2350 */
2351 if (sci_port->overrun_reg == SCxSR) {
2352 sci_port->error_mask |= sci_port->overrun_mask;
2353 sci_port->error_clear &= ~sci_port->overrun_mask;
2354 }
2355
2356 port->type = p->type;
2357 port->flags = UPF_FIXED_PORT | p->flags;
2358 port->regshift = p->regshift;
2359
2360 /*
2361 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2362 * for the multi-IRQ ports, which is where we are primarily
2363 * concerned with the shutdown path synchronization.
2364 *
2365 * For the muxed case there's nothing more to do.
2366 */
2367 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2368 port->irqflags = 0;
2369
2370 port->serial_in = sci_serial_in;
2371 port->serial_out = sci_serial_out;
2372
2373 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2374 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2375 p->dma_slave_tx, p->dma_slave_rx);
2376
2377 return 0;
2378 }
2379
sci_cleanup_single(struct sci_port * port)2380 static void sci_cleanup_single(struct sci_port *port)
2381 {
2382 clk_put(port->iclk);
2383 clk_put(port->fclk);
2384
2385 pm_runtime_disable(port->port.dev);
2386 }
2387
2388 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
serial_console_putchar(struct uart_port * port,int ch)2389 static void serial_console_putchar(struct uart_port *port, int ch)
2390 {
2391 sci_poll_put_char(port, ch);
2392 }
2393
2394 /*
2395 * Print a string to the serial port trying not to disturb
2396 * any possible real use of the port...
2397 */
serial_console_write(struct console * co,const char * s,unsigned count)2398 static void serial_console_write(struct console *co, const char *s,
2399 unsigned count)
2400 {
2401 struct sci_port *sci_port = &sci_ports[co->index];
2402 struct uart_port *port = &sci_port->port;
2403 unsigned short bits, ctrl;
2404 unsigned long flags;
2405 int locked = 1;
2406
2407 local_irq_save(flags);
2408 if (port->sysrq)
2409 locked = 0;
2410 else if (oops_in_progress)
2411 locked = spin_trylock(&port->lock);
2412 else
2413 spin_lock(&port->lock);
2414
2415 /* first save the SCSCR then disable the interrupts */
2416 ctrl = serial_port_in(port, SCSCR);
2417 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2418
2419 uart_console_write(port, s, count, serial_console_putchar);
2420
2421 /* wait until fifo is empty and last bit has been transmitted */
2422 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2423 while ((serial_port_in(port, SCxSR) & bits) != bits)
2424 cpu_relax();
2425
2426 /* restore the SCSCR */
2427 serial_port_out(port, SCSCR, ctrl);
2428
2429 if (locked)
2430 spin_unlock(&port->lock);
2431 local_irq_restore(flags);
2432 }
2433
serial_console_setup(struct console * co,char * options)2434 static int serial_console_setup(struct console *co, char *options)
2435 {
2436 struct sci_port *sci_port;
2437 struct uart_port *port;
2438 int baud = 115200;
2439 int bits = 8;
2440 int parity = 'n';
2441 int flow = 'n';
2442 int ret;
2443
2444 /*
2445 * Refuse to handle any bogus ports.
2446 */
2447 if (co->index < 0 || co->index >= SCI_NPORTS)
2448 return -ENODEV;
2449
2450 sci_port = &sci_ports[co->index];
2451 port = &sci_port->port;
2452
2453 /*
2454 * Refuse to handle uninitialized ports.
2455 */
2456 if (!port->ops)
2457 return -ENODEV;
2458
2459 ret = sci_remap_port(port);
2460 if (unlikely(ret != 0))
2461 return ret;
2462
2463 if (options)
2464 uart_parse_options(options, &baud, &parity, &bits, &flow);
2465
2466 return uart_set_options(port, co, baud, parity, bits, flow);
2467 }
2468
2469 static struct console serial_console = {
2470 .name = "ttySC",
2471 .device = uart_console_device,
2472 .write = serial_console_write,
2473 .setup = serial_console_setup,
2474 .flags = CON_PRINTBUFFER,
2475 .index = -1,
2476 .data = &sci_uart_driver,
2477 };
2478
2479 static struct console early_serial_console = {
2480 .name = "early_ttySC",
2481 .write = serial_console_write,
2482 .flags = CON_PRINTBUFFER,
2483 .index = -1,
2484 };
2485
2486 static char early_serial_buf[32];
2487
sci_probe_earlyprintk(struct platform_device * pdev)2488 static int sci_probe_earlyprintk(struct platform_device *pdev)
2489 {
2490 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2491
2492 if (early_serial_console.data)
2493 return -EEXIST;
2494
2495 early_serial_console.index = pdev->id;
2496
2497 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2498
2499 serial_console_setup(&early_serial_console, early_serial_buf);
2500
2501 if (!strstr(early_serial_buf, "keep"))
2502 early_serial_console.flags |= CON_BOOT;
2503
2504 register_console(&early_serial_console);
2505 return 0;
2506 }
2507
2508 #define SCI_CONSOLE (&serial_console)
2509
2510 #else
sci_probe_earlyprintk(struct platform_device * pdev)2511 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2512 {
2513 return -EINVAL;
2514 }
2515
2516 #define SCI_CONSOLE NULL
2517
2518 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2519
2520 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2521
2522 static struct uart_driver sci_uart_driver = {
2523 .owner = THIS_MODULE,
2524 .driver_name = "sci",
2525 .dev_name = "ttySC",
2526 .major = SCI_MAJOR,
2527 .minor = SCI_MINOR_START,
2528 .nr = SCI_NPORTS,
2529 .cons = SCI_CONSOLE,
2530 };
2531
sci_remove(struct platform_device * dev)2532 static int sci_remove(struct platform_device *dev)
2533 {
2534 struct sci_port *port = platform_get_drvdata(dev);
2535
2536 uart_remove_one_port(&sci_uart_driver, &port->port);
2537
2538 sci_cleanup_single(port);
2539
2540 return 0;
2541 }
2542
2543 struct sci_port_info {
2544 unsigned int type;
2545 unsigned int regtype;
2546 };
2547
2548 static const struct of_device_id of_sci_match[] = {
2549 {
2550 .compatible = "renesas,scif",
2551 .data = &(const struct sci_port_info) {
2552 .type = PORT_SCIF,
2553 .regtype = SCIx_SH4_SCIF_REGTYPE,
2554 },
2555 }, {
2556 .compatible = "renesas,scifa",
2557 .data = &(const struct sci_port_info) {
2558 .type = PORT_SCIFA,
2559 .regtype = SCIx_SCIFA_REGTYPE,
2560 },
2561 }, {
2562 .compatible = "renesas,scifb",
2563 .data = &(const struct sci_port_info) {
2564 .type = PORT_SCIFB,
2565 .regtype = SCIx_SCIFB_REGTYPE,
2566 },
2567 }, {
2568 .compatible = "renesas,hscif",
2569 .data = &(const struct sci_port_info) {
2570 .type = PORT_HSCIF,
2571 .regtype = SCIx_HSCIF_REGTYPE,
2572 },
2573 }, {
2574 .compatible = "renesas,sci",
2575 .data = &(const struct sci_port_info) {
2576 .type = PORT_SCI,
2577 .regtype = SCIx_SCI_REGTYPE,
2578 },
2579 }, {
2580 /* Terminator */
2581 },
2582 };
2583 MODULE_DEVICE_TABLE(of, of_sci_match);
2584
2585 static struct plat_sci_port *
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)2586 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2587 {
2588 struct device_node *np = pdev->dev.of_node;
2589 const struct of_device_id *match;
2590 const struct sci_port_info *info;
2591 struct plat_sci_port *p;
2592 int id;
2593
2594 if (!IS_ENABLED(CONFIG_OF) || !np)
2595 return NULL;
2596
2597 match = of_match_node(of_sci_match, pdev->dev.of_node);
2598 if (!match)
2599 return NULL;
2600
2601 info = match->data;
2602
2603 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2604 if (!p)
2605 return NULL;
2606
2607 /* Get the line number for the aliases node. */
2608 id = of_alias_get_id(np, "serial");
2609 if (id < 0) {
2610 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2611 return NULL;
2612 }
2613
2614 *dev_id = id;
2615
2616 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2617 p->type = info->type;
2618 p->regtype = info->regtype;
2619 p->scscr = SCSCR_RE | SCSCR_TE;
2620
2621 return p;
2622 }
2623
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport)2624 static int sci_probe_single(struct platform_device *dev,
2625 unsigned int index,
2626 struct plat_sci_port *p,
2627 struct sci_port *sciport)
2628 {
2629 int ret;
2630
2631 /* Sanity check */
2632 if (unlikely(index >= SCI_NPORTS)) {
2633 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2634 index+1, SCI_NPORTS);
2635 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2636 return -EINVAL;
2637 }
2638
2639 ret = sci_init_single(dev, sciport, index, p, false);
2640 if (ret)
2641 return ret;
2642
2643 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2644 if (ret) {
2645 sci_cleanup_single(sciport);
2646 return ret;
2647 }
2648
2649 return 0;
2650 }
2651
sci_probe(struct platform_device * dev)2652 static int sci_probe(struct platform_device *dev)
2653 {
2654 struct plat_sci_port *p;
2655 struct sci_port *sp;
2656 unsigned int dev_id;
2657 int ret;
2658
2659 /*
2660 * If we've come here via earlyprintk initialization, head off to
2661 * the special early probe. We don't have sufficient device state
2662 * to make it beyond this yet.
2663 */
2664 if (is_early_platform_device(dev))
2665 return sci_probe_earlyprintk(dev);
2666
2667 if (dev->dev.of_node) {
2668 p = sci_parse_dt(dev, &dev_id);
2669 if (p == NULL)
2670 return -EINVAL;
2671 } else {
2672 p = dev->dev.platform_data;
2673 if (p == NULL) {
2674 dev_err(&dev->dev, "no platform data supplied\n");
2675 return -EINVAL;
2676 }
2677
2678 dev_id = dev->id;
2679 }
2680
2681 sp = &sci_ports[dev_id];
2682 platform_set_drvdata(dev, sp);
2683
2684 ret = sci_probe_single(dev, dev_id, p, sp);
2685 if (ret)
2686 return ret;
2687
2688 #ifdef CONFIG_SH_STANDARD_BIOS
2689 sh_bios_gdb_detach();
2690 #endif
2691
2692 return 0;
2693 }
2694
sci_suspend(struct device * dev)2695 static __maybe_unused int sci_suspend(struct device *dev)
2696 {
2697 struct sci_port *sport = dev_get_drvdata(dev);
2698
2699 if (sport)
2700 uart_suspend_port(&sci_uart_driver, &sport->port);
2701
2702 return 0;
2703 }
2704
sci_resume(struct device * dev)2705 static __maybe_unused int sci_resume(struct device *dev)
2706 {
2707 struct sci_port *sport = dev_get_drvdata(dev);
2708
2709 if (sport)
2710 uart_resume_port(&sci_uart_driver, &sport->port);
2711
2712 return 0;
2713 }
2714
2715 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2716
2717 static struct platform_driver sci_driver = {
2718 .probe = sci_probe,
2719 .remove = sci_remove,
2720 .driver = {
2721 .name = "sh-sci",
2722 .pm = &sci_dev_pm_ops,
2723 .of_match_table = of_match_ptr(of_sci_match),
2724 },
2725 };
2726
sci_init(void)2727 static int __init sci_init(void)
2728 {
2729 int ret;
2730
2731 pr_info("%s\n", banner);
2732
2733 ret = uart_register_driver(&sci_uart_driver);
2734 if (likely(ret == 0)) {
2735 ret = platform_driver_register(&sci_driver);
2736 if (unlikely(ret))
2737 uart_unregister_driver(&sci_uart_driver);
2738 }
2739
2740 return ret;
2741 }
2742
sci_exit(void)2743 static void __exit sci_exit(void)
2744 {
2745 platform_driver_unregister(&sci_driver);
2746 uart_unregister_driver(&sci_uart_driver);
2747 }
2748
2749 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2750 early_platform_init_buffer("earlyprintk", &sci_driver,
2751 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2752 #endif
2753 module_init(sci_init);
2754 module_exit(sci_exit);
2755
2756 MODULE_LICENSE("GPL");
2757 MODULE_ALIAS("platform:sh-sci");
2758 MODULE_AUTHOR("Paul Mundt");
2759 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
2760