1 /*
2 * 8250-core based driver for the OMAP internal UART
3 *
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
5 *
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
7 *
8 */
9
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/delay.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/console.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/dma-mapping.h>
28
29 #include "8250.h"
30
31 #define DEFAULT_CLK_SPEED 48000000
32
33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
35 #define OMAP_DMA_TX_KICK (1 << 2)
36 /*
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
39 */
40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
41
42 #define OMAP_UART_FCR_RX_TRIG 6
43 #define OMAP_UART_FCR_TX_TRIG 4
44
45 /* SCR register bitmasks */
46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
52
53 /* MVR register bitmasks */
54 #define OMAP_UART_MVR_SCHEME_SHIFT 30
55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58 #define OMAP_UART_MVR_MAJ_MASK 0x700
59 #define OMAP_UART_MVR_MAJ_SHIFT 8
60 #define OMAP_UART_MVR_MIN_MASK 0x3f
61
62 /* SYSC register bitmasks */
63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
64
65 /* SYSS register bitmasks */
66 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
67
68 #define UART_TI752_TLR_TX 0
69 #define UART_TI752_TLR_RX 4
70
71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72 #define TRIGGER_FCR_MASK(x) (x & 3)
73
74 /* Enable XON/XOFF flow control on output */
75 #define OMAP_UART_SW_TX 0x08
76 /* Enable XON/XOFF flow control on input */
77 #define OMAP_UART_SW_RX 0x02
78
79 #define OMAP_UART_WER_MOD_WKUP 0x7f
80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
81
82 #define TX_TRIGGER 1
83 #define RX_TRIGGER 48
84
85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
87
88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
89
90 #define OMAP_UART_REV_46 0x0406
91 #define OMAP_UART_REV_52 0x0502
92 #define OMAP_UART_REV_63 0x0603
93
94 struct omap8250_priv {
95 int line;
96 u8 habit;
97 u8 mdr1;
98 u8 efr;
99 u8 scr;
100 u8 wer;
101 u8 xon;
102 u8 xoff;
103 u8 delayed_restore;
104 u16 quot;
105
106 bool is_suspending;
107 int wakeirq;
108 int wakeups_enabled;
109 u32 latency;
110 u32 calc_latency;
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
114 spinlock_t rx_dma_lock;
115 bool rx_dma_broken;
116 };
117
uart_read(struct uart_8250_port * up,u32 reg)118 static u32 uart_read(struct uart_8250_port *up, u32 reg)
119 {
120 return readl(up->port.membase + (reg << up->port.regshift));
121 }
122
omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)123 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
124 {
125 struct uart_8250_port *up = up_to_u8250p(port);
126 struct omap8250_priv *priv = up->port.private_data;
127 u8 lcr;
128
129 serial8250_do_set_mctrl(port, mctrl);
130
131 /*
132 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
133 * if RTS is raised
134 */
135 lcr = serial_in(up, UART_LCR);
136 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
137 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
138 priv->efr |= UART_EFR_RTS;
139 else
140 priv->efr &= ~UART_EFR_RTS;
141 serial_out(up, UART_EFR, priv->efr);
142 serial_out(up, UART_LCR, lcr);
143 }
144
145 /*
146 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
147 * The access to uart register after MDR1 Access
148 * causes UART to corrupt data.
149 *
150 * Need a delay =
151 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
152 * give 10 times as much
153 */
omap_8250_mdr1_errataset(struct uart_8250_port * up,struct omap8250_priv * priv)154 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
155 struct omap8250_priv *priv)
156 {
157 u8 timeout = 255;
158 u8 old_mdr1;
159
160 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
161 if (old_mdr1 == priv->mdr1)
162 return;
163
164 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
165 udelay(2);
166 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
167 UART_FCR_CLEAR_RCVR);
168 /*
169 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
170 * TX_FIFO_E bit is 1.
171 */
172 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
173 (UART_LSR_THRE | UART_LSR_DR))) {
174 timeout--;
175 if (!timeout) {
176 /* Should *never* happen. we warn and carry on */
177 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
178 serial_in(up, UART_LSR));
179 break;
180 }
181 udelay(1);
182 }
183 }
184
omap_8250_get_divisor(struct uart_port * port,unsigned int baud,struct omap8250_priv * priv)185 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
186 struct omap8250_priv *priv)
187 {
188 unsigned int uartclk = port->uartclk;
189 unsigned int div_13, div_16;
190 unsigned int abs_d13, abs_d16;
191
192 /*
193 * Old custom speed handling.
194 */
195 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
196 priv->quot = port->custom_divisor & 0xffff;
197 /*
198 * I assume that nobody is using this. But hey, if somebody
199 * would like to specify the divisor _and_ the mode then the
200 * driver is ready and waiting for it.
201 */
202 if (port->custom_divisor & (1 << 16))
203 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
204 else
205 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
206 return;
207 }
208 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
209 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
210
211 if (!div_13)
212 div_13 = 1;
213 if (!div_16)
214 div_16 = 1;
215
216 abs_d13 = abs(baud - uartclk / 13 / div_13);
217 abs_d16 = abs(baud - uartclk / 16 / div_16);
218
219 if (abs_d13 >= abs_d16) {
220 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
221 priv->quot = div_16;
222 } else {
223 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
224 priv->quot = div_13;
225 }
226 }
227
omap8250_update_scr(struct uart_8250_port * up,struct omap8250_priv * priv)228 static void omap8250_update_scr(struct uart_8250_port *up,
229 struct omap8250_priv *priv)
230 {
231 u8 old_scr;
232
233 old_scr = serial_in(up, UART_OMAP_SCR);
234 if (old_scr == priv->scr)
235 return;
236
237 /*
238 * The manual recommends not to enable the DMA mode selector in the SCR
239 * (instead of the FCR) register _and_ selecting the DMA mode as one
240 * register write because this may lead to malfunction.
241 */
242 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
243 serial_out(up, UART_OMAP_SCR,
244 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
245 serial_out(up, UART_OMAP_SCR, priv->scr);
246 }
247
omap8250_update_mdr1(struct uart_8250_port * up,struct omap8250_priv * priv)248 static void omap8250_update_mdr1(struct uart_8250_port *up,
249 struct omap8250_priv *priv)
250 {
251 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
252 omap_8250_mdr1_errataset(up, priv);
253 else
254 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
255 }
256
omap8250_restore_regs(struct uart_8250_port * up)257 static void omap8250_restore_regs(struct uart_8250_port *up)
258 {
259 struct omap8250_priv *priv = up->port.private_data;
260 struct uart_8250_dma *dma = up->dma;
261
262 if (dma && dma->tx_running) {
263 /*
264 * TCSANOW requests the change to occur immediately however if
265 * we have a TX-DMA operation in progress then it has been
266 * observed that it might stall and never complete. Therefore we
267 * delay DMA completes to prevent this hang from happen.
268 */
269 priv->delayed_restore = 1;
270 return;
271 }
272
273 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
274 serial_out(up, UART_EFR, UART_EFR_ECB);
275
276 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
277 serial_out(up, UART_MCR, UART_MCR_TCRTLR);
278 serial_out(up, UART_FCR, up->fcr);
279
280 omap8250_update_scr(up, priv);
281
282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
283
284 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
285 OMAP_UART_TCR_HALT(52));
286 serial_out(up, UART_TI752_TLR,
287 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
288 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
289
290 serial_out(up, UART_LCR, 0);
291
292 /* drop TCR + TLR access, we setup XON/XOFF later */
293 serial_out(up, UART_MCR, up->mcr);
294 serial_out(up, UART_IER, up->ier);
295
296 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
297 serial_dl_write(up, priv->quot);
298
299 serial_out(up, UART_EFR, priv->efr);
300
301 /* Configure flow control */
302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
303 serial_out(up, UART_XON1, priv->xon);
304 serial_out(up, UART_XOFF1, priv->xoff);
305
306 serial_out(up, UART_LCR, up->lcr);
307
308 omap8250_update_mdr1(up, priv);
309
310 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
311 }
312
313 /*
314 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
315 * some differences in how we want to handle flow control.
316 */
omap_8250_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)317 static void omap_8250_set_termios(struct uart_port *port,
318 struct ktermios *termios,
319 struct ktermios *old)
320 {
321 struct uart_8250_port *up =
322 container_of(port, struct uart_8250_port, port);
323 struct omap8250_priv *priv = up->port.private_data;
324 unsigned char cval = 0;
325 unsigned int baud;
326
327 switch (termios->c_cflag & CSIZE) {
328 case CS5:
329 cval = UART_LCR_WLEN5;
330 break;
331 case CS6:
332 cval = UART_LCR_WLEN6;
333 break;
334 case CS7:
335 cval = UART_LCR_WLEN7;
336 break;
337 default:
338 case CS8:
339 cval = UART_LCR_WLEN8;
340 break;
341 }
342
343 if (termios->c_cflag & CSTOPB)
344 cval |= UART_LCR_STOP;
345 if (termios->c_cflag & PARENB)
346 cval |= UART_LCR_PARITY;
347 if (!(termios->c_cflag & PARODD))
348 cval |= UART_LCR_EPAR;
349 if (termios->c_cflag & CMSPAR)
350 cval |= UART_LCR_SPAR;
351
352 /*
353 * Ask the core to calculate the divisor for us.
354 */
355 baud = uart_get_baud_rate(port, termios, old,
356 port->uartclk / 16 / 0xffff,
357 port->uartclk / 13);
358 omap_8250_get_divisor(port, baud, priv);
359
360 /*
361 * Ok, we're now changing the port state. Do it with
362 * interrupts disabled.
363 */
364 pm_runtime_get_sync(port->dev);
365 spin_lock_irq(&port->lock);
366
367 /*
368 * Update the per-port timeout.
369 */
370 uart_update_timeout(port, termios->c_cflag, baud);
371
372 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
373 if (termios->c_iflag & INPCK)
374 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
375 if (termios->c_iflag & (IGNBRK | PARMRK))
376 up->port.read_status_mask |= UART_LSR_BI;
377
378 /*
379 * Characters to ignore
380 */
381 up->port.ignore_status_mask = 0;
382 if (termios->c_iflag & IGNPAR)
383 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
384 if (termios->c_iflag & IGNBRK) {
385 up->port.ignore_status_mask |= UART_LSR_BI;
386 /*
387 * If we're ignoring parity and break indicators,
388 * ignore overruns too (for real raw support).
389 */
390 if (termios->c_iflag & IGNPAR)
391 up->port.ignore_status_mask |= UART_LSR_OE;
392 }
393
394 /*
395 * ignore all characters if CREAD is not set
396 */
397 if ((termios->c_cflag & CREAD) == 0)
398 up->port.ignore_status_mask |= UART_LSR_DR;
399
400 /*
401 * Modem status interrupts
402 */
403 up->ier &= ~UART_IER_MSI;
404 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
405 up->ier |= UART_IER_MSI;
406
407 up->lcr = cval;
408 /* Up to here it was mostly serial8250_do_set_termios() */
409
410 /*
411 * We enable TRIG_GRANU for RX and TX and additionaly we set
412 * SCR_TX_EMPTY bit. The result is the following:
413 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
414 * - less than RX_TRIGGER number of bytes will also cause an interrupt
415 * once the UART decides that there no new bytes arriving.
416 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
417 * empty - the trigger level is ignored here.
418 *
419 * Once DMA is enabled:
420 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
421 * bytes in the TX FIFO. On each assert the DMA engine will move
422 * TX_TRIGGER bytes into the FIFO.
423 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
424 * the FIFO and move RX_TRIGGER bytes.
425 * This is because threshold and trigger values are the same.
426 */
427 up->fcr = UART_FCR_ENABLE_FIFO;
428 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
429 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
430
431 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
432 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
433
434 if (up->dma)
435 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
436 OMAP_UART_SCR_DMAMODE_CTL;
437
438 priv->xon = termios->c_cc[VSTART];
439 priv->xoff = termios->c_cc[VSTOP];
440
441 priv->efr = 0;
442 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
443
444 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
445 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
446 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
447 priv->efr |= UART_EFR_CTS;
448 } else if (up->port.flags & UPF_SOFT_FLOW) {
449 /*
450 * OMAP rx s/w flow control is borked; the transmitter remains
451 * stuck off even if rx flow control is subsequently disabled
452 */
453
454 /*
455 * IXOFF Flag:
456 * Enable XON/XOFF flow control on output.
457 * Transmit XON1, XOFF1
458 */
459 if (termios->c_iflag & IXOFF) {
460 up->port.status |= UPSTAT_AUTOXOFF;
461 priv->efr |= OMAP_UART_SW_TX;
462 }
463 }
464 omap8250_restore_regs(up);
465
466 spin_unlock_irq(&up->port.lock);
467 pm_runtime_mark_last_busy(port->dev);
468 pm_runtime_put_autosuspend(port->dev);
469
470 /* calculate wakeup latency constraint */
471 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
472 priv->latency = priv->calc_latency;
473
474 schedule_work(&priv->qos_work);
475
476 /* Don't rewrite B0 */
477 if (tty_termios_baud_rate(termios))
478 tty_termios_encode_baud_rate(termios, baud, baud);
479 }
480
481 /* same as 8250 except that we may have extra flow bits set in EFR */
omap_8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)482 static void omap_8250_pm(struct uart_port *port, unsigned int state,
483 unsigned int oldstate)
484 {
485 struct uart_8250_port *up = up_to_u8250p(port);
486 u8 efr;
487
488 pm_runtime_get_sync(port->dev);
489 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
490 efr = serial_in(up, UART_EFR);
491 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
492 serial_out(up, UART_LCR, 0);
493
494 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
495 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
496 serial_out(up, UART_EFR, efr);
497 serial_out(up, UART_LCR, 0);
498
499 pm_runtime_mark_last_busy(port->dev);
500 pm_runtime_put_autosuspend(port->dev);
501 }
502
omap_serial_fill_features_erratas(struct uart_8250_port * up,struct omap8250_priv * priv)503 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
504 struct omap8250_priv *priv)
505 {
506 u32 mvr, scheme;
507 u16 revision, major, minor;
508
509 mvr = uart_read(up, UART_OMAP_MVER);
510
511 /* Check revision register scheme */
512 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
513
514 switch (scheme) {
515 case 0: /* Legacy Scheme: OMAP2/3 */
516 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
517 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
518 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
519 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
520 break;
521 case 1:
522 /* New Scheme: OMAP4+ */
523 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
524 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
525 OMAP_UART_MVR_MAJ_SHIFT;
526 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
527 break;
528 default:
529 dev_warn(up->port.dev,
530 "Unknown revision, defaulting to highest\n");
531 /* highest possible revision */
532 major = 0xff;
533 minor = 0xff;
534 }
535 /* normalize revision for the driver */
536 revision = UART_BUILD_REVISION(major, minor);
537
538 switch (revision) {
539 case OMAP_UART_REV_46:
540 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
541 break;
542 case OMAP_UART_REV_52:
543 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
544 OMAP_UART_WER_HAS_TX_WAKEUP;
545 break;
546 case OMAP_UART_REV_63:
547 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
548 OMAP_UART_WER_HAS_TX_WAKEUP;
549 break;
550 default:
551 break;
552 }
553 }
554
omap8250_uart_qos_work(struct work_struct * work)555 static void omap8250_uart_qos_work(struct work_struct *work)
556 {
557 struct omap8250_priv *priv;
558
559 priv = container_of(work, struct omap8250_priv, qos_work);
560 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
561 }
562
563 #ifdef CONFIG_SERIAL_8250_DMA
564 static int omap_8250_dma_handle_irq(struct uart_port *port);
565 #endif
566
omap8250_irq(int irq,void * dev_id)567 static irqreturn_t omap8250_irq(int irq, void *dev_id)
568 {
569 struct uart_port *port = dev_id;
570 struct uart_8250_port *up = up_to_u8250p(port);
571 unsigned int iir;
572 int ret;
573
574 #ifdef CONFIG_SERIAL_8250_DMA
575 if (up->dma) {
576 ret = omap_8250_dma_handle_irq(port);
577 return IRQ_RETVAL(ret);
578 }
579 #endif
580
581 serial8250_rpm_get(up);
582 iir = serial_port_in(port, UART_IIR);
583 ret = serial8250_handle_irq(port, iir);
584 serial8250_rpm_put(up);
585
586 return IRQ_RETVAL(ret);
587 }
588
omap_8250_startup(struct uart_port * port)589 static int omap_8250_startup(struct uart_port *port)
590 {
591 struct uart_8250_port *up = up_to_u8250p(port);
592 struct omap8250_priv *priv = port->private_data;
593 int ret;
594
595 if (priv->wakeirq) {
596 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
597 if (ret)
598 return ret;
599 }
600
601 pm_runtime_get_sync(port->dev);
602
603 up->mcr = 0;
604 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
605
606 serial_out(up, UART_LCR, UART_LCR_WLEN8);
607
608 up->lsr_saved_flags = 0;
609 up->msr_saved_flags = 0;
610
611 if (up->dma) {
612 ret = serial8250_request_dma(up);
613 if (ret) {
614 dev_warn_ratelimited(port->dev,
615 "failed to request DMA\n");
616 up->dma = NULL;
617 }
618 }
619
620 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
621 dev_name(port->dev), port);
622 if (ret < 0)
623 goto err;
624
625 up->ier = UART_IER_RLSI | UART_IER_RDI;
626 serial_out(up, UART_IER, up->ier);
627
628 #ifdef CONFIG_PM
629 up->capabilities |= UART_CAP_RPM;
630 #endif
631
632 /* Enable module level wake up */
633 priv->wer = OMAP_UART_WER_MOD_WKUP;
634 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
635 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
636 serial_out(up, UART_OMAP_WER, priv->wer);
637
638 if (up->dma)
639 up->dma->rx_dma(up, 0);
640
641 pm_runtime_mark_last_busy(port->dev);
642 pm_runtime_put_autosuspend(port->dev);
643 return 0;
644 err:
645 pm_runtime_mark_last_busy(port->dev);
646 pm_runtime_put_autosuspend(port->dev);
647 dev_pm_clear_wake_irq(port->dev);
648 return ret;
649 }
650
omap_8250_shutdown(struct uart_port * port)651 static void omap_8250_shutdown(struct uart_port *port)
652 {
653 struct uart_8250_port *up = up_to_u8250p(port);
654 struct omap8250_priv *priv = port->private_data;
655
656 flush_work(&priv->qos_work);
657 if (up->dma)
658 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT);
659
660 pm_runtime_get_sync(port->dev);
661
662 serial_out(up, UART_OMAP_WER, 0);
663
664 up->ier = 0;
665 serial_out(up, UART_IER, 0);
666
667 if (up->dma)
668 serial8250_release_dma(up);
669
670 /*
671 * Disable break condition and FIFOs
672 */
673 if (up->lcr & UART_LCR_SBC)
674 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
675 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
676
677 pm_runtime_mark_last_busy(port->dev);
678 pm_runtime_put_autosuspend(port->dev);
679 free_irq(port->irq, port);
680 dev_pm_clear_wake_irq(port->dev);
681 }
682
omap_8250_throttle(struct uart_port * port)683 static void omap_8250_throttle(struct uart_port *port)
684 {
685 unsigned long flags;
686 struct uart_8250_port *up =
687 container_of(port, struct uart_8250_port, port);
688
689 pm_runtime_get_sync(port->dev);
690
691 spin_lock_irqsave(&port->lock, flags);
692 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
693 serial_out(up, UART_IER, up->ier);
694 spin_unlock_irqrestore(&port->lock, flags);
695
696 pm_runtime_mark_last_busy(port->dev);
697 pm_runtime_put_autosuspend(port->dev);
698 }
699
omap_8250_unthrottle(struct uart_port * port)700 static void omap_8250_unthrottle(struct uart_port *port)
701 {
702 unsigned long flags;
703 struct uart_8250_port *up =
704 container_of(port, struct uart_8250_port, port);
705
706 pm_runtime_get_sync(port->dev);
707
708 spin_lock_irqsave(&port->lock, flags);
709 up->ier |= UART_IER_RLSI | UART_IER_RDI;
710 serial_out(up, UART_IER, up->ier);
711 spin_unlock_irqrestore(&port->lock, flags);
712
713 pm_runtime_mark_last_busy(port->dev);
714 pm_runtime_put_autosuspend(port->dev);
715 }
716
717 #ifdef CONFIG_SERIAL_8250_DMA
718 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir);
719
__dma_rx_do_complete(struct uart_8250_port * p,bool error)720 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error)
721 {
722 struct omap8250_priv *priv = p->port.private_data;
723 struct uart_8250_dma *dma = p->dma;
724 struct tty_port *tty_port = &p->port.state->port;
725 struct dma_tx_state state;
726 int count;
727 unsigned long flags;
728 int ret;
729
730 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
731 dma->rx_size, DMA_FROM_DEVICE);
732
733 spin_lock_irqsave(&priv->rx_dma_lock, flags);
734
735 if (!dma->rx_running)
736 goto unlock;
737
738 dma->rx_running = 0;
739 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
740 dmaengine_terminate_all(dma->rxchan);
741
742 count = dma->rx_size - state.residue;
743
744 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
745
746 p->port.icount.rx += ret;
747 p->port.icount.buf_overrun += count - ret;
748 unlock:
749 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
750
751 if (!error)
752 omap_8250_rx_dma(p, 0);
753
754 tty_flip_buffer_push(tty_port);
755 }
756
__dma_rx_complete(void * param)757 static void __dma_rx_complete(void *param)
758 {
759 __dma_rx_do_complete(param, false);
760 }
761
omap_8250_rx_dma_flush(struct uart_8250_port * p)762 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
763 {
764 struct omap8250_priv *priv = p->port.private_data;
765 struct uart_8250_dma *dma = p->dma;
766 unsigned long flags;
767 int ret;
768
769 spin_lock_irqsave(&priv->rx_dma_lock, flags);
770
771 if (!dma->rx_running) {
772 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
773 return;
774 }
775
776 ret = dmaengine_pause(dma->rxchan);
777 if (WARN_ON_ONCE(ret))
778 priv->rx_dma_broken = true;
779
780 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
781
782 __dma_rx_do_complete(p, true);
783 }
784
omap_8250_rx_dma(struct uart_8250_port * p,unsigned int iir)785 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
786 {
787 struct omap8250_priv *priv = p->port.private_data;
788 struct uart_8250_dma *dma = p->dma;
789 int err = 0;
790 struct dma_async_tx_descriptor *desc;
791 unsigned long flags;
792
793 switch (iir & 0x3f) {
794 case UART_IIR_RLSI:
795 /* 8250_core handles errors and break interrupts */
796 omap_8250_rx_dma_flush(p);
797 return -EIO;
798 case UART_IIR_RX_TIMEOUT:
799 /*
800 * If RCVR FIFO trigger level was not reached, complete the
801 * transfer and let 8250_core copy the remaining data.
802 */
803 omap_8250_rx_dma_flush(p);
804 return -ETIMEDOUT;
805 case UART_IIR_RDI:
806 /*
807 * The OMAP UART is a special BEAST. If we receive RDI we _have_
808 * a DMA transfer programmed but it didn't work. One reason is
809 * that we were too slow and there were too many bytes in the
810 * FIFO, the UART counted wrong and never kicked the DMA engine
811 * to do anything. That means once we receive RDI on OMAP then
812 * the DMA won't do anything soon so we have to cancel the DMA
813 * transfer and purge the FIFO manually.
814 */
815 omap_8250_rx_dma_flush(p);
816 return -ETIMEDOUT;
817
818 default:
819 break;
820 }
821
822 if (priv->rx_dma_broken)
823 return -EINVAL;
824
825 spin_lock_irqsave(&priv->rx_dma_lock, flags);
826
827 if (dma->rx_running)
828 goto out;
829
830 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
831 dma->rx_size, DMA_DEV_TO_MEM,
832 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
833 if (!desc) {
834 err = -EBUSY;
835 goto out;
836 }
837
838 dma->rx_running = 1;
839 desc->callback = __dma_rx_complete;
840 desc->callback_param = p;
841
842 dma->rx_cookie = dmaengine_submit(desc);
843
844 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
845 dma->rx_size, DMA_FROM_DEVICE);
846
847 dma_async_issue_pending(dma->rxchan);
848 out:
849 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
850 return err;
851 }
852
853 static int omap_8250_tx_dma(struct uart_8250_port *p);
854
omap_8250_dma_tx_complete(void * param)855 static void omap_8250_dma_tx_complete(void *param)
856 {
857 struct uart_8250_port *p = param;
858 struct uart_8250_dma *dma = p->dma;
859 struct circ_buf *xmit = &p->port.state->xmit;
860 unsigned long flags;
861 bool en_thri = false;
862 struct omap8250_priv *priv = p->port.private_data;
863
864 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
865 UART_XMIT_SIZE, DMA_TO_DEVICE);
866
867 spin_lock_irqsave(&p->port.lock, flags);
868
869 dma->tx_running = 0;
870
871 xmit->tail += dma->tx_size;
872 xmit->tail &= UART_XMIT_SIZE - 1;
873 p->port.icount.tx += dma->tx_size;
874
875 if (priv->delayed_restore) {
876 priv->delayed_restore = 0;
877 omap8250_restore_regs(p);
878 }
879
880 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
881 uart_write_wakeup(&p->port);
882
883 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
884 int ret;
885
886 ret = omap_8250_tx_dma(p);
887 if (ret)
888 en_thri = true;
889
890 } else if (p->capabilities & UART_CAP_RPM) {
891 en_thri = true;
892 }
893
894 if (en_thri) {
895 dma->tx_err = 1;
896 p->ier |= UART_IER_THRI;
897 serial_port_out(&p->port, UART_IER, p->ier);
898 }
899
900 spin_unlock_irqrestore(&p->port.lock, flags);
901 }
902
omap_8250_tx_dma(struct uart_8250_port * p)903 static int omap_8250_tx_dma(struct uart_8250_port *p)
904 {
905 struct uart_8250_dma *dma = p->dma;
906 struct omap8250_priv *priv = p->port.private_data;
907 struct circ_buf *xmit = &p->port.state->xmit;
908 struct dma_async_tx_descriptor *desc;
909 unsigned int skip_byte = 0;
910 int ret;
911
912 if (dma->tx_running)
913 return 0;
914 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
915
916 /*
917 * Even if no data, we need to return an error for the two cases
918 * below so serial8250_tx_chars() is invoked and properly clears
919 * THRI and/or runtime suspend.
920 */
921 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
922 ret = -EBUSY;
923 goto err;
924 }
925 if (p->ier & UART_IER_THRI) {
926 p->ier &= ~UART_IER_THRI;
927 serial_out(p, UART_IER, p->ier);
928 }
929 return 0;
930 }
931
932 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
933 if (priv->habit & OMAP_DMA_TX_KICK) {
934 u8 tx_lvl;
935
936 /*
937 * We need to put the first byte into the FIFO in order to start
938 * the DMA transfer. For transfers smaller than four bytes we
939 * don't bother doing DMA at all. It seem not matter if there
940 * are still bytes in the FIFO from the last transfer (in case
941 * we got here directly from omap_8250_dma_tx_complete()). Bytes
942 * leaving the FIFO seem not to trigger the DMA transfer. It is
943 * really the byte that we put into the FIFO.
944 * If the FIFO is already full then we most likely got here from
945 * omap_8250_dma_tx_complete(). And this means the DMA engine
946 * just completed its work. We don't have to wait the complete
947 * 86us at 115200,8n1 but around 60us (not to mention lower
948 * baudrates). So in that case we take the interrupt and try
949 * again with an empty FIFO.
950 */
951 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
952 if (tx_lvl == p->tx_loadsz) {
953 ret = -EBUSY;
954 goto err;
955 }
956 if (dma->tx_size < 4) {
957 ret = -EINVAL;
958 goto err;
959 }
960 skip_byte = 1;
961 }
962
963 desc = dmaengine_prep_slave_single(dma->txchan,
964 dma->tx_addr + xmit->tail + skip_byte,
965 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
966 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
967 if (!desc) {
968 ret = -EBUSY;
969 goto err;
970 }
971
972 dma->tx_running = 1;
973
974 desc->callback = omap_8250_dma_tx_complete;
975 desc->callback_param = p;
976
977 dma->tx_cookie = dmaengine_submit(desc);
978
979 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
980 UART_XMIT_SIZE, DMA_TO_DEVICE);
981
982 dma_async_issue_pending(dma->txchan);
983 if (dma->tx_err)
984 dma->tx_err = 0;
985
986 if (p->ier & UART_IER_THRI) {
987 p->ier &= ~UART_IER_THRI;
988 serial_out(p, UART_IER, p->ier);
989 }
990 if (skip_byte)
991 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
992 return 0;
993 err:
994 dma->tx_err = 1;
995 return ret;
996 }
997
998 /*
999 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1000 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1001 * use the default routine in the non-DMA case and this one for with DMA.
1002 */
omap_8250_dma_handle_irq(struct uart_port * port)1003 static int omap_8250_dma_handle_irq(struct uart_port *port)
1004 {
1005 struct uart_8250_port *up = up_to_u8250p(port);
1006 unsigned char status;
1007 unsigned long flags;
1008 u8 iir;
1009 int dma_err = 0;
1010
1011 serial8250_rpm_get(up);
1012
1013 iir = serial_port_in(port, UART_IIR);
1014 if (iir & UART_IIR_NO_INT) {
1015 serial8250_rpm_put(up);
1016 return 0;
1017 }
1018
1019 spin_lock_irqsave(&port->lock, flags);
1020
1021 status = serial_port_in(port, UART_LSR);
1022
1023 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1024
1025 dma_err = omap_8250_rx_dma(up, iir);
1026 if (dma_err) {
1027 status = serial8250_rx_chars(up, status);
1028 omap_8250_rx_dma(up, 0);
1029 }
1030 }
1031 serial8250_modem_status(up);
1032 if (status & UART_LSR_THRE && up->dma->tx_err) {
1033 if (uart_tx_stopped(&up->port) ||
1034 uart_circ_empty(&up->port.state->xmit)) {
1035 up->dma->tx_err = 0;
1036 serial8250_tx_chars(up);
1037 } else {
1038 /*
1039 * try again due to an earlier failer which
1040 * might have been resolved by now.
1041 */
1042 dma_err = omap_8250_tx_dma(up);
1043 if (dma_err)
1044 serial8250_tx_chars(up);
1045 }
1046 }
1047
1048 spin_unlock_irqrestore(&port->lock, flags);
1049 serial8250_rpm_put(up);
1050 return 1;
1051 }
1052
the_no_dma_filter_fn(struct dma_chan * chan,void * param)1053 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1054 {
1055 return false;
1056 }
1057
1058 #else
1059
omap_8250_rx_dma(struct uart_8250_port * p,unsigned int iir)1060 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
1061 {
1062 return -EINVAL;
1063 }
1064 #endif
1065
omap8250_no_handle_irq(struct uart_port * port)1066 static int omap8250_no_handle_irq(struct uart_port *port)
1067 {
1068 /* IRQ has not been requested but handling irq? */
1069 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1070 return 0;
1071 }
1072
1073 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1074 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE;
1075
1076 static const struct of_device_id omap8250_dt_ids[] = {
1077 { .compatible = "ti,omap2-uart" },
1078 { .compatible = "ti,omap3-uart" },
1079 { .compatible = "ti,omap4-uart" },
1080 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1081 { .compatible = "ti,am4372-uart", .data = &am4372_habit, },
1082 { .compatible = "ti,dra742-uart", .data = &am4372_habit, },
1083 {},
1084 };
1085 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1086
omap8250_probe(struct platform_device * pdev)1087 static int omap8250_probe(struct platform_device *pdev)
1088 {
1089 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1091 struct omap8250_priv *priv;
1092 struct uart_8250_port up;
1093 int ret;
1094 void __iomem *membase;
1095
1096 if (!regs || !irq) {
1097 dev_err(&pdev->dev, "missing registers or irq\n");
1098 return -EINVAL;
1099 }
1100
1101 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1102 if (!priv)
1103 return -ENOMEM;
1104
1105 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1106 resource_size(regs));
1107 if (!membase)
1108 return -ENODEV;
1109
1110 memset(&up, 0, sizeof(up));
1111 up.port.dev = &pdev->dev;
1112 up.port.mapbase = regs->start;
1113 up.port.membase = membase;
1114 up.port.irq = irq->start;
1115 /*
1116 * It claims to be 16C750 compatible however it is a little different.
1117 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1118 * have) is enabled via EFR instead of MCR. The type is set here 8250
1119 * just to get things going. UNKNOWN does not work for a few reasons and
1120 * we don't need our own type since we don't use 8250's set_termios()
1121 * or pm callback.
1122 */
1123 up.port.type = PORT_8250;
1124 up.port.iotype = UPIO_MEM;
1125 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1126 UPF_HARD_FLOW;
1127 up.port.private_data = priv;
1128
1129 up.port.regshift = 2;
1130 up.port.fifosize = 64;
1131 up.tx_loadsz = 64;
1132 up.capabilities = UART_CAP_FIFO;
1133 #ifdef CONFIG_PM
1134 /*
1135 * Runtime PM is mostly transparent. However to do it right we need to a
1136 * TX empty interrupt before we can put the device to auto idle. So if
1137 * PM is not enabled we don't add that flag and can spare that one extra
1138 * interrupt in the TX path.
1139 */
1140 up.capabilities |= UART_CAP_RPM;
1141 #endif
1142 up.port.set_termios = omap_8250_set_termios;
1143 up.port.set_mctrl = omap8250_set_mctrl;
1144 up.port.pm = omap_8250_pm;
1145 up.port.startup = omap_8250_startup;
1146 up.port.shutdown = omap_8250_shutdown;
1147 up.port.throttle = omap_8250_throttle;
1148 up.port.unthrottle = omap_8250_unthrottle;
1149
1150 if (pdev->dev.of_node) {
1151 const struct of_device_id *id;
1152
1153 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1154
1155 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1156 &up.port.uartclk);
1157 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1158
1159 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1160 if (id && id->data)
1161 priv->habit |= *(u8 *)id->data;
1162 } else {
1163 ret = pdev->id;
1164 }
1165 if (ret < 0) {
1166 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1167 return ret;
1168 }
1169 up.port.line = ret;
1170
1171 if (!up.port.uartclk) {
1172 up.port.uartclk = DEFAULT_CLK_SPEED;
1173 dev_warn(&pdev->dev,
1174 "No clock speed specified: using default: %d\n",
1175 DEFAULT_CLK_SPEED);
1176 }
1177
1178 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1179 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1180 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1181 priv->latency);
1182 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1183
1184 spin_lock_init(&priv->rx_dma_lock);
1185
1186 device_init_wakeup(&pdev->dev, true);
1187 pm_runtime_use_autosuspend(&pdev->dev);
1188 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1189
1190 pm_runtime_irq_safe(&pdev->dev);
1191 pm_runtime_enable(&pdev->dev);
1192
1193 pm_runtime_get_sync(&pdev->dev);
1194
1195 omap_serial_fill_features_erratas(&up, priv);
1196 up.port.handle_irq = omap8250_no_handle_irq;
1197 #ifdef CONFIG_SERIAL_8250_DMA
1198 if (pdev->dev.of_node) {
1199 /*
1200 * Oh DMA support. If there are no DMA properties in the DT then
1201 * we will fall back to a generic DMA channel which does not
1202 * really work here. To ensure that we do not get a generic DMA
1203 * channel assigned, we have the the_no_dma_filter_fn() here.
1204 * To avoid "failed to request DMA" messages we check for DMA
1205 * properties in DT.
1206 */
1207 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1208 if (ret == 2) {
1209 up.dma = &priv->omap8250_dma;
1210 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1211 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1212 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1213 priv->omap8250_dma.rx_size = RX_TRIGGER;
1214 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1215 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1216
1217 if (of_machine_is_compatible("ti,am33xx"))
1218 priv->habit |= OMAP_DMA_TX_KICK;
1219 /*
1220 * pause is currently not supported atleast on omap-sdma
1221 * and edma on most earlier kernels.
1222 */
1223 priv->rx_dma_broken = true;
1224 }
1225 }
1226 #endif
1227 ret = serial8250_register_8250_port(&up);
1228 if (ret < 0) {
1229 dev_err(&pdev->dev, "unable to register 8250 port\n");
1230 goto err;
1231 }
1232 priv->line = ret;
1233 platform_set_drvdata(pdev, priv);
1234 pm_runtime_mark_last_busy(&pdev->dev);
1235 pm_runtime_put_autosuspend(&pdev->dev);
1236 return 0;
1237 err:
1238 pm_runtime_put(&pdev->dev);
1239 pm_runtime_disable(&pdev->dev);
1240 return ret;
1241 }
1242
omap8250_remove(struct platform_device * pdev)1243 static int omap8250_remove(struct platform_device *pdev)
1244 {
1245 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1246
1247 pm_runtime_put_sync(&pdev->dev);
1248 pm_runtime_disable(&pdev->dev);
1249 serial8250_unregister_port(priv->line);
1250 pm_qos_remove_request(&priv->pm_qos_request);
1251 device_init_wakeup(&pdev->dev, false);
1252 return 0;
1253 }
1254
1255 #ifdef CONFIG_PM_SLEEP
omap8250_prepare(struct device * dev)1256 static int omap8250_prepare(struct device *dev)
1257 {
1258 struct omap8250_priv *priv = dev_get_drvdata(dev);
1259
1260 if (!priv)
1261 return 0;
1262 priv->is_suspending = true;
1263 return 0;
1264 }
1265
omap8250_complete(struct device * dev)1266 static void omap8250_complete(struct device *dev)
1267 {
1268 struct omap8250_priv *priv = dev_get_drvdata(dev);
1269
1270 if (!priv)
1271 return;
1272 priv->is_suspending = false;
1273 }
1274
omap8250_suspend(struct device * dev)1275 static int omap8250_suspend(struct device *dev)
1276 {
1277 struct omap8250_priv *priv = dev_get_drvdata(dev);
1278
1279 serial8250_suspend_port(priv->line);
1280 flush_work(&priv->qos_work);
1281 return 0;
1282 }
1283
omap8250_resume(struct device * dev)1284 static int omap8250_resume(struct device *dev)
1285 {
1286 struct omap8250_priv *priv = dev_get_drvdata(dev);
1287
1288 serial8250_resume_port(priv->line);
1289 return 0;
1290 }
1291 #else
1292 #define omap8250_prepare NULL
1293 #define omap8250_complete NULL
1294 #endif
1295
1296 #ifdef CONFIG_PM
omap8250_lost_context(struct uart_8250_port * up)1297 static int omap8250_lost_context(struct uart_8250_port *up)
1298 {
1299 u32 val;
1300
1301 val = serial_in(up, UART_OMAP_SCR);
1302 /*
1303 * If we lose context, then SCR is set to its reset value of zero.
1304 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1305 * among other bits, to never set the register back to zero again.
1306 */
1307 if (!val)
1308 return 1;
1309 return 0;
1310 }
1311
1312 /* TODO: in future, this should happen via API in drivers/reset/ */
omap8250_soft_reset(struct device * dev)1313 static int omap8250_soft_reset(struct device *dev)
1314 {
1315 struct omap8250_priv *priv = dev_get_drvdata(dev);
1316 struct uart_8250_port *up = serial8250_get_port(priv->line);
1317 int timeout = 100;
1318 int sysc;
1319 int syss;
1320
1321 sysc = serial_in(up, UART_OMAP_SYSC);
1322
1323 /* softreset the UART */
1324 sysc |= OMAP_UART_SYSC_SOFTRESET;
1325 serial_out(up, UART_OMAP_SYSC, sysc);
1326
1327 /* By experiments, 1us enough for reset complete on AM335x */
1328 do {
1329 udelay(1);
1330 syss = serial_in(up, UART_OMAP_SYSS);
1331 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1332
1333 if (!timeout) {
1334 dev_err(dev, "timed out waiting for reset done\n");
1335 return -ETIMEDOUT;
1336 }
1337
1338 return 0;
1339 }
1340
omap8250_runtime_suspend(struct device * dev)1341 static int omap8250_runtime_suspend(struct device *dev)
1342 {
1343 struct omap8250_priv *priv = dev_get_drvdata(dev);
1344 struct uart_8250_port *up;
1345
1346 up = serial8250_get_port(priv->line);
1347 /*
1348 * When using 'no_console_suspend', the console UART must not be
1349 * suspended. Since driver suspend is managed by runtime suspend,
1350 * preventing runtime suspend (by returning error) will keep device
1351 * active during suspend.
1352 */
1353 if (priv->is_suspending && !console_suspend_enabled) {
1354 if (uart_console(&up->port))
1355 return -EBUSY;
1356 }
1357
1358 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1359 int ret;
1360
1361 ret = omap8250_soft_reset(dev);
1362 if (ret)
1363 return ret;
1364
1365 /* Restore to UART mode after reset (for wakeup) */
1366 omap8250_update_mdr1(up, priv);
1367 }
1368
1369 if (up->dma && up->dma->rxchan)
1370 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT);
1371
1372 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1373 schedule_work(&priv->qos_work);
1374
1375 return 0;
1376 }
1377
omap8250_runtime_resume(struct device * dev)1378 static int omap8250_runtime_resume(struct device *dev)
1379 {
1380 struct omap8250_priv *priv = dev_get_drvdata(dev);
1381 struct uart_8250_port *up;
1382 int loss_cntx;
1383
1384 /* In case runtime-pm tries this before we are setup */
1385 if (!priv)
1386 return 0;
1387
1388 up = serial8250_get_port(priv->line);
1389 loss_cntx = omap8250_lost_context(up);
1390
1391 if (loss_cntx)
1392 omap8250_restore_regs(up);
1393
1394 if (up->dma && up->dma->rxchan)
1395 omap_8250_rx_dma(up, 0);
1396
1397 priv->latency = priv->calc_latency;
1398 schedule_work(&priv->qos_work);
1399 return 0;
1400 }
1401 #endif
1402
1403 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
omap8250_console_fixup(void)1404 static int __init omap8250_console_fixup(void)
1405 {
1406 char *omap_str;
1407 char *options;
1408 u8 idx;
1409
1410 if (strstr(boot_command_line, "console=ttyS"))
1411 /* user set a ttyS based name for the console */
1412 return 0;
1413
1414 omap_str = strstr(boot_command_line, "console=ttyO");
1415 if (!omap_str)
1416 /* user did not set ttyO based console, so we don't care */
1417 return 0;
1418
1419 omap_str += 12;
1420 if ('0' <= *omap_str && *omap_str <= '9')
1421 idx = *omap_str - '0';
1422 else
1423 return 0;
1424
1425 omap_str++;
1426 if (omap_str[0] == ',') {
1427 omap_str++;
1428 options = omap_str;
1429 } else {
1430 options = NULL;
1431 }
1432
1433 add_preferred_console("ttyS", idx, options);
1434 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1435 idx, idx);
1436 pr_err("This ensures that you still see kernel messages. Please\n");
1437 pr_err("update your kernel commandline.\n");
1438 return 0;
1439 }
1440 console_initcall(omap8250_console_fixup);
1441 #endif
1442
1443 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1444 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1445 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1446 omap8250_runtime_resume, NULL)
1447 .prepare = omap8250_prepare,
1448 .complete = omap8250_complete,
1449 };
1450
1451 static struct platform_driver omap8250_platform_driver = {
1452 .driver = {
1453 .name = "omap8250",
1454 .pm = &omap8250_dev_pm_ops,
1455 .of_match_table = omap8250_dt_ids,
1456 },
1457 .probe = omap8250_probe,
1458 .remove = omap8250_remove,
1459 };
1460 module_platform_driver(omap8250_platform_driver);
1461
1462 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1463 MODULE_DESCRIPTION("OMAP 8250 Driver");
1464 MODULE_LICENSE("GPL v2");
1465