1 /*
2  * Copyright (C) 2014 Intel Corporation
3  *
4  * Authors:
5  * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
6  *
7  * Maintained by: <tpmdd-devel@lists.sourceforge.net>
8  *
9  * This device driver implements the TPM interface as defined in
10  * the TCG CRB 2.0 TPM specification.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License
14  * as published by the Free Software Foundation; version 2
15  * of the License.
16  */
17 
18 #include <linux/acpi.h>
19 #include <linux/highmem.h>
20 #include <linux/rculist.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include "tpm.h"
24 
25 #define ACPI_SIG_TPM2 "TPM2"
26 
27 static const u8 CRB_ACPI_START_UUID[] = {
28 	/* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
29 	/* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
30 };
31 
32 enum crb_defaults {
33 	CRB_ACPI_START_REVISION_ID = 1,
34 	CRB_ACPI_START_INDEX = 1,
35 };
36 
37 struct acpi_tpm2 {
38 	struct acpi_table_header hdr;
39 	u16 platform_class;
40 	u16 reserved;
41 	u64 control_area_pa;
42 	u32 start_method;
43 } __packed;
44 
45 enum crb_ca_request {
46 	CRB_CA_REQ_GO_IDLE	= BIT(0),
47 	CRB_CA_REQ_CMD_READY	= BIT(1),
48 };
49 
50 enum crb_ca_status {
51 	CRB_CA_STS_ERROR	= BIT(0),
52 	CRB_CA_STS_TPM_IDLE	= BIT(1),
53 };
54 
55 enum crb_start {
56 	CRB_START_INVOKE	= BIT(0),
57 };
58 
59 enum crb_cancel {
60 	CRB_CANCEL_INVOKE	= BIT(0),
61 };
62 
63 struct crb_control_area {
64 	u32 req;
65 	u32 sts;
66 	u32 cancel;
67 	u32 start;
68 	u32 int_enable;
69 	u32 int_sts;
70 	u32 cmd_size;
71 	u64 cmd_pa;
72 	u32 rsp_size;
73 	u64 rsp_pa;
74 } __packed;
75 
76 enum crb_status {
77 	CRB_STS_COMPLETE	= BIT(0),
78 };
79 
80 enum crb_flags {
81 	CRB_FL_ACPI_START	= BIT(0),
82 	CRB_FL_CRB_START	= BIT(1),
83 };
84 
85 struct crb_priv {
86 	unsigned int flags;
87 	struct crb_control_area __iomem *cca;
88 	u8 __iomem *cmd;
89 	u8 __iomem *rsp;
90 };
91 
92 static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);
93 
crb_status(struct tpm_chip * chip)94 static u8 crb_status(struct tpm_chip *chip)
95 {
96 	struct crb_priv *priv = chip->vendor.priv;
97 	u8 sts = 0;
98 
99 	if ((le32_to_cpu(ioread32(&priv->cca->start)) & CRB_START_INVOKE) !=
100 	    CRB_START_INVOKE)
101 		sts |= CRB_STS_COMPLETE;
102 
103 	return sts;
104 }
105 
crb_recv(struct tpm_chip * chip,u8 * buf,size_t count)106 static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
107 {
108 	struct crb_priv *priv = chip->vendor.priv;
109 	unsigned int expected;
110 
111 	/* sanity check */
112 	if (count < 6)
113 		return -EIO;
114 
115 	if (le32_to_cpu(ioread32(&priv->cca->sts)) & CRB_CA_STS_ERROR)
116 		return -EIO;
117 
118 	memcpy_fromio(buf, priv->rsp, 6);
119 	expected = be32_to_cpup((__be32 *) &buf[2]);
120 
121 	if (expected > count)
122 		return -EIO;
123 
124 	memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);
125 
126 	return expected;
127 }
128 
crb_do_acpi_start(struct tpm_chip * chip)129 static int crb_do_acpi_start(struct tpm_chip *chip)
130 {
131 	union acpi_object *obj;
132 	int rc;
133 
134 	obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
135 				CRB_ACPI_START_UUID,
136 				CRB_ACPI_START_REVISION_ID,
137 				CRB_ACPI_START_INDEX,
138 				NULL);
139 	if (!obj)
140 		return -ENXIO;
141 	rc = obj->integer.value == 0 ? 0 : -ENXIO;
142 	ACPI_FREE(obj);
143 	return rc;
144 }
145 
crb_send(struct tpm_chip * chip,u8 * buf,size_t len)146 static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
147 {
148 	struct crb_priv *priv = chip->vendor.priv;
149 	int rc = 0;
150 
151 	if (len > le32_to_cpu(ioread32(&priv->cca->cmd_size))) {
152 		dev_err(&chip->dev,
153 			"invalid command count value %x %zx\n",
154 			(unsigned int) len,
155 			(size_t) le32_to_cpu(ioread32(&priv->cca->cmd_size)));
156 		return -E2BIG;
157 	}
158 
159 	memcpy_toio(priv->cmd, buf, len);
160 
161 	/* Make sure that cmd is populated before issuing start. */
162 	wmb();
163 
164 	if (priv->flags & CRB_FL_CRB_START)
165 		iowrite32(cpu_to_le32(CRB_START_INVOKE), &priv->cca->start);
166 
167 	if (priv->flags & CRB_FL_ACPI_START)
168 		rc = crb_do_acpi_start(chip);
169 
170 	return rc;
171 }
172 
crb_cancel(struct tpm_chip * chip)173 static void crb_cancel(struct tpm_chip *chip)
174 {
175 	struct crb_priv *priv = chip->vendor.priv;
176 
177 	iowrite32(cpu_to_le32(CRB_CANCEL_INVOKE), &priv->cca->cancel);
178 
179 	/* Make sure that cmd is populated before issuing cancel. */
180 	wmb();
181 
182 	if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
183 		dev_err(&chip->dev, "ACPI Start failed\n");
184 
185 	iowrite32(0, &priv->cca->cancel);
186 }
187 
crb_req_canceled(struct tpm_chip * chip,u8 status)188 static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
189 {
190 	struct crb_priv *priv = chip->vendor.priv;
191 	u32 cancel = le32_to_cpu(ioread32(&priv->cca->cancel));
192 
193 	return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
194 }
195 
196 static const struct tpm_class_ops tpm_crb = {
197 	.status = crb_status,
198 	.recv = crb_recv,
199 	.send = crb_send,
200 	.cancel = crb_cancel,
201 	.req_canceled = crb_req_canceled,
202 	.req_complete_mask = CRB_STS_COMPLETE,
203 	.req_complete_val = CRB_STS_COMPLETE,
204 };
205 
crb_acpi_add(struct acpi_device * device)206 static int crb_acpi_add(struct acpi_device *device)
207 {
208 	struct tpm_chip *chip;
209 	struct acpi_tpm2 *buf;
210 	struct crb_priv *priv;
211 	struct device *dev = &device->dev;
212 	acpi_status status;
213 	u32 sm;
214 	u64 pa;
215 	int rc;
216 
217 	status = acpi_get_table(ACPI_SIG_TPM2, 1,
218 				(struct acpi_table_header **) &buf);
219 	if (ACPI_FAILURE(status)) {
220 		dev_err(dev, "failed to get TPM2 ACPI table\n");
221 		return -ENODEV;
222 	}
223 
224 	/* Should the FIFO driver handle this? */
225 	if (buf->start_method == TPM2_START_FIFO)
226 		return -ENODEV;
227 
228 	chip = tpmm_chip_alloc(dev, &tpm_crb);
229 	if (IS_ERR(chip))
230 		return PTR_ERR(chip);
231 
232 	chip->flags = TPM_CHIP_FLAG_TPM2;
233 
234 	if (buf->hdr.length < sizeof(struct acpi_tpm2)) {
235 		dev_err(dev, "TPM2 ACPI table has wrong size");
236 		return -EINVAL;
237 	}
238 
239 	priv = (struct crb_priv *) devm_kzalloc(dev, sizeof(struct crb_priv),
240 						GFP_KERNEL);
241 	if (!priv) {
242 		dev_err(dev, "failed to devm_kzalloc for private data\n");
243 		return -ENOMEM;
244 	}
245 
246 	sm = le32_to_cpu(buf->start_method);
247 
248 	/* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
249 	 * report only ACPI start but in practice seems to require both
250 	 * ACPI start and CRB start.
251 	 */
252 	if (sm == TPM2_START_CRB || sm == TPM2_START_FIFO ||
253 	    !strcmp(acpi_device_hid(device), "MSFT0101"))
254 		priv->flags |= CRB_FL_CRB_START;
255 
256 	if (sm == TPM2_START_ACPI || sm == TPM2_START_CRB_WITH_ACPI)
257 		priv->flags |= CRB_FL_ACPI_START;
258 
259 	priv->cca = (struct crb_control_area __iomem *)
260 		devm_ioremap_nocache(dev, buf->control_area_pa, 0x1000);
261 	if (!priv->cca) {
262 		dev_err(dev, "ioremap of the control area failed\n");
263 		return -ENOMEM;
264 	}
265 
266 	memcpy_fromio(&pa, &priv->cca->cmd_pa, 8);
267 	pa = le64_to_cpu(pa);
268 	priv->cmd = devm_ioremap_nocache(dev, pa,
269 					 ioread32(&priv->cca->cmd_size));
270 	if (!priv->cmd) {
271 		dev_err(dev, "ioremap of the command buffer failed\n");
272 		return -ENOMEM;
273 	}
274 
275 	memcpy_fromio(&pa, &priv->cca->rsp_pa, 8);
276 	pa = le64_to_cpu(pa);
277 	priv->rsp = devm_ioremap_nocache(dev, pa,
278 					 ioread32(&priv->cca->rsp_size));
279 	if (!priv->rsp) {
280 		dev_err(dev, "ioremap of the response buffer failed\n");
281 		return -ENOMEM;
282 	}
283 
284 	chip->vendor.priv = priv;
285 
286 	/* Default timeouts and durations */
287 	chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
288 	chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
289 	chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
290 	chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
291 	chip->vendor.duration[TPM_SHORT] =
292 		msecs_to_jiffies(TPM2_DURATION_SHORT);
293 	chip->vendor.duration[TPM_MEDIUM] =
294 		msecs_to_jiffies(TPM2_DURATION_MEDIUM);
295 	chip->vendor.duration[TPM_LONG] =
296 		msecs_to_jiffies(TPM2_DURATION_LONG);
297 
298 	chip->acpi_dev_handle = device->handle;
299 
300 	rc = tpm2_do_selftest(chip);
301 	if (rc)
302 		return rc;
303 
304 	return tpm_chip_register(chip);
305 }
306 
crb_acpi_remove(struct acpi_device * device)307 static int crb_acpi_remove(struct acpi_device *device)
308 {
309 	struct device *dev = &device->dev;
310 	struct tpm_chip *chip = dev_get_drvdata(dev);
311 
312 	if (chip->flags & TPM_CHIP_FLAG_TPM2)
313 		tpm2_shutdown(chip, TPM2_SU_CLEAR);
314 
315 	tpm_chip_unregister(chip);
316 
317 	return 0;
318 }
319 
320 static struct acpi_device_id crb_device_ids[] = {
321 	{"MSFT0101", 0},
322 	{"", 0},
323 };
324 MODULE_DEVICE_TABLE(acpi, crb_device_ids);
325 
326 static struct acpi_driver crb_acpi_driver = {
327 	.name = "tpm_crb",
328 	.ids = crb_device_ids,
329 	.ops = {
330 		.add = crb_acpi_add,
331 		.remove = crb_acpi_remove,
332 	},
333 	.drv = {
334 		.pm = &crb_pm,
335 	},
336 };
337 
338 module_acpi_driver(crb_acpi_driver);
339 MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
340 MODULE_DESCRIPTION("TPM2 Driver");
341 MODULE_VERSION("0.1");
342 MODULE_LICENSE("GPL");
343