1 #ifndef __LINUX_FUSBH200_H
2 #define __LINUX_FUSBH200_H
3
4 #include <linux/usb/ehci-dbgp.h>
5
6 /* definitions used for the EHCI driver */
7
8 /*
9 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
10 * __leXX (normally) or __beXX (given FUSBH200_BIG_ENDIAN_DESC), depending on
11 * the host controller implementation.
12 *
13 * To facilitate the strongest possible byte-order checking from "sparse"
14 * and so on, we use __leXX unless that's not practical.
15 */
16 #define __hc32 __le32
17 #define __hc16 __le16
18
19 /* statistics can be kept for tuning/monitoring */
20 struct fusbh200_stats {
21 /* irq usage */
22 unsigned long normal;
23 unsigned long error;
24 unsigned long iaa;
25 unsigned long lost_iaa;
26
27 /* termination of urbs from core */
28 unsigned long complete;
29 unsigned long unlink;
30 };
31
32 /* fusbh200_hcd->lock guards shared data against other CPUs:
33 * fusbh200_hcd: async, unlink, periodic (and shadow), ...
34 * usb_host_endpoint: hcpriv
35 * fusbh200_qh: qh_next, qtd_list
36 * fusbh200_qtd: qtd_list
37 *
38 * Also, hold this lock when talking to HC registers or
39 * when updating hw_* fields in shared qh/qtd/... structures.
40 */
41
42 #define FUSBH200_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
43
44 /*
45 * fusbh200_rh_state values of FUSBH200_RH_RUNNING or above mean that the
46 * controller may be doing DMA. Lower values mean there's no DMA.
47 */
48 enum fusbh200_rh_state {
49 FUSBH200_RH_HALTED,
50 FUSBH200_RH_SUSPENDED,
51 FUSBH200_RH_RUNNING,
52 FUSBH200_RH_STOPPING
53 };
54
55 /*
56 * Timer events, ordered by increasing delay length.
57 * Always update event_delays_ns[] and event_handlers[] (defined in
58 * ehci-timer.c) in parallel with this list.
59 */
60 enum fusbh200_hrtimer_event {
61 FUSBH200_HRTIMER_POLL_ASS, /* Poll for async schedule off */
62 FUSBH200_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
63 FUSBH200_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
64 FUSBH200_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
65 FUSBH200_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
66 FUSBH200_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
67 FUSBH200_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
68 FUSBH200_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
69 FUSBH200_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
70 FUSBH200_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
71 FUSBH200_HRTIMER_NUM_EVENTS /* Must come last */
72 };
73 #define FUSBH200_HRTIMER_NO_EVENT 99
74
75 struct fusbh200_hcd { /* one per controller */
76 /* timing support */
77 enum fusbh200_hrtimer_event next_hrtimer_event;
78 unsigned enabled_hrtimer_events;
79 ktime_t hr_timeouts[FUSBH200_HRTIMER_NUM_EVENTS];
80 struct hrtimer hrtimer;
81
82 int PSS_poll_count;
83 int ASS_poll_count;
84 int died_poll_count;
85
86 /* glue to PCI and HCD framework */
87 struct fusbh200_caps __iomem *caps;
88 struct fusbh200_regs __iomem *regs;
89 struct ehci_dbg_port __iomem *debug;
90
91 __u32 hcs_params; /* cached register copy */
92 spinlock_t lock;
93 enum fusbh200_rh_state rh_state;
94
95 /* general schedule support */
96 bool scanning:1;
97 bool need_rescan:1;
98 bool intr_unlinking:1;
99 bool async_unlinking:1;
100 bool shutdown:1;
101 struct fusbh200_qh *qh_scan_next;
102
103 /* async schedule support */
104 struct fusbh200_qh *async;
105 struct fusbh200_qh *dummy; /* For AMD quirk use */
106 struct fusbh200_qh *async_unlink;
107 struct fusbh200_qh *async_unlink_last;
108 struct fusbh200_qh *async_iaa;
109 unsigned async_unlink_cycle;
110 unsigned async_count; /* async activity count */
111
112 /* periodic schedule support */
113 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
114 unsigned periodic_size;
115 __hc32 *periodic; /* hw periodic table */
116 dma_addr_t periodic_dma;
117 struct list_head intr_qh_list;
118 unsigned i_thresh; /* uframes HC might cache */
119
120 union fusbh200_shadow *pshadow; /* mirror hw periodic table */
121 struct fusbh200_qh *intr_unlink;
122 struct fusbh200_qh *intr_unlink_last;
123 unsigned intr_unlink_cycle;
124 unsigned now_frame; /* frame from HC hardware */
125 unsigned next_frame; /* scan periodic, start here */
126 unsigned intr_count; /* intr activity count */
127 unsigned isoc_count; /* isoc activity count */
128 unsigned periodic_count; /* periodic activity count */
129 unsigned uframe_periodic_max; /* max periodic time per uframe */
130
131
132 /* list of itds completed while now_frame was still active */
133 struct list_head cached_itd_list;
134 struct fusbh200_itd *last_itd_to_free;
135
136 /* per root hub port */
137 unsigned long reset_done [FUSBH200_MAX_ROOT_PORTS];
138
139 /* bit vectors (one bit per port) */
140 unsigned long bus_suspended; /* which ports were
141 already suspended at the start of a bus suspend */
142 unsigned long companion_ports; /* which ports are
143 dedicated to the companion controller */
144 unsigned long owned_ports; /* which ports are
145 owned by the companion during a bus suspend */
146 unsigned long port_c_suspend; /* which ports have
147 the change-suspend feature turned on */
148 unsigned long suspended_ports; /* which ports are
149 suspended */
150 unsigned long resuming_ports; /* which ports have
151 started to resume */
152
153 /* per-HC memory pools (could be per-bus, but ...) */
154 struct dma_pool *qh_pool; /* qh per active urb */
155 struct dma_pool *qtd_pool; /* one or more per qh */
156 struct dma_pool *itd_pool; /* itd per iso urb */
157
158 unsigned random_frame;
159 unsigned long next_statechange;
160 ktime_t last_periodic_enable;
161 u32 command;
162
163 /* SILICON QUIRKS */
164 unsigned need_io_watchdog:1;
165 unsigned fs_i_thresh:1; /* Intel iso scheduling */
166
167 u8 sbrn; /* packed release number */
168
169 /* irq statistics */
170 struct fusbh200_stats stats;
171 # define COUNT(x) do { (x)++; } while (0)
172
173 /* debug files */
174 struct dentry *debug_dir;
175 };
176
177 /* convert between an HCD pointer and the corresponding FUSBH200_HCD */
hcd_to_fusbh200(struct usb_hcd * hcd)178 static inline struct fusbh200_hcd *hcd_to_fusbh200 (struct usb_hcd *hcd)
179 {
180 return (struct fusbh200_hcd *) (hcd->hcd_priv);
181 }
fusbh200_to_hcd(struct fusbh200_hcd * fusbh200)182 static inline struct usb_hcd *fusbh200_to_hcd (struct fusbh200_hcd *fusbh200)
183 {
184 return container_of ((void *) fusbh200, struct usb_hcd, hcd_priv);
185 }
186
187 /*-------------------------------------------------------------------------*/
188
189 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
190
191 /* Section 2.2 Host Controller Capability Registers */
192 struct fusbh200_caps {
193 /* these fields are specified as 8 and 16 bit registers,
194 * but some hosts can't perform 8 or 16 bit PCI accesses.
195 * some hosts treat caplength and hciversion as parts of a 32-bit
196 * register, others treat them as two separate registers, this
197 * affects the memory map for big endian controllers.
198 */
199 u32 hc_capbase;
200 #define HC_LENGTH(fusbh200, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
201 (fusbh200_big_endian_capbase(fusbh200) ? 24 : 0)))
202 #define HC_VERSION(fusbh200, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
203 (fusbh200_big_endian_capbase(fusbh200) ? 0 : 16)))
204 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
205 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
206
207 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
208 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
209 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
210 u8 portroute[8]; /* nibbles for routing - offset 0xC */
211 };
212
213
214 /* Section 2.3 Host Controller Operational Registers */
215 struct fusbh200_regs {
216
217 /* USBCMD: offset 0x00 */
218 u32 command;
219
220 /* EHCI 1.1 addendum */
221 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
222 #define CMD_PARK (1<<11) /* enable "park" on async qh */
223 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
224 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
225 #define CMD_ASE (1<<5) /* async schedule enable */
226 #define CMD_PSE (1<<4) /* periodic schedule enable */
227 /* 3:2 is periodic frame list size */
228 #define CMD_RESET (1<<1) /* reset HC not bus */
229 #define CMD_RUN (1<<0) /* start/stop HC */
230
231 /* USBSTS: offset 0x04 */
232 u32 status;
233 #define STS_ASS (1<<15) /* Async Schedule Status */
234 #define STS_PSS (1<<14) /* Periodic Schedule Status */
235 #define STS_RECL (1<<13) /* Reclamation */
236 #define STS_HALT (1<<12) /* Not running (any reason) */
237 /* some bits reserved */
238 /* these STS_* flags are also intr_enable bits (USBINTR) */
239 #define STS_IAA (1<<5) /* Interrupted on async advance */
240 #define STS_FATAL (1<<4) /* such as some PCI access errors */
241 #define STS_FLR (1<<3) /* frame list rolled over */
242 #define STS_PCD (1<<2) /* port change detect */
243 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
244 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
245
246 /* USBINTR: offset 0x08 */
247 u32 intr_enable;
248
249 /* FRINDEX: offset 0x0C */
250 u32 frame_index; /* current microframe number */
251 /* CTRLDSSEGMENT: offset 0x10 */
252 u32 segment; /* address bits 63:32 if needed */
253 /* PERIODICLISTBASE: offset 0x14 */
254 u32 frame_list; /* points to periodic list */
255 /* ASYNCLISTADDR: offset 0x18 */
256 u32 async_next; /* address of next async queue head */
257
258 u32 reserved1;
259 /* PORTSC: offset 0x20 */
260 u32 port_status;
261 /* 31:23 reserved */
262 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
263 #define PORT_RESET (1<<8) /* reset port */
264 #define PORT_SUSPEND (1<<7) /* suspend port */
265 #define PORT_RESUME (1<<6) /* resume it */
266 #define PORT_PEC (1<<3) /* port enable change */
267 #define PORT_PE (1<<2) /* port enable */
268 #define PORT_CSC (1<<1) /* connect status change */
269 #define PORT_CONNECT (1<<0) /* device connected */
270 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
271
272 u32 reserved2[3];
273
274 /* BMCSR: offset 0x30 */
275 u32 bmcsr; /* Bus Moniter Control/Status Register */
276 #define BMCSR_HOST_SPD_TYP (3<<9)
277 #define BMCSR_VBUS_OFF (1<<4)
278 #define BMCSR_INT_POLARITY (1<<3)
279
280 /* BMISR: offset 0x34 */
281 u32 bmisr; /* Bus Moniter Interrupt Status Register*/
282 #define BMISR_OVC (1<<1)
283
284 /* BMIER: offset 0x38 */
285 u32 bmier; /* Bus Moniter Interrupt Enable Register */
286 #define BMIER_OVC_EN (1<<1)
287 #define BMIER_VBUS_ERR_EN (1<<0)
288 };
289
290 /*-------------------------------------------------------------------------*/
291
292 #define QTD_NEXT(fusbh200, dma) cpu_to_hc32(fusbh200, (u32)dma)
293
294 /*
295 * EHCI Specification 0.95 Section 3.5
296 * QTD: describe data transfer components (buffer, direction, ...)
297 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
298 *
299 * These are associated only with "QH" (Queue Head) structures,
300 * used with control, bulk, and interrupt transfers.
301 */
302 struct fusbh200_qtd {
303 /* first part defined by EHCI spec */
304 __hc32 hw_next; /* see EHCI 3.5.1 */
305 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
306 __hc32 hw_token; /* see EHCI 3.5.3 */
307 #define QTD_TOGGLE (1 << 31) /* data toggle */
308 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
309 #define QTD_IOC (1 << 15) /* interrupt on complete */
310 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
311 #define QTD_PID(tok) (((tok)>>8) & 0x3)
312 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
313 #define QTD_STS_HALT (1 << 6) /* halted on error */
314 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
315 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
316 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
317 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
318 #define QTD_STS_STS (1 << 1) /* split transaction state */
319 #define QTD_STS_PING (1 << 0) /* issue PING? */
320
321 #define ACTIVE_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_ACTIVE)
322 #define HALT_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_HALT)
323 #define STATUS_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_STS)
324
325 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
326 __hc32 hw_buf_hi [5]; /* Appendix B */
327
328 /* the rest is HCD-private */
329 dma_addr_t qtd_dma; /* qtd address */
330 struct list_head qtd_list; /* sw qtd list */
331 struct urb *urb; /* qtd's urb */
332 size_t length; /* length of buffer */
333 } __attribute__ ((aligned (32)));
334
335 /* mask NakCnt+T in qh->hw_alt_next */
336 #define QTD_MASK(fusbh200) cpu_to_hc32 (fusbh200, ~0x1f)
337
338 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
339
340 /*-------------------------------------------------------------------------*/
341
342 /* type tag from {qh,itd,fstn}->hw_next */
343 #define Q_NEXT_TYPE(fusbh200,dma) ((dma) & cpu_to_hc32(fusbh200, 3 << 1))
344
345 /*
346 * Now the following defines are not converted using the
347 * cpu_to_le32() macro anymore, since we have to support
348 * "dynamic" switching between be and le support, so that the driver
349 * can be used on one system with SoC EHCI controller using big-endian
350 * descriptors as well as a normal little-endian PCI EHCI controller.
351 */
352 /* values for that type tag */
353 #define Q_TYPE_ITD (0 << 1)
354 #define Q_TYPE_QH (1 << 1)
355 #define Q_TYPE_SITD (2 << 1)
356 #define Q_TYPE_FSTN (3 << 1)
357
358 /* next async queue entry, or pointer to interrupt/periodic QH */
359 #define QH_NEXT(fusbh200,dma) (cpu_to_hc32(fusbh200, (((u32)dma)&~0x01f)|Q_TYPE_QH))
360
361 /* for periodic/async schedules and qtd lists, mark end of list */
362 #define FUSBH200_LIST_END(fusbh200) cpu_to_hc32(fusbh200, 1) /* "null pointer" to hw */
363
364 /*
365 * Entries in periodic shadow table are pointers to one of four kinds
366 * of data structure. That's dictated by the hardware; a type tag is
367 * encoded in the low bits of the hardware's periodic schedule. Use
368 * Q_NEXT_TYPE to get the tag.
369 *
370 * For entries in the async schedule, the type tag always says "qh".
371 */
372 union fusbh200_shadow {
373 struct fusbh200_qh *qh; /* Q_TYPE_QH */
374 struct fusbh200_itd *itd; /* Q_TYPE_ITD */
375 struct fusbh200_fstn *fstn; /* Q_TYPE_FSTN */
376 __hc32 *hw_next; /* (all types) */
377 void *ptr;
378 };
379
380 /*-------------------------------------------------------------------------*/
381
382 /*
383 * EHCI Specification 0.95 Section 3.6
384 * QH: describes control/bulk/interrupt endpoints
385 * See Fig 3-7 "Queue Head Structure Layout".
386 *
387 * These appear in both the async and (for interrupt) periodic schedules.
388 */
389
390 /* first part defined by EHCI spec */
391 struct fusbh200_qh_hw {
392 __hc32 hw_next; /* see EHCI 3.6.1 */
393 __hc32 hw_info1; /* see EHCI 3.6.2 */
394 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
395 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
396 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
397 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
398 #define QH_LOW_SPEED (1 << 12)
399 #define QH_FULL_SPEED (0 << 12)
400 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
401 __hc32 hw_info2; /* see EHCI 3.6.2 */
402 #define QH_SMASK 0x000000ff
403 #define QH_CMASK 0x0000ff00
404 #define QH_HUBADDR 0x007f0000
405 #define QH_HUBPORT 0x3f800000
406 #define QH_MULT 0xc0000000
407 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
408
409 /* qtd overlay (hardware parts of a struct fusbh200_qtd) */
410 __hc32 hw_qtd_next;
411 __hc32 hw_alt_next;
412 __hc32 hw_token;
413 __hc32 hw_buf [5];
414 __hc32 hw_buf_hi [5];
415 } __attribute__ ((aligned(32)));
416
417 struct fusbh200_qh {
418 struct fusbh200_qh_hw *hw; /* Must come first */
419 /* the rest is HCD-private */
420 dma_addr_t qh_dma; /* address of qh */
421 union fusbh200_shadow qh_next; /* ptr to qh; or periodic */
422 struct list_head qtd_list; /* sw qtd list */
423 struct list_head intr_node; /* list of intr QHs */
424 struct fusbh200_qtd *dummy;
425 struct fusbh200_qh *unlink_next; /* next on unlink list */
426
427 unsigned unlink_cycle;
428
429 u8 needs_rescan; /* Dequeue during giveback */
430 u8 qh_state;
431 #define QH_STATE_LINKED 1 /* HC sees this */
432 #define QH_STATE_UNLINK 2 /* HC may still see this */
433 #define QH_STATE_IDLE 3 /* HC doesn't see this */
434 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
435 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
436
437 u8 xacterrs; /* XactErr retry counter */
438 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
439
440 /* periodic schedule info */
441 u8 usecs; /* intr bandwidth */
442 u8 gap_uf; /* uframes split/csplit gap */
443 u8 c_usecs; /* ... split completion bw */
444 u16 tt_usecs; /* tt downstream bandwidth */
445 unsigned short period; /* polling interval */
446 unsigned short start; /* where polling starts */
447 #define NO_FRAME ((unsigned short)~0) /* pick new start */
448
449 struct usb_device *dev; /* access to TT */
450 unsigned is_out:1; /* bulk or intr OUT */
451 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
452 };
453
454 /*-------------------------------------------------------------------------*/
455
456 /* description of one iso transaction (up to 3 KB data if highspeed) */
457 struct fusbh200_iso_packet {
458 /* These will be copied to iTD when scheduling */
459 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
460 __hc32 transaction; /* itd->hw_transaction[i] |= */
461 u8 cross; /* buf crosses pages */
462 /* for full speed OUT splits */
463 u32 buf1;
464 };
465
466 /* temporary schedule data for packets from iso urbs (both speeds)
467 * each packet is one logical usb transaction to the device (not TT),
468 * beginning at stream->next_uframe
469 */
470 struct fusbh200_iso_sched {
471 struct list_head td_list;
472 unsigned span;
473 struct fusbh200_iso_packet packet [0];
474 };
475
476 /*
477 * fusbh200_iso_stream - groups all (s)itds for this endpoint.
478 * acts like a qh would, if EHCI had them for ISO.
479 */
480 struct fusbh200_iso_stream {
481 /* first field matches fusbh200_hq, but is NULL */
482 struct fusbh200_qh_hw *hw;
483
484 u8 bEndpointAddress;
485 u8 highspeed;
486 struct list_head td_list; /* queued itds */
487 struct list_head free_list; /* list of unused itds */
488 struct usb_device *udev;
489 struct usb_host_endpoint *ep;
490
491 /* output of (re)scheduling */
492 int next_uframe;
493 __hc32 splits;
494
495 /* the rest is derived from the endpoint descriptor,
496 * trusting urb->interval == f(epdesc->bInterval) and
497 * including the extra info for hw_bufp[0..2]
498 */
499 u8 usecs, c_usecs;
500 u16 interval;
501 u16 tt_usecs;
502 u16 maxp;
503 u16 raw_mask;
504 unsigned bandwidth;
505
506 /* This is used to initialize iTD's hw_bufp fields */
507 __hc32 buf0;
508 __hc32 buf1;
509 __hc32 buf2;
510
511 /* this is used to initialize sITD's tt info */
512 __hc32 address;
513 };
514
515 /*-------------------------------------------------------------------------*/
516
517 /*
518 * EHCI Specification 0.95 Section 3.3
519 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
520 *
521 * Schedule records for high speed iso xfers
522 */
523 struct fusbh200_itd {
524 /* first part defined by EHCI spec */
525 __hc32 hw_next; /* see EHCI 3.3.1 */
526 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
527 #define FUSBH200_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
528 #define FUSBH200_ISOC_BUF_ERR (1<<30) /* Data buffer error */
529 #define FUSBH200_ISOC_BABBLE (1<<29) /* babble detected */
530 #define FUSBH200_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
531 #define FUSBH200_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
532 #define FUSBH200_ITD_IOC (1 << 15) /* interrupt on complete */
533
534 #define ITD_ACTIVE(fusbh200) cpu_to_hc32(fusbh200, FUSBH200_ISOC_ACTIVE)
535
536 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
537 __hc32 hw_bufp_hi [7]; /* Appendix B */
538
539 /* the rest is HCD-private */
540 dma_addr_t itd_dma; /* for this itd */
541 union fusbh200_shadow itd_next; /* ptr to periodic q entry */
542
543 struct urb *urb;
544 struct fusbh200_iso_stream *stream; /* endpoint's queue */
545 struct list_head itd_list; /* list of stream's itds */
546
547 /* any/all hw_transactions here may be used by that urb */
548 unsigned frame; /* where scheduled */
549 unsigned pg;
550 unsigned index[8]; /* in urb->iso_frame_desc */
551 } __attribute__ ((aligned (32)));
552
553 /*-------------------------------------------------------------------------*/
554
555 /*
556 * EHCI Specification 0.96 Section 3.7
557 * Periodic Frame Span Traversal Node (FSTN)
558 *
559 * Manages split interrupt transactions (using TT) that span frame boundaries
560 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
561 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
562 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
563 */
564 struct fusbh200_fstn {
565 __hc32 hw_next; /* any periodic q entry */
566 __hc32 hw_prev; /* qh or FUSBH200_LIST_END */
567
568 /* the rest is HCD-private */
569 dma_addr_t fstn_dma;
570 union fusbh200_shadow fstn_next; /* ptr to periodic q entry */
571 } __attribute__ ((aligned (32)));
572
573 /*-------------------------------------------------------------------------*/
574
575 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
576
577 #define fusbh200_prepare_ports_for_controller_suspend(fusbh200, do_wakeup) \
578 fusbh200_adjust_port_wakeup_flags(fusbh200, true, do_wakeup);
579
580 #define fusbh200_prepare_ports_for_controller_resume(fusbh200) \
581 fusbh200_adjust_port_wakeup_flags(fusbh200, false, false);
582
583 /*-------------------------------------------------------------------------*/
584
585 /*
586 * Some EHCI controllers have a Transaction Translator built into the
587 * root hub. This is a non-standard feature. Each controller will need
588 * to add code to the following inline functions, and call them as
589 * needed (mostly in root hub code).
590 */
591
592 static inline unsigned int
fusbh200_get_speed(struct fusbh200_hcd * fusbh200,unsigned int portsc)593 fusbh200_get_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
594 {
595 return (readl(&fusbh200->regs->bmcsr)
596 & BMCSR_HOST_SPD_TYP) >> 9;
597 }
598
599 /* Returns the speed of a device attached to a port on the root hub. */
600 static inline unsigned int
fusbh200_port_speed(struct fusbh200_hcd * fusbh200,unsigned int portsc)601 fusbh200_port_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
602 {
603 switch (fusbh200_get_speed(fusbh200, portsc)) {
604 case 0:
605 return 0;
606 case 1:
607 return USB_PORT_STAT_LOW_SPEED;
608 case 2:
609 default:
610 return USB_PORT_STAT_HIGH_SPEED;
611 }
612 }
613
614 /*-------------------------------------------------------------------------*/
615
616 #define fusbh200_has_fsl_portno_bug(e) (0)
617
618 /*
619 * While most USB host controllers implement their registers in
620 * little-endian format, a minority (celleb companion chip) implement
621 * them in big endian format.
622 *
623 * This attempts to support either format at compile time without a
624 * runtime penalty, or both formats with the additional overhead
625 * of checking a flag bit.
626 *
627 */
628
629 #define fusbh200_big_endian_mmio(e) 0
630 #define fusbh200_big_endian_capbase(e) 0
631
fusbh200_readl(const struct fusbh200_hcd * fusbh200,__u32 __iomem * regs)632 static inline unsigned int fusbh200_readl(const struct fusbh200_hcd *fusbh200,
633 __u32 __iomem * regs)
634 {
635 return readl(regs);
636 }
637
fusbh200_writel(const struct fusbh200_hcd * fusbh200,const unsigned int val,__u32 __iomem * regs)638 static inline void fusbh200_writel(const struct fusbh200_hcd *fusbh200,
639 const unsigned int val, __u32 __iomem *regs)
640 {
641 writel(val, regs);
642 }
643
644 /* cpu to fusbh200 */
cpu_to_hc32(const struct fusbh200_hcd * fusbh200,const u32 x)645 static inline __hc32 cpu_to_hc32 (const struct fusbh200_hcd *fusbh200, const u32 x)
646 {
647 return cpu_to_le32(x);
648 }
649
650 /* fusbh200 to cpu */
hc32_to_cpu(const struct fusbh200_hcd * fusbh200,const __hc32 x)651 static inline u32 hc32_to_cpu (const struct fusbh200_hcd *fusbh200, const __hc32 x)
652 {
653 return le32_to_cpu(x);
654 }
655
hc32_to_cpup(const struct fusbh200_hcd * fusbh200,const __hc32 * x)656 static inline u32 hc32_to_cpup (const struct fusbh200_hcd *fusbh200, const __hc32 *x)
657 {
658 return le32_to_cpup(x);
659 }
660
661 /*-------------------------------------------------------------------------*/
662
fusbh200_read_frame_index(struct fusbh200_hcd * fusbh200)663 static inline unsigned fusbh200_read_frame_index(struct fusbh200_hcd *fusbh200)
664 {
665 return fusbh200_readl(fusbh200, &fusbh200->regs->frame_index);
666 }
667
668 #define fusbh200_itdlen(urb, desc, t) ({ \
669 usb_pipein((urb)->pipe) ? \
670 (desc)->length - FUSBH200_ITD_LENGTH(t) : \
671 FUSBH200_ITD_LENGTH(t); \
672 })
673 /*-------------------------------------------------------------------------*/
674
675 #endif /* __LINUX_FUSBH200_H */
676