| /linux-4.4.14/drivers/video/fbdev/geode/ |
| H A D | display_gx.c | 69 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); gx_set_mode()
76 write_dc(par, DC_DISPLAY_CFG, dcfg); gx_set_mode()
84 write_dc(par, DC_GENERAL_CFG, gcfg); gx_set_mode()
103 write_dc(par, DC_FB_ST_OFFSET, 0); gx_set_mode()
106 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); gx_set_mode()
107 write_dc(par, DC_LINE_SIZE, gx_set_mode()
147 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | gx_set_mode()
149 write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) | gx_set_mode()
151 write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) | gx_set_mode()
154 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | gx_set_mode()
156 write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) | gx_set_mode()
158 write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) | gx_set_mode()
162 write_dc(par, DC_DISPLAY_CFG, dcfg); gx_set_mode()
163 write_dc(par, DC_GENERAL_CFG, gcfg); gx_set_mode()
168 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); gx_set_mode()
182 write_dc(par, DC_PAL_ADDRESS, regno); gx_set_hw_palette_reg()
183 write_dc(par, DC_PAL_DATA, val); gx_set_hw_palette_reg()
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| H A D | suspend_gx.c | 33 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); gx_save_regs()
42 write_dc(par, DC_PAL_ADDRESS, 0); gx_save_regs()
96 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); gx_restore_display_ctlr()
101 write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE | gx_restore_display_ctlr()
109 write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN | gx_restore_display_ctlr()
128 write_dc(par, i, par->dc[i]); gx_restore_display_ctlr()
133 write_dc(par, DC_PAL_ADDRESS, 0); gx_restore_display_ctlr()
135 write_dc(par, DC_PAL_DATA, par->pal[i]); gx_restore_display_ctlr()
203 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); gx_disable_graphics()
204 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] & gx_disable_graphics()
207 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] & gx_disable_graphics()
210 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); gx_disable_graphics()
231 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]); gx_enable_graphics()
233 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]); gx_enable_graphics()
236 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); gx_enable_graphics()
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| H A D | lxfb_ops.c | 199 write_dc(par, DC_GENERAL_CFG, val); lx_graphics_disable()
204 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | lx_graphics_disable()
208 write_dc(par, DC_GENLK_CTL, val); lx_graphics_disable()
211 write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN); lx_graphics_disable()
227 write_dc(par, DC_GENERAL_CFG, gcfg); lx_graphics_disable()
232 write_dc(par, DC_DISPLAY_CFG, val); lx_graphics_disable()
240 write_dc(par, DC_GENERAL_CFG, gcfg); lx_graphics_disable()
357 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); lx_set_mode()
383 write_dc(par, DC_FB_ST_OFFSET, 0); lx_set_mode()
384 write_dc(par, DC_CB_ST_OFFSET, 0); lx_set_mode()
385 write_dc(par, DC_CURS_ST_OFFSET, 0); lx_set_mode()
396 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); lx_set_mode()
397 write_dc(par, DC_IRQ_FILT_CTL, 0); lx_set_mode()
398 write_dc(par, DC_GENLK_CTL, val); lx_set_mode()
414 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN); lx_set_mode()
417 write_dc(par, DC_DV_CTL, val | dv); lx_set_mode()
421 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); lx_set_mode()
422 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3); lx_set_mode()
482 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16)); lx_set_mode()
483 write_dc(par, DC_H_BLANK_TIMING, lx_set_mode()
485 write_dc(par, DC_H_SYNC_TIMING, lx_set_mode()
488 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16)); lx_set_mode()
489 write_dc(par, DC_V_BLANK_TIMING, lx_set_mode()
491 write_dc(par, DC_V_SYNC_TIMING, lx_set_mode()
494 write_dc(par, DC_FB_ACTIVE, lx_set_mode()
501 write_dc(par, DC_DISPLAY_CFG, dcfg); lx_set_mode()
502 write_dc(par, DC_ARB_CFG, 0); lx_set_mode()
503 write_dc(par, DC_GENERAL_CFG, gcfg); lx_set_mode()
506 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); lx_set_mode()
521 write_dc(par, DC_PAL_ADDRESS, regno); lx_set_palette_reg()
522 write_dc(par, DC_PAL_DATA, val); lx_set_palette_reg()
605 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); lx_save_regs()
614 write_dc(par, DC_PAL_ADDRESS, 0); lx_save_regs()
626 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); lx_save_regs()
634 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); lx_save_regs()
679 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); lx_restore_display_ctlr()
685 write_dc(par, i, 0); lx_restore_display_ctlr()
690 write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM); lx_restore_display_ctlr()
708 write_dc(par, i, par->dc[i]); lx_restore_display_ctlr()
713 write_dc(par, DC_PAL_ADDRESS, 0); lx_restore_display_ctlr()
715 write_dc(par, DC_PAL_DATA, par->dc_pal[i]); lx_restore_display_ctlr()
720 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); lx_restore_display_ctlr()
721 write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]); lx_restore_display_ctlr()
722 write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]); lx_restore_display_ctlr()
728 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); lx_restore_display_ctlr()
729 write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]); lx_restore_display_ctlr()
810 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]); lx_restore_regs()
812 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]); lx_restore_regs()
815 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); lx_restore_regs()
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| H A D | lxfb_core.c | 392 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); lxfb_map_video_memory()
393 write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000); lxfb_map_video_memory()
394 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); lxfb_map_video_memory()
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| H A D | gxfb.h | 317 static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) write_dc() function
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| H A D | lxfb.h | 400 static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val) write_dc() function
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| H A D | gxfb_core.c | 274 write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000); gxfb_map_video_memory()
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