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Searched refs:write_aux_reg (Results 1 – 10 of 10) sorted by relevance

/linux-4.4.14/arch/arc/mm/
Dtlb.c111 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
114 write_aux_reg(ARC_REG_TLBPD1HI, 0); in __tlb_entry_erase()
116 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
117 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in __tlb_entry_erase()
126 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
128 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); in tlb_entry_lkup()
181 write_aux_reg(ARC_REG_TLBINDEX, 0xa); in utlb_invalidate()
184 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); in utlb_invalidate()
206 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex); in tlb_entry_insert()
209 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
[all …]
Dcache.c251 write_aux_reg(aux_cmd, paddr); in __cache_line_loop_v2()
294 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
304 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v3()
308 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
312 write_aux_reg(aux_cmd, vaddr); in __cache_line_loop_v3()
369 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
371 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
375 write_aux_reg(aux_cmd, paddr); in __cache_line_loop_v4()
403 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()
419 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); in __after_dc_op()
[all …]
/linux-4.4.14/arch/arc/kernel/
Dperf_event.c94 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_read_counter()
96 write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN); in arc_pmu_read_counter()
203 write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1); in arc_pmu_enable()
211 write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0); in arc_pmu_disable()
244 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_event_set_period()
247 write_aux_reg(ARC_REG_PCT_COUNTL, (u32)value); in arc_pmu_event_set_period()
248 write_aux_reg(ARC_REG_PCT_COUNTH, (value >> 32)); in arc_pmu_event_set_period()
277 write_aux_reg(ARC_REG_PCT_INT_CTRL, in arc_pmu_start()
281 write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */ in arc_pmu_start()
282 write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */ in arc_pmu_start()
[all …]
Dintc-arcv2.c75 write_aux_reg(AUX_IRQ_SELECT, data->irq); in arcv2_irq_mask()
76 write_aux_reg(AUX_IRQ_ENABLE, 0); in arcv2_irq_mask()
81 write_aux_reg(AUX_IRQ_SELECT, data->irq); in arcv2_irq_unmask()
82 write_aux_reg(AUX_IRQ_ENABLE, 1); in arcv2_irq_unmask()
88 write_aux_reg(AUX_IRQ_SELECT, data->irq); in arcv2_irq_enable()
89 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); in arcv2_irq_enable()
96 write_aux_reg(AUX_IRQ_ENABLE, 1); in arcv2_irq_enable()
Dtime.c115 write_aux_reg(AUX_RTC_CTRL, 1); in arc_counter_setup()
160 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); in arc_counter_setup()
161 write_aux_reg(ARC_REG_TIMER1_CNT, 0); in arc_counter_setup()
162 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); in arc_counter_setup()
192 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); in arc_timer_event_setup()
193 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ in arc_timer_event_setup()
195 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); in arc_timer_event_setup()
240 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); in timer_irq_handler()
Dintc-compact.c38 write_aux_reg(AUX_IRQ_LEV, level_mask); in arc_init_IRQ()
61 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_mask()
70 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_unmask()
/linux-4.4.14/arch/arc/include/asm/
Dirqflags-arcv2.h74 write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff); in arch_local_irq_enable()
118 write_aux_reg(AUX_IRQ_HINT, irq); in arc_softirq_trigger()
123 write_aux_reg(AUX_IRQ_HINT, 0); in arc_softirq_clear()
Dmmu_context.h98 write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE); in get_new_mmu_context()
151 write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd); in switch_mm()
Darcregs.h122 #define write_aux_reg(reg_immed, val) \ macro
143 #define write_aux_reg(reg_imm, val) \ macro
189 write_aux_reg(reg, tmp); \
Dmcip.h84 write_aux_reg(ARC_REG_MCIP_WDATA, data); in __mcip_cmd_data()