Searched refs:v7 (Results 1 - 53 of 53) sorted by relevance

/linux-4.4.14/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_opr.h45 volatile void __iomem *dis_shared_mem_addr;/* only v7 */
67 volatile void __iomem *d_min_num_dis;/* only v7 */
68 volatile void __iomem *d_min_first_dis_size;/* only v7 */
69 volatile void __iomem *d_min_second_dis_size;/* only v7 */
70 volatile void __iomem *d_min_third_dis_size;/* only v7 */
71 volatile void __iomem *d_post_filter_luma_dpb0;/* v7 and v8 */
72 volatile void __iomem *d_post_filter_luma_dpb1;/* v7 and v8 */
73 volatile void __iomem *d_post_filter_luma_dpb2;/* only v7 */
74 volatile void __iomem *d_post_filter_chroma_dpb0;/* v7 and v8 */
75 volatile void __iomem *d_post_filter_chroma_dpb1;/* v7 and v8 */
76 volatile void __iomem *d_post_filter_chroma_dpb2;/* only v7 */
95 volatile void __iomem *d_nal_start_options;/* v7 and v8 */
104 volatile void __iomem *d_dynamic_dpb_flag_upper;/* v7 and v8 */
105 volatile void __iomem *d_dynamic_dpb_flag_lower;/* v7 and v8 */
116 volatile void __iomem *d_display_luma_crc;/* v7 and v8 */
117 volatile void __iomem *d_display_chroma0_crc;/* v7 and v8 */
144 volatile void __iomem *d_vc1_info;/* v7 and v8 */
155 volatile void __iomem *d_metadata_addr_mvcvui;/* v7 and v8 */
156 volatile void __iomem *d_metadata_size_mvcvui;/* v7 and v8 */
162 volatile void __iomem *d_display_recovery_sei_info;/* v7 and v8 */
163 volatile void __iomem *d_decoded_recovery_sei_info;/* v7 and v8 */
164 volatile void __iomem *d_display_first_addr;/* only v7 */
165 volatile void __iomem *d_display_second_addr;/* only v7 */
166 volatile void __iomem *d_display_third_addr;/* only v7 */
167 volatile void __iomem *d_decoded_first_addr;/* only v7 */
168 volatile void __iomem *d_decoded_second_addr;/* only v7 */
169 volatile void __iomem *d_decoded_third_addr;/* only v7 */
170 volatile void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */
171 volatile void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */
186 volatile void __iomem *e_rc_qp_bound_pb;/* v7 and v8 */
201 volatile void __iomem *e_ir_buffer_addr;/* v7 and v8 */
204 volatile void __iomem *e_source_third_plane_addr;/* v7 and v8 */
205 volatile void __iomem *e_source_first_plane_stride;/* v7 and v8 */
206 volatile void __iomem *e_source_second_plane_stride;/* v7 and v8 */
207 volatile void __iomem *e_source_third_plane_stride;/* v7 and v8 */
229 volatile void __iomem *e_encoded_source_third_plane_addr;/* v7 and v8 */
244 volatile void __iomem *e_h264_options_2;/* v7 and v8 */
258 volatile void __iomem *e_h264_nal_control;/* v7 and v8 */
264 volatile void __iomem *e_vp8_options;/* v7 and v8 */
265 volatile void __iomem *e_vp8_filter_options;/* v7 and v8 */
266 volatile void __iomem *e_vp8_golden_frame_option;/* v7 and v8 */
267 volatile void __iomem *e_vp8_num_t_layer;/* v7 and v8 */
268 volatile void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */
269 volatile void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
270 volatile void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
H A Dregs-mfc-v7.h17 /* Additional features of v7 */
20 /* Additional registers for v7 */
H A Dregs-mfc-v8.h16 #include "regs-mfc-v7.h"
H A Ds5p_mfc.c1441 .fw_name[0] = "s5p-mfc-v7.fw",
1482 .name = "s5p-mfc-v7",
1500 .compatible = "samsung,mfc-v7",
H A Ds5p_mfc_opr_v6.c1451 /* Set stride lengths for v7 & above */ s5p_mfc_init_encode_v6()
2192 /* Initialize registers used in MFC v7+ */ s5p_mfc_init_regs_v6_plus()
/linux-4.4.14/arch/arm64/crypto/
H A Daes-modes.S213 ld1 {v7.16b}, [x5] /* get iv */
225 eor v0.16b, v0.16b, v7.16b
227 mov v7.16b, v3.16b
236 eor v0.16b, v0.16b, v7.16b
238 ld1 {v7.16b}, [x1], #16 /* reload 1 ct block */
252 eor v0.16b, v0.16b, v7.16b /* xor with iv => pt */
253 mov v7.16b, v1.16b /* ct is next iv */
308 dup v7.4s, w5
310 add v7.4s, v7.4s, v8.4s
312 rev32 v8.16b, v7.16b
318 ld1 {v5.16b-v7.16b}, [x1], #48 /* get 3 input blocks */
323 eor v2.16b, v7.16b, v2.16b
404 next_tweak v4, v4, v7, v8
411 next_tweak v5, v4, v7, v8
419 next_tweak v4, v5, v7, v8
426 next_tweak v5, v4, v7, v8
428 next_tweak v6, v5, v7, v8
431 next_tweak v7, v6, v7, v8
432 eor v3.16b, v3.16b, v7.16b
434 eor v3.16b, v3.16b, v7.16b
439 mov v4.16b, v7.16b
455 next_tweak v4, v4, v7, v8
476 next_tweak v4, v4, v7, v8
483 next_tweak v5, v4, v7, v8
491 next_tweak v4, v5, v7, v8
498 next_tweak v5, v4, v7, v8
500 next_tweak v6, v5, v7, v8
503 next_tweak v7, v6, v7, v8
504 eor v3.16b, v3.16b, v7.16b
506 eor v3.16b, v3.16b, v7.16b
511 mov v4.16b, v7.16b
527 next_tweak v4, v4, v7, v8
/linux-4.4.14/arch/arm/mach-mvebu/
H A DMakefile10 obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o
/linux-4.4.14/arch/arm/mm/
H A DMakefile37 obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
43 obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
48 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
66 obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
70 AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
95 obj-$(CONFIG_CPU_V7) += proc-v7.o
99 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
H A Dcache-tauros2.c27 * When Tauros2 is used on a CPU that supports the v7 hierarchical
28 * cache operations, the cache handling code in proc-v7.S takes care
32 * being used on a pre-v7 CPU, and we only need to build support for
34 * configured to support a pre-v7 CPU.
234 * Check whether this CPU has support for the v7 hierarchical tauros2_internal_init()
235 * cache ops. (PJ4 is in its v7 personality mode if the MMFR3 tauros2_internal_init()
236 * register indicates support for the v7 hierarchical cache tauros2_internal_init()
240 * implement the v7 cache ops but are only ARMv6 CPUs (due to tauros2_internal_init()
H A Dproc-v7-3level.S2 * arch/arm/mm/proc-v7-3level.S
7 * based on arch/arm/mm/proc-v7-2level.S
H A Dproc-v7.S2 * linux/arch/arm/mm/proc-v7.S
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
492 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
504 string cpu_elf_name, "v7"
510 * Standard v7 proc info content
H A Dproc-v7-2level.S2 * arch/arm/mm/proc-v7-2level.S
H A Dcache-v7.S2 * linux/arch/arm/mm/cache-v7.S
448 define_cache_functions v7
H A Dmmu.c564 * v6/v7 kernels), so we must use a separate memory type for user build_mem_type_table()
/linux-4.4.14/arch/unicore32/lib/
H A Dbacktrace.S119 .Ldumpstm: stm.w (instr, reg, stack, v7, lr), [sp-]
123 mov v7, #0
131 add v7, v7, #1
132 cxor.a v7, #6
133 cmoveq v7, #1
150 cxor.a v7, #0
154 201: ldm.w (instr, reg, stack, v7, pc), [sp]+
/linux-4.4.14/arch/arm/include/asm/
H A Dcachetype.h26 * - v7+ VIPT never aliases on D-side
H A Dglue-pf.h23 * v7 - ARMv7: IFSR and IFAR
H A Dswitch_to.h7 * For v7 SMP cores running a preemptible kernel we may be pre-empted
H A Dpgtable-2level-hwdef.h23 #define PMD_PXNTABLE (_AT(pmdval_t, 1) << 2) /* v7 */
31 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 0) /* v7 */
H A Dglue-cache.h116 # define _CACHE v7
H A Dcacheflush.h45 * Currently only needed for cache-v6.S and cache-v7.S, see
56 * Only needed from v7 onwards, falls back to flush_cache_all()
H A Dassembler.h315 * setmode is used to assert to be in svc mode during boot. For v7-M
/linux-4.4.14/drivers/char/mwave/
H A Dmwavedd.h109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
122 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7)
/linux-4.4.14/drivers/cpuidle/
H A Dcpuidle-mvebu-v7.c138 MODULE_DESCRIPTION("Marvell EBU v7 cpuidle driver");
/linux-4.4.14/arch/arm/kernel/
H A Dhead-nommu.S194 /* Probe for v7 PMSA compliance */
197 teq r0, #(MMFR0_PMSAv7) @ PMSA v7
198 bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA
H A Dentry-armv.S522 * The following code won't get run unless the running CPU really is v7, so
H A Dhw_breakpoint.c934 * v7 debug contains save and restore registers so that debug state reset_ctrl_regs()
/linux-4.4.14/fs/sysv/
H A Dsuper.c507 /* Try PC/IX, v7/x86 */ v7_fill_super()
553 .name = "v7",
558 MODULE_ALIAS_FS("v7");
559 MODULE_ALIAS("v7");
/linux-4.4.14/arch/powerpc/lib/
H A Dcopyuser_power7.S436 err4; lvx v7,r0,r4
445 err4; stvx v7,r0,r3
621 err4; lvx v7,r0,r4
622 VPERM(v8,v0,v7,v16)
624 VPERM(v9,v7,v6,v16)
H A Dmemcpy_power7.S369 lvx v7,r0,r4
378 stvx v7,r0,r3
555 lvx v7,r0,r4
556 VPERM(v8,v0,v7,v16)
558 VPERM(v9,v7,v6,v16)
/linux-4.4.14/tools/testing/selftests/powerpc/copyloops/
H A Dcopyuser_power7.S436 err4; lvx v7,r0,r4
445 err4; stvx v7,r0,r3
621 err4; lvx v7,r0,r4
622 VPERM(v8,v0,v7,v16)
624 VPERM(v9,v7,v6,v16)
H A Dmemcpy_power7.S369 lvx v7,r0,r4
378 stvx v7,r0,r3
555 lvx v7,r0,r4
556 VPERM(v8,v0,v7,v16)
558 VPERM(v9,v7,v6,v16)
/linux-4.4.14/drivers/mtd/nand/brcmnand/
H A Dbrcmnand.c282 /* BRCMNAND v6.0 - v7.1 */
312 /* BRCMNAND v7.1 */
350 /* Per chip-select offsets for v7.1 */
359 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
378 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
380 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
390 /* Only for pre-v7.1 (with no CFG_EXT register) */
394 /* Only for v7.1+ (with CFG_EXT register) */
465 /* >= v7.1 use nice power-of-2 values! */ brcmnand_revision_init()
2125 { .compatible = "brcm,brcmnand-v7.0" },
2126 { .compatible = "brcm,brcmnand-v7.1" },
/linux-4.4.14/arch/unicore32/include/asm/
H A Dcacheflush.h43 * Currently only needed for cache-v6.S and cache-v7.S, see
/linux-4.4.14/arch/arm64/kernel/
H A Dkgdb.c69 { "v7", 16, -1 },
/linux-4.4.14/arch/arm/mach-exynos/
H A Dexynos.c300 "samsung,mfc-v7", exynos_reserve()
/linux-4.4.14/arch/sparc/math-emu/
H A Dmath_32.c100 #define FSQRTS 0x029 /* v7 */
101 #define FSQRTD 0x02a /* v7 */
/linux-4.4.14/arch/arm/kvm/
H A Dinterrupts.S41 * inside the inner-shareable domain (which is the case for all v7
46 * As v7 does not support flushing per IPA, just nuke the whole TLB
H A Dmmu.c59 * kvm_flush_remote_tlbs() - flush all VM TLB entries for v7/8
/linux-4.4.14/include/linux/
H A Dsysv_fs.h152 /* This is not a hard limit, nor enforced by v7 kernel. It's actually just
/linux-4.4.14/arch/arm/boot/compressed/
H A Dhead.S842 * On v7-M the processor id is located in the V7M_SCB_CPUID
844 * v7-M (if existant at all) we just return early here.
847 * use cp15 registers that are not implemented on v7-M.
/linux-4.4.14/arch/s390/include/asm/
H A Dvx-insn.h117 .ifc \vxr,%v7
/linux-4.4.14/drivers/video/fbdev/
H A Dmacfb.c712 * Note: these first four have the v7 DAFB, which is macfb_init()
/linux-4.4.14/arch/arm/boot/dts/
H A DMakefile590 sun4i-a10-chuwi-v7-cw0825.dtb \
/linux-4.4.14/arch/powerpc/include/asm/
H A Dppc_asm.h647 #define v7 7 macro
/linux-4.4.14/net/irda/irnet/
H A Dirnet.h189 * v7 - 22.08.01 - Jean II
/linux-4.4.14/lib/mpi/
H A Dlonglong.h1074 /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
/linux-4.4.14/net/ceph/
H A Dosdmap.c743 * to struct_v of the client_data section for new (v7 and above)
/linux-4.4.14/arch/arm/probes/
H A Ddecode-arm.c250 /* Deprecated on ARMv6 and may be UNDEFINED on v7 */
/linux-4.4.14/drivers/video/fbdev/sis/
H A Dsis_main.c4310 u8 reg, v1, v2, v3, v4, v5, v6, v7, v8; sisfb_post_sis300() local
4362 v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00; sisfb_post_sis300()
4371 v7 = bios[memtype + 48]; sisfb_post_sis300()
4382 SiS_SetReg(SISSR, 0x1b, v7); sisfb_post_sis300()
/linux-4.4.14/drivers/iommu/
H A Darm-smmu.c24 * - v7/v8 long-descriptor format
/linux-4.4.14/arch/arm/mach-omap2/
H A Dmux34xx.c1256 _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmfmac/
H A Dsdio.c352 __le32 r10; /* sl/v7 */

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