| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 38 mpll, upll, enumerator in enum:s3c2410_plls
199 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
214 /* uclk is fed from the unmodified upll */
215 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
265 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
295 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
299 DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
314 ALIAS(CAMIF, NULL, "camif-upll"),
319 PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
332 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
335 PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
387 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl; s3c2410_common_clk_init()
398 * upll following the same scheme as the s3c2410 plls s3c2410_common_clk_init()
402 s3c244x_common_plls[upll].rate_table = s3c2410_common_clk_init()
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| H A D | clk-s3c2410-dclk.c | 143 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
145 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
148 static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
150 static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
153 static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
155 static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
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| H A D | clk-s3c2412.c | 32 mpll, upll, enumerator in enum:s3c2412_plls
128 PNAME(usysclk_p) = { "urefclk", "upll" };
149 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
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| H A D | clk-s3c2443.c | 313 ALIAS(SCLK_CAM, NULL, "camif-upll"),
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| /linux-4.4.14/drivers/clk/imx/ |
| H A D | clk-imx31.c | 47 static const char *csi_sel[] = { "upll", "spll", };
48 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
51 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator in enum:mx31_clks
88 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); _mx31_clocks_init()
94 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); _mx31_clocks_init()
99 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); _mx31_clocks_init()
141 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); _mx31_clocks_init()
145 clk_set_parent(clk[csi], clk[upll]); _mx31_clocks_init()
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| H A D | clk-imx25.c | 59 static const char *per_sel_clks[] = { "ahb", "upll", };
66 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator in enum:mx25_clks
107 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); __mx25_clocks_init()
112 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); __mx25_clocks_init()
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