Searched refs:tmdsck (Results 1 – 2 of 2) sorted by relevance
77 u32 val, tmdsck, idf, odf, pllctrl = 0; in sti_hdmi_tx3g4c28phy_start() local100 tmdsck = ckpxpll; in sti_hdmi_tx3g4c28phy_start()103 if (tmdsck > 340000000) { in sti_hdmi_tx3g4c28phy_start()104 DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck); in sti_hdmi_tx3g4c28phy_start()136 if (tmdsck > 165000000) in sti_hdmi_tx3g4c28phy_start()145 if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) && in sti_hdmi_tx3g4c28phy_start()146 (hdmiphy_config[i].max_tmds_freq >= tmdsck)) { in sti_hdmi_tx3g4c28phy_start()
205 u32 val, tmdsck, freqvco, pllctrl = 0; in sti_hdmi_tx3g0c55phy_start() local214 tmdsck = ckpxpll; in sti_hdmi_tx3g0c55phy_start()228 freqvco = tmdsck * 10; in sti_hdmi_tx3g0c55phy_start()268 if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) && in sti_hdmi_tx3g0c55phy_start()269 (hdmiphy_config[i].max_tmds_freq >= tmdsck)) { in sti_hdmi_tx3g0c55phy_start()