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Searched refs:tiling (Results 1 – 13 of 13) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/tegra/
Ddc.c65 struct tegra_bo_tiling tiling; member
319 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
321 switch (window->tiling.mode) { in tegra_dc_setup_window()
338 switch (window->tiling.mode) { in tegra_dc_setup_window()
459 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
515 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
529 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_plane_atomic_check()
533 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
585 window.tiling = state->tiling; in tegra_plane_atomic_update()
Dfb.c50 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
55 *tiling = fb->planes[0]->tiling; in tegra_fb_get_tiling()
Dgem.h47 struct tegra_bo_tiling tiling; member
Ddrm.h187 struct tegra_bo_tiling tiling; member
268 struct tegra_bo_tiling *tiling);
Ddrm.c683 bo->tiling.mode = mode; in tegra_gem_set_tiling()
684 bo->tiling.value = value; in tegra_gem_set_tiling()
705 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
718 args->value = bo->tiling.value; in tegra_gem_get_tiling()
Dgem.c270 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
/linux-4.4.14/drivers/gpu/drm/i915/
Di915_gpu_error.c55 static const char *tiling_flag(int tiling) in tiling_flag() argument
57 switch (tiling) { in tiling_flag()
206 err_puts(m, tiling_flag(err->tiling)); in print_error_buffers()
709 err->tiling = obj->tiling_mode; in capture_bo()
Dintel_pm.c3011 uint64_t tiling, uint32_t latency) in skl_wm_method2() argument
3022 if (tiling == I915_FORMAT_MOD_Y_TILED || in skl_wm_method2()
3023 tiling == I915_FORMAT_MOD_Yf_TILED) { in skl_wm_method2()
3099 p->plane[0].tiling = fb->modifier[0]; in skl_compute_wm_pipe_parameters()
3104 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; in skl_compute_wm_pipe_parameters()
3162 p_params->tiling, in skl_compute_plane_wm()
3168 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || in skl_compute_plane_wm()
3169 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { in skl_compute_plane_wm()
3197 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || in skl_compute_plane_wm()
3198 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) in skl_compute_plane_wm()
[all …]
Dintel_drv.h287 unsigned int tiling; member
608 u64 tiling; member
Dintel_display.c2558 obj->tiling_mode = plane_config->tiling; in intel_alloc_initial_plane_obj()
8057 plane_config->tiling = I915_TILING_X; in i9xx_get_initial_plane_config()
8068 if (plane_config->tiling) in i9xx_get_initial_plane_config()
9089 u32 val, base, offset, stride_mult, tiling; in skylake_get_initial_plane_config() local
9115 tiling = val & PLANE_CTL_TILED_MASK; in skylake_get_initial_plane_config()
9116 switch (tiling) { in skylake_get_initial_plane_config()
9121 plane_config->tiling = I915_TILING_X; in skylake_get_initial_plane_config()
9131 MISSING_CASE(tiling); in skylake_get_initial_plane_config()
9218 plane_config->tiling = I915_TILING_X; in ironlake_get_initial_plane_config()
9232 if (plane_config->tiling) in ironlake_get_initial_plane_config()
Di915_drv.h593 u32 tiling:2; member
/linux-4.4.14/Documentation/DocBook/
Dgpu.xml.db622 API-i915-gem-set-tiling
623 API-i915-gem-get-tiling
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
Dcom.fuc518 // to correctly handle tiling.