/linux-4.4.14/drivers/gpu/drm/i915/ |
H A D | i915_gem_tiling.c | 35 * DOC: buffer object tiling 41 * object, and hence it also doesn't care about tiling or swizzling. There's two 44 * - For X and Y tiling the hardware provides detilers for CPU access, so called 46 * these, and therefore userspace must tell the kernel the object tiling if it 51 * and hence now the tiling. Note that on a subset of platforms with 55 * Since neither of this applies for new tiling layouts on modern platforms like 56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. 61 /* Check pitch constriants for all chips & tiling formats */ 116 /* Is the current GTT allocation valid for the change in tiling? */ 147 * i915_gem_set_tiling - IOCTL handler to set tiling mode 152 * Sets the tiling mode of an object, returning the required swizzling of 218 * tiling mode. Otherwise we can just leave it alone, but i915_gem_set_tiling() 223 * After updating the tiling parameters, we then flag whether i915_gem_set_tiling() 276 * i915_gem_get_tiling - IOCTL handler to get tiling mode 281 * Returns the current tiling mode and required bit 6 swizzling for the object. 314 DRM_ERROR("unknown tiling mode\n"); i915_gem_get_tiling()
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H A D | i915_gem_fence.c | 42 * have their own tiling state bits and don't need fences. 44 * Also note that fences only support X and Y tiling and hence can't be used for 45 * the fancier new tiling formats like W, Ys and Yf. 205 "bogus fence setup with stride: 0x%x, tiling mode: %i\n", i915_gem_write_fence() 255 * a tiling change if we ever need to acquire one. i915_gem_object_fence_lost() 358 * and tiling format. 375 /* Have we updated the tiling parameters upon the object and so i915_gem_object_get_fence() 482 * Commit delayed tiling changes if we have an object still i915_gem_restore_fences() 495 * DOC: tiling swizzling details 497 * The idea behind tiling is to increase cache hit rates by rearranging 526 * If we don't have interleaved memory, all tiling is safe and no swizzling is 653 "Disabling tiling.\n"); i915_gem_detect_bit_6_swizzle() 694 * the get-tiling-ioctl by reporting the physical swizzle i915_gem_detect_bit_6_swizzle()
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H A D | i915_gpu_error.c | 55 static const char *tiling_flag(int tiling) tiling_flag() argument 57 switch (tiling) { tiling_flag() 206 err_puts(m, tiling_flag(err->tiling)); print_error_buffers() 651 /* Simply ignore tiling or any overlapping fence. i915_error_object_create() 709 err->tiling = obj->tiling_mode; capture_bo()
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H A D | intel_atomic_plane.c | 160 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n"); intel_plane_atomic_check()
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H A D | intel_pm.c | 3011 uint64_t tiling, uint32_t latency) skl_wm_method2() 3022 if (tiling == I915_FORMAT_MOD_Y_TILED || skl_wm_method2() 3023 tiling == I915_FORMAT_MOD_Yf_TILED) { skl_wm_method2() 3099 p->plane[0].tiling = fb->modifier[0]; skl_compute_wm_pipe_parameters() 3104 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; skl_compute_wm_pipe_parameters() 3162 p_params->tiling, skl_compute_plane_wm() 3168 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || skl_compute_plane_wm() 3169 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { skl_compute_plane_wm() 3197 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || skl_compute_plane_wm() 3198 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) skl_compute_plane_wm() 3669 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; skl_update_sprite_wm() 3681 * matter for watermarks if we assume no tiling in that case. skl_update_sprite_wm() 3684 intel_plane->wm.tiling = fb->modifier[0]; skl_update_sprite_wm() 3009 skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, uint32_t horiz_pixels, uint8_t bytes_per_pixel, uint64_t tiling, uint32_t latency) skl_wm_method2() argument
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H A D | i915_drv.h | 593 u32 tiling:2; member in struct:drm_i915_error_state::drm_i915_error_buffer 1324 /** Bit 6 swizzling required for X tiling */ 1326 /** Bit 6 swizzling required for Y tiling */ 2081 * Current tiling mode for the object. 2085 * Whether the tiling parameters for the currently associated fence 2087 * tiling changes we also treat the unfenced register, the register 2144 /** Current tiling stride for the object, if it's tiled. */ 2147 /** References from framebuffers, locks out tiling changes. */ 2569 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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H A D | intel_drv.h | 287 unsigned int tiling; member in struct:intel_initial_plane_config 608 u64 tiling; member in struct:intel_plane_wm_parameters
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H A D | intel_display.c | 2361 "Y tiling bo slipped through, driver bug!\n")) intel_pin_and_fence_fb_obj() 2558 obj->tiling_mode = plane_config->tiling; intel_alloc_initial_plane_obj() 2937 /* No need to check for old gens and Y tiling since this is intel_fb_stride_alignment() 8057 plane_config->tiling = I915_TILING_X; i9xx_get_initial_plane_config() 8068 if (plane_config->tiling) i9xx_get_initial_plane_config() 9089 u32 val, base, offset, stride_mult, tiling; skylake_get_initial_plane_config() local 9115 tiling = val & PLANE_CTL_TILED_MASK; skylake_get_initial_plane_config() 9116 switch (tiling) { skylake_get_initial_plane_config() 9121 plane_config->tiling = I915_TILING_X; skylake_get_initial_plane_config() 9131 MISSING_CASE(tiling); skylake_get_initial_plane_config() 9218 plane_config->tiling = I915_TILING_X; ironlake_get_initial_plane_config() 9232 if (plane_config->tiling) ironlake_get_initial_plane_config() 11499 /* vlv: DISPLAY_FLIP fails to change tiling */ intel_crtc_page_flip() 11644 /* Update watermarks on tiling changes. */ intel_wm_need_update() 14329 /* Enforce that fb modifier and tiling mode match, but only for intel_framebuffer_init() 14340 DRM_DEBUG("No Y tiling for legacy addfb\n"); intel_framebuffer_init() 14350 DRM_DEBUG("Unsupported tiling 0x%llx!\n", intel_framebuffer_init() 14383 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", intel_framebuffer_init()
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H A D | i915_debugfs.c | 2165 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", i915_swizzle_info() 2167 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", i915_swizzle_info()
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H A D | i915_gem.c | 1991 /* Previous chips need a power-of-two fence region when tiling */ i915_gem_get_gtt_size()
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/linux-4.4.14/drivers/gpu/drm/tegra/ |
H A D | gem.h | 47 struct tegra_bo_tiling tiling; member in struct:tegra_bo
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H A D | fb.c | 50 struct tegra_bo_tiling *tiling) tegra_fb_get_tiling() 55 *tiling = fb->planes[0]->tiling; tegra_fb_get_tiling() 49 tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_bo_tiling *tiling) tegra_fb_get_tiling() argument
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H A D | dc.c | 65 struct tegra_bo_tiling tiling; member in struct:tegra_plane_state 319 unsigned long height = window->tiling.value; tegra_dc_setup_window() 321 switch (window->tiling.mode) { tegra_dc_setup_window() 338 switch (window->tiling.mode) { tegra_dc_setup_window() 459 copy->tiling = state->tiling; tegra_plane_atomic_duplicate_state() 515 struct tegra_bo_tiling *tiling = &plane_state->tiling; tegra_plane_atomic_check() local 529 err = tegra_fb_get_tiling(state->fb, tiling); tegra_plane_atomic_check() 533 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && tegra_plane_atomic_check() 585 window.tiling = state->tiling; tegra_plane_atomic_update()
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H A D | drm.h | 187 struct tegra_bo_tiling tiling; member in struct:tegra_dc_window 268 struct tegra_bo_tiling *tiling);
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H A D | drm.c | 683 bo->tiling.mode = mode; tegra_gem_set_tiling() 684 bo->tiling.value = value; tegra_gem_set_tiling() 705 switch (bo->tiling.mode) { tegra_gem_get_tiling() 718 args->value = bo->tiling.value; tegra_gem_get_tiling()
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H A D | gem.c | 270 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; tegra_bo_create()
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/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | radeon_drv.c | 49 * - 2.1.0 - add square tiling interface 54 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 55 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 57 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 58 * 2.10.0 - fusion 2D tiling 62 * 2.14.0 - add evergreen tiling informations 81 * 2.33.0 - Add SI tiling mode array query 82 * 2.34.0 - Add CIK tiling mode array query 84 * 2.36.0 - Fix CIK DCE tiling setup 87 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
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H A D | radeon_fb.c | 158 dev_err(rdev->dev, "FB failed to set tiling flags\n"); radeonfb_create_pinned_object()
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H A D | ni_dma.c | 41 * has support for tiling/detiling of buffers.
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H A D | r600_cs.c | 388 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, r600_cs_track_validate_cb() 406 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, r600_cs_track_validate_cb() 584 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, r600_cs_track_validate_db() 597 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, r600_cs_track_validate_db()
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H A D | r600_dma.c | 40 * has support for tiling/detiling of buffers.
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H A D | radeon_kms.c | 211 * drivers. Examples include: pci device id, pipeline parms, tiling params, 293 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); radeon_info_ioctl()
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H A D | radeon_state.c | 1833 /* texture micro tiling in use, minimum texture width is thus 16 bytes. radeon_cp_dispatch_texture() 1837 Thus, tiling manually in this case. Additionally, need to special radeon_cp_dispatch_texture() 3142 DRM_DEBUG("color tiling disabled\n"); radeon_cp_setparam() 3148 DRM_DEBUG("color tiling enabled\n"); radeon_cp_setparam()
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H A D | ni.c | 1050 /* setup tiling info dword. gb_addr_config is not adequate since it does cayman_gpu_init() 1051 * not have bank info, so create a custom tiling dword. cayman_gpu_init()
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H A D | r600_cp.c | 836 /* setup tiling, simd, pipe config */ r600_gfx_init() 1486 /* setup tiling, simd, pipe config */ r700_gfx_init()
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H A D | radeon_drv.h | 86 * 1.14- Add support for color tiling 88 * 1.15- Add support for texture micro tiling
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H A D | cik_sdma.c | 51 * things. It also has support for tiling/detiling of
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H A D | cik.c | 2334 * cik_tiling_mode_table_init - init the hw tiling table 2338 * Starting with SI, the tiling setup is done globally in a 2339 * set of 32 tiling modes. Rather than selecting each set of 2341 * which index in the tiling table we want to use, and the 3553 * Configures the 3D engine and tiling configuration 3708 /* setup tiling info dword. gb_addr_config is not adequate since it does cik_gpu_init() 3709 * not have bank info, so create a custom tiling dword. cik_gpu_init()
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H A D | rv770.c | 1296 /* setup tiling, simd, pipe config */ rv770_gpu_init()
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H A D | atombios_crtc.c | 1331 /* XXX need to know more about the surface tiling mode */ dce4_crtc_do_set_base()
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H A D | r600d.h | 47 /* tiling bits */
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H A D | evergreen.c | 3497 /* setup tiling info dword. gb_addr_config is not adequate since it does evergreen_gpu_init() 3498 * not have bank info, so create a custom tiling dword. evergreen_gpu_init()
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H A D | si.c | 3234 /* setup tiling info dword. gb_addr_config is not adequate since it does si_gpu_init() 3235 * not have bank info, so create a custom tiling dword. si_gpu_init()
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H A D | r100.c | 3108 /* setting pitch to 0 disables tiling */ r100_set_surface_reg()
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H A D | r600.c | 2073 /* Setup tiling */ r600_gpu_init()
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/linux-4.4.14/include/uapi/drm/ |
H A D | drm_fourcc.h | 174 * Intel X-tiling layout 188 * Intel Y-tiling layout 203 * Intel Yf-tiling layout
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H A D | i915_drm.h | 874 /** Handle of the buffer to have its tiling state updated */ 882 * kernel on successful return with the actual chosen tiling layout. 884 * The tiling mode may be demoted to I915_TILING_NONE when the system 905 /** Handle of the buffer to get tiling state for. */ 909 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
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H A D | drm_mode.h | 383 * different tiling/swizzling pattern on different planes. 389 __u64 modifier[4]; /* ie, tiling, compressed (per plane) */
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H A D | amdgpu_drm.h | 235 /** family specific tiling info */
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H A D | radeon_drm.h | 768 #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
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/linux-4.4.14/drivers/gpu/drm/nouveau/ |
H A D | nouveau_drm.h | 154 /* nv10-nv40 tiling regions */
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H A D | nouveau_bo.c | 42 * NV10-NV40 tiling helpers
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/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/ |
H A D | arb.c | 147 + 5 /* tiling pipeline */ nv10_calc_arb()
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/linux-4.4.14/drivers/video/fbdev/aty/ |
H A D | radeonfb.h | 177 /* Surface/tiling registers */
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H A D | radeon_pm.c | 1752 /* Clear tiling, reset swappers */ radeon_reinitialize_M10() 2003 /* Clear tiling, reset swappers */ radeon_reinitialize_M9P()
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/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_fb.c | 149 dev_err(adev->dev, "FB failed to set tiling flags\n"); amdgpufb_create_pinned_object()
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H A D | amdgpu_kms.c | 156 * drivers. Examples include: pci device id, pipeline parms, tiling params,
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H A D | gfx_v7_0.c | 997 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 1001 * Starting with SI, the tiling setup is done globally in a 1002 * set of 32 tiling modes. Rather than selecting each set of 1004 * which index in the tiling table we want to use, and the 2057 * Configures the 3D engine and tiling configuration
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H A D | cik_sdma.c | 82 * things. It also has support for tiling/detiling of
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H A D | sdma_v2_4.c | 88 * things. It also has support for tiling/detiling of
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H A D | sdma_v3_0.c | 152 * things. It also has support for tiling/detiling of
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/linux-4.4.14/include/drm/ |
H A D | drm_dp_mst_helper.h | 90 struct edid *cached_edid; /* for DP logical ports - make tiling work */
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/linux-4.4.14/drivers/video/fbdev/ |
H A D | gbefb.c | 742 normal tiling linear gbefb_set_par()
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/linux-4.4.14/drivers/media/usb/gspca/ |
H A D | sn9c2028.c | 745 * Above is changed from OEM 0x0b. Fixes Bayer tiling. start_vivitar_cam()
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/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | ctxnv50.c | 1426 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ nv50_gr_construct_gene_m2mf() 1433 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ nv50_gr_construct_gene_m2mf()
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/linux-4.4.14/include/drm/ttm/ |
H A D | ttm_bo_driver.h | 417 * can do tiling things */
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/linux-4.4.14/drivers/video/fbdev/intelfb/ |
H A D | intelfbdrv.c | 1205 /* Good pitches to allow tiling. Don't care about pitches < 1024. */ intelfb_check_var()
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/linux-4.4.14/drivers/video/fbdev/nvidia/ |
H A D | nv_hw.c | 450 mclks += 5; /* ap_hp_req tiling pipeline */ nv10CalcArbitration()
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/linux-4.4.14/drivers/video/fbdev/riva/ |
H A D | riva_hw.c | 884 mclks += 5; /* ap_hp_req tiling pipeline */ nv10CalcArbitration()
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/linux-4.4.14/drivers/media/platform/coda/ |
H A D | coda-common.c | 1126 * macroblock tiling only works for to NV12 pixel format. set_default_params()
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/linux-4.4.14/drivers/video/fbdev/sis/ |
H A D | sis_main.c | 4640 /* No tiling */ sisfb_post_xgi_ramsize()
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/linux-4.4.14/drivers/gpu/drm/ |
H A D | drm_crtc.c | 5217 * properties (including driver specific metadata like tiling layout) will work,
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