Searched refs:tile_split (Results 1 – 7 of 7) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | evergreen_cs.c | 1183 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1187 &tile_split); in evergreen_cs_handle_reg()
1189 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1446 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1450 &tile_split); in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1474 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1478 &tile_split); in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
2357 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_packet3_check() local
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| D | atombios_crtc.c | 1148 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1262 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1272 tile_split_bytes = 64 << tile_split; in dce4_crtc_do_set_base()
1281 target_fb->bits_per_pixel, tile_split); in dce4_crtc_do_set_base()
1326 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); in dce4_crtc_do_set_base()
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| D | evergreen.c | 1108 unsigned *tile_split) in evergreen_tiling_fields() argument
1113 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
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| D | radeon.h | 349 unsigned *tile_split);
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v8_0.c | 2105 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
2110 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
2115 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v8_0_crtc_do_set_base()
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| D | dce_v11_0.c | 2163 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local
2168 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2175 tile_split); in dce_v11_0_crtc_do_set_base()
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| D | dce_v10_0.c | 2175 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
2180 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2187 tile_split); in dce_v10_0_crtc_do_set_base()
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