| H A D | db8500-prcmu.c | 449 static __iomem void *tcdm_base; variable
673 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & prcmu_has_arm_maxopp()
689 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); prcmu_set_rc_a2p()
702 return readb(tcdm_base + PRCM_ROMCODE_P2A); prcmu_get_rc_p2a()
712 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); prcmu_get_xp70_current_state()
795 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); db8500_prcmu_set_power_state()
796 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); db8500_prcmu_set_power_state()
797 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); db8500_prcmu_set_power_state()
799 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); db8500_prcmu_set_power_state()
800 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); db8500_prcmu_set_power_state()
810 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); db8500_prcmu_get_power_state_result()
837 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); config_wakeups()
838 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); config_wakeups()
839 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); config_wakeups()
881 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) db8500_prcmu_get_abb_event_buffer()
882 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); db8500_prcmu_get_abb_event_buffer()
884 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); db8500_prcmu_get_abb_event_buffer()
908 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); db8500_prcmu_set_arm_opp()
909 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); db8500_prcmu_set_arm_opp()
910 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); db8500_prcmu_set_arm_opp()
931 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); db8500_prcmu_get_arm_opp()
1034 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); db8500_prcmu_set_ape_opp()
1035 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); db8500_prcmu_set_ape_opp()
1037 (tcdm_base + PRCM_REQ_MB1_APE_OPP)); db8500_prcmu_set_ape_opp()
1065 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); db8500_prcmu_get_ape_opp()
1099 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); db8500_prcmu_request_ape_opp_100_voltage()
1129 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); prcmu_release_usb_wakeup_state()
1159 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); request_pll()
1160 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); request_pll()
1213 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); db8500_prcmu_set_epod()
1214 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); db8500_prcmu_set_epod()
1216 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); db8500_prcmu_set_epod()
1276 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); prcmu_configure_auto_pm()
1277 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); prcmu_configure_auto_pm()
1308 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); request_sysclk()
1310 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); request_sysclk()
1998 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); db8500_prcmu_config_esram0_deep_sleep()
2000 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); db8500_prcmu_config_esram0_deep_sleep()
2002 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); db8500_prcmu_config_esram0_deep_sleep()
2003 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); db8500_prcmu_config_esram0_deep_sleep()
2020 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); db8500_prcmu_config_hotdog()
2021 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); db8500_prcmu_config_hotdog()
2038 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); db8500_prcmu_config_hotmon()
2039 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); db8500_prcmu_config_hotmon()
2041 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); db8500_prcmu_config_hotmon()
2042 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); db8500_prcmu_config_hotmon()
2059 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); config_hot_period()
2060 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); config_hot_period()
2091 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); prcmu_a9wdog()
2092 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); prcmu_a9wdog()
2093 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); prcmu_a9wdog()
2094 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); prcmu_a9wdog()
2096 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); prcmu_a9wdog()
2174 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); prcmu_abb_read()
2175 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); prcmu_abb_read()
2176 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); prcmu_abb_read()
2177 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); prcmu_abb_read()
2178 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); prcmu_abb_read()
2224 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); prcmu_abb_write_masked()
2225 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); prcmu_abb_write_masked()
2226 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); prcmu_abb_write_masked()
2227 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); prcmu_abb_write_masked()
2228 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); prcmu_abb_write_masked()
2345 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); db8500_prcmu_system_reset()
2357 return readw(tcdm_base + PRCM_SW_RST_REASON); db8500_prcmu_get_reset_code()
2370 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); db8500_prcmu_modem_reset()
2391 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); ack_dbb_wakeup()
2410 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); read_mailbox_0()
2414 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) read_mailbox_0()
2415 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); read_mailbox_0()
2417 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); read_mailbox_0()
2443 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); read_mailbox_1()
2444 mb1_transfer.ack.arm_opp = readb(tcdm_base + read_mailbox_1()
2446 mb1_transfer.ack.ape_opp = readb(tcdm_base + read_mailbox_1()
2448 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + read_mailbox_1()
2457 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); read_mailbox_2()
2474 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); read_mailbox_4()
2502 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); read_mailbox_5()
2503 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); read_mailbox_5()
3158 tcdm_base = devm_ioremap(&pdev->dev, res->start, db8500_prcmu_probe()
3160 if (!tcdm_base) { db8500_prcmu_probe()
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