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Searched refs:sor (Results 1 – 26 of 26) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/tegra/
Dsor.c158 int (*probe)(struct tegra_sor *sor);
159 int (*remove)(struct tegra_sor *sor);
217 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) in tegra_sor_readl() argument
219 return readl(sor->regs + (offset << 2)); in tegra_sor_readl()
222 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
225 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
228 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, in tegra_sor_dp_train_fast() argument
241 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
247 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
253 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
[all …]
DMakefile13 sor.o \
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgm204.c43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
47 .sor.magic = gm204_sor_magic,
Dgm107.c43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
Dgk110.c43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
Dgk104.c43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
Dgt215.c45 .sor.nr = 4,
46 .sor.power = nv50_sor_power,
47 .sor.hda_eld = gt215_hda_eld,
48 .sor.hdmi = gt215_hdmi_ctrl,
Dg84.c44 .sor.nr = 2,
45 .sor.power = nv50_sor_power,
46 .sor.hdmi = g84_hdmi_ctrl,
Dgt200.c44 .sor.nr = 2,
45 .sor.power = nv50_sor_power,
46 .sor.hdmi = g84_hdmi_ctrl,
Dg94.c45 .sor.nr = 4,
46 .sor.power = nv50_sor_power,
47 .sor.hdmi = g84_hdmi_ctrl,
Drootnv50.c133 return func->sor.power(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
135 if (!func->sor.hda_eld) in nv50_disp_root_mthd_()
137 return func->sor.hda_eld(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
139 if (!func->sor.hdmi) in nv50_disp_root_mthd_()
141 return func->sor.hdmi(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
151 disp->sor.lvdsconf = args->v0.script; in nv50_disp_root_mthd_()
339 for (i = 0; i < disp->func->sor.nr; i++) { in nv50_disp_root_init()
Dnv50.h24 } sor; member
100 } sor; member
Dgf119.c165 *conf = disp->sor.lvdsconf; in exec_clkcmp()
325 if (disp->func->sor.magic) in gf119_disp_intr_unk2_2()
326 disp->func->sor.magic(outp); in gf119_disp_intr_unk2_2()
526 .sor.nr = 4,
527 .sor.power = nv50_sor_power,
528 .sor.hda_eld = gf119_hda_eld,
529 .sor.hdmi = gf119_hdmi_ctrl,
Dnv50.c310 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) in exec_script()
370 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) in exec_clkcmp()
398 *conf = disp->sor.lvdsconf; in exec_clkcmp()
832 .sor.nr = 2,
833 .sor.power = nv50_sor_power,
Ddport.c334 if (!outp->base.info.location && disp->func->sor.magic) in nvkm_dp_train()
335 disp->func->sor.magic(&outp->base); in nvkm_dp_train()
Drootgf119.c106 for (i = 0; i < disp->func->sor.nr; i++) { in gf119_disp_root_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
Ddcb.h36 struct sor_conf sor; member
45 struct sor_conf sor; member
50 struct sor_conf sor; member
/linux-4.4.14/arch/powerpc/sysdev/
Dcpm2.c330 u32 dir, par, sor, odr, dat; member
352 setbits32(&iop[port].sor, pin); in cpm2_set_pin()
354 clrbits32(&iop[port].sor, pin); in cpm2_set_pin()
Dcpm1.c303 __be32 dir, par, sor, odr, dat; member
337 setbits32(&iop->sor, pin); in cpm1_set_pin32()
339 clrbits32(&iop->sor, pin); in cpm1_set_pin32()
Dcpm_common.c227 u32 dir, par, sor, odr, dat; member
/linux-4.4.14/arch/ia64/kernel/
Dunaligned.c296 rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg) in rotate_reg() argument
299 if (reg >= sor) in rotate_reg()
300 reg -= sor; in rotate_reg()
313 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); in set_rse_reg() local
323 if (ridx < sor) in set_rse_reg()
324 ridx = rotate_reg(sor, rrb_gr, ridx); in set_rse_reg()
386 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); in get_rse_reg() local
396 if (ridx < sor) in get_rse_reg()
397 ridx = rotate_reg(sor, rrb_gr, ridx); in get_rse_reg()
/linux-4.4.14/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt197 - sor: serial output resource
201 - "nvidia,tegra124-sor": for Tegra124 and Tegra132
202 - "nvidia,tegra132-sor": for Tegra132
203 - "nvidia,tegra210-sor": for Tegra210
210 - sor: clock input for the SOR hardware
217 - sor
/linux-4.4.14/drivers/gpu/drm/nouveau/
Dnouveau_bios.c1446 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1447 link = entry->lvdsconf.sor.link; in parse_dcb20_entry()
1472 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1498 link = entry->dpconf.sor.link; in parse_dcb20_entry()
1502 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1504 link = entry->tmdsconf.sor.link; in parse_dcb20_entry()
/linux-4.4.14/arch/arm/boot/dts/
Dtegra124.dtsi140 sor@0,54540000 {
141 compatible = "nvidia,tegra124-sor";
148 clock-names = "sor", "parent", "dp", "safe";
150 reset-names = "sor";
Dtegra124-nyan.dtsi28 sor@0,54540000 {
Dtegra124-venice2.dts33 sor@0,54540000 {