| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | kv_smc.c | 76 u32 smc_address, u32 limit) in kv_set_smc_sram_address() argument
78 if (smc_address & 3) in kv_set_smc_sram_address()
80 if ((smc_address + 3) > limit) in kv_set_smc_sram_address()
83 WREG32(SMC_IND_INDEX_0, smc_address); in kv_set_smc_sram_address()
89 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, in kv_read_smc_sram_dword() argument
94 ret = kv_set_smc_sram_address(rdev, smc_address, limit); in kv_read_smc_sram_dword()
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| D | ci_smc.c | 34 u32 smc_address, u32 limit) in ci_set_smc_sram_address() argument
36 if (smc_address & 3) in ci_set_smc_sram_address()
38 if ((smc_address + 3) > limit) in ci_set_smc_sram_address()
41 WREG32(SMC_IND_INDEX_0, smc_address); in ci_set_smc_sram_address()
268 u32 smc_address, u32 *value, u32 limit) in ci_read_smc_sram_dword() argument
274 ret = ci_set_smc_sram_address(rdev, smc_address, limit); in ci_read_smc_sram_dword()
283 u32 smc_address, u32 value, u32 limit) in ci_write_smc_sram_dword() argument
289 ret = ci_set_smc_sram_address(rdev, smc_address, limit); in ci_write_smc_sram_dword()
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| D | si_smc.c | 34 u32 smc_address, u32 limit) in si_set_smc_sram_address() argument
36 if (smc_address & 3) in si_set_smc_sram_address()
38 if ((smc_address + 3) > limit) in si_set_smc_sram_address()
41 WREG32(SMC_IND_INDEX_0, smc_address); in si_set_smc_sram_address()
282 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, in si_read_smc_sram_dword() argument
289 ret = si_set_smc_sram_address(rdev, smc_address, limit); in si_read_smc_sram_dword()
297 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, in si_write_smc_sram_dword() argument
304 ret = si_set_smc_sram_address(rdev, smc_address, limit); in si_write_smc_sram_dword()
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| D | rv770_smc.c | 278 u16 smc_address, u16 limit) in rv770_set_smc_sram_address() argument
282 if (smc_address & 3) in rv770_set_smc_sram_address()
284 if ((smc_address + 3) > limit) in rv770_set_smc_sram_address()
287 addr = smc_address; in rv770_set_smc_sram_address()
604 u16 smc_address, u32 *value, u16 limit) in rv770_read_smc_sram_dword() argument
610 ret = rv770_set_smc_sram_address(rdev, smc_address, limit); in rv770_read_smc_sram_dword()
619 u16 smc_address, u32 value, u16 limit) in rv770_write_smc_sram_dword() argument
625 ret = rv770_set_smc_sram_address(rdev, smc_address, limit); in rv770_write_smc_sram_dword()
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| D | rv770_smc.h | 201 u16 smc_address, u32 *value, u16 limit);
203 u16 smc_address, u32 value, u16 limit);
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| D | ci_dpm.h | 337 u32 smc_address, u32 *value, u32 limit);
339 u32 smc_address, u32 value, u32 limit);
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| D | sislands_smc.h | 417 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
419 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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| D | kv_dpm.h | 192 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | kv_smc.c | 79 u32 smc_address, u32 limit) in kv_set_smc_sram_address() argument
81 if (smc_address & 3) in kv_set_smc_sram_address()
83 if ((smc_address + 3) > limit) in kv_set_smc_sram_address()
86 WREG32(mmSMC_IND_INDEX_0, smc_address); in kv_set_smc_sram_address()
93 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, in amdgpu_kv_read_smc_sram_dword() argument
98 ret = kv_set_smc_sram_address(adev, smc_address, limit); in amdgpu_kv_read_smc_sram_dword()
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| D | ci_smc.c | 37 u32 smc_address, u32 limit) in ci_set_smc_sram_address() argument
39 if (smc_address & 3) in ci_set_smc_sram_address()
41 if ((smc_address + 3) > limit) in ci_set_smc_sram_address()
44 WREG32(mmSMC_IND_INDEX_0, smc_address); in ci_set_smc_sram_address()
252 u32 smc_address, u32 *value, u32 limit) in amdgpu_ci_read_smc_sram_dword() argument
258 ret = ci_set_smc_sram_address(adev, smc_address, limit); in amdgpu_ci_read_smc_sram_dword()
267 u32 smc_address, u32 value, u32 limit) in amdgpu_ci_write_smc_sram_dword() argument
273 ret = ci_set_smc_sram_address(adev, smc_address, limit); in amdgpu_ci_write_smc_sram_dword()
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| D | iceland_smc.c | 38 uint32_t smc_address, uint32_t limit) in iceland_set_smc_sram_address() argument
42 if (smc_address & 3) in iceland_set_smc_sram_address()
45 if ((smc_address + 3) > limit) in iceland_set_smc_sram_address()
48 WREG32(mmSMC_IND_INDEX_0, smc_address); in iceland_set_smc_sram_address()
337 uint32_t smc_address,
345 result = iceland_set_smc_sram_address(adev, smc_address, limit);
353 uint32_t smc_address,
361 result = iceland_set_smc_sram_address(adev, smc_address, limit);
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| D | fiji_smc.c | 37 static int fiji_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t lim… in fiji_set_smc_sram_address() argument
41 if (smc_address & 3) in fiji_set_smc_sram_address()
44 if ((smc_address + 3) > limit) in fiji_set_smc_sram_address()
47 WREG32(mmSMC_IND_INDEX_0, smc_address); in fiji_set_smc_sram_address()
316 uint32_t smc_address,
324 result = fiji_set_smc_sram_address(adev, smc_address, limit);
332 uint32_t smc_address,
340 result = fiji_set_smc_sram_address(adev, smc_address, limit);
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| D | tonga_smc.c | 37 static int tonga_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t li… in tonga_set_smc_sram_address() argument
41 if (smc_address & 3) in tonga_set_smc_sram_address()
44 if ((smc_address + 3) > limit) in tonga_set_smc_sram_address()
47 WREG32(mmSMC_IND_INDEX_0, smc_address); in tonga_set_smc_sram_address()
316 uint32_t smc_address,
324 result = tonga_set_smc_sram_address(adev, smc_address, limit);
332 uint32_t smc_address,
340 result = tonga_set_smc_sram_address(adev, smc_address, limit);
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| D | cz_smc.c | 117 u32 smc_address, u32 limit) in cz_set_smc_sram_address() argument
119 if (smc_address & 3) in cz_set_smc_sram_address()
121 if ((smc_address + 3) > limit) in cz_set_smc_sram_address()
124 WREG32(mmMP0PUB_IND_INDEX_0, SMN_MP1_SRAM_START_ADDR + smc_address); in cz_set_smc_sram_address()
129 int cz_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, in cz_read_smc_sram_dword() argument
134 ret = cz_set_smc_sram_address(adev, smc_address, limit); in cz_read_smc_sram_dword()
143 int cz_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, in cz_write_smc_sram_dword() argument
148 ret = cz_set_smc_sram_address(adev, smc_address, limit); in cz_write_smc_sram_dword()
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| D | ci_dpm.h | 344 u32 smc_address, u32 *value, u32 limit);
346 u32 smc_address, u32 value, u32 limit);
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| D | kv_dpm.h | 221 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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| D | cz_dpm.h | 234 uint32_t smc_address, uint32_t *value, uint32_t limit);
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