| H A D | pci.c | 216 #define show_reg(name, what) \ dump_cxl_config_space() macro
220 show_reg("Cap ID", (val >> 0) & 0xffff); dump_cxl_config_space()
221 show_reg("Cap Ver", (val >> 16) & 0xf); dump_cxl_config_space()
222 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); dump_cxl_config_space()
224 show_reg("VSEC ID", (val >> 0) & 0xffff); dump_cxl_config_space()
225 show_reg("VSEC Rev", (val >> 16) & 0xf); dump_cxl_config_space()
226 show_reg("VSEC Length", (val >> 20) & 0xfff); dump_cxl_config_space()
228 show_reg("Num AFUs", (val >> 0) & 0xff); dump_cxl_config_space()
229 show_reg("Status", (val >> 8) & 0xff); dump_cxl_config_space()
230 show_reg("Mode Control", (val >> 16) & 0xff); dump_cxl_config_space()
231 show_reg("Reserved", (val >> 24) & 0xff); dump_cxl_config_space()
233 show_reg("PSL Rev", (val >> 0) & 0xffff); dump_cxl_config_space()
234 show_reg("CAIA Ver", (val >> 16) & 0xffff); dump_cxl_config_space()
236 show_reg("Base Image Rev", (val >> 0) & 0xffff); dump_cxl_config_space()
237 show_reg("Reserved", (val >> 16) & 0x0fff); dump_cxl_config_space()
238 show_reg("Image Control", (val >> 28) & 0x3); dump_cxl_config_space()
239 show_reg("Reserved", (val >> 30) & 0x1); dump_cxl_config_space()
240 show_reg("Image Loaded", (val >> 31) & 0x1); dump_cxl_config_space()
243 show_reg("Reserved", val); dump_cxl_config_space()
245 show_reg("Reserved", val); dump_cxl_config_space()
247 show_reg("Reserved", val); dump_cxl_config_space()
250 show_reg("AFU Descriptor Offset", val); dump_cxl_config_space()
252 show_reg("AFU Descriptor Size", val); dump_cxl_config_space()
254 show_reg("Problem State Offset", val); dump_cxl_config_space()
256 show_reg("Problem State Size", val); dump_cxl_config_space()
259 show_reg("Reserved", val); dump_cxl_config_space()
261 show_reg("Reserved", val); dump_cxl_config_space()
263 show_reg("Reserved", val); dump_cxl_config_space()
265 show_reg("Reserved", val); dump_cxl_config_space()
268 show_reg("PSL Programming Port", val); dump_cxl_config_space()
270 show_reg("PSL Programming Control", val); dump_cxl_config_space()
273 show_reg("Reserved", val); dump_cxl_config_space()
275 show_reg("Reserved", val); dump_cxl_config_space()
278 show_reg("Flash Address Register", val); dump_cxl_config_space()
280 show_reg("Flash Size Register", val); dump_cxl_config_space()
282 show_reg("Flash Status/Control Register", val); dump_cxl_config_space()
284 show_reg("Flash Data Port", val); dump_cxl_config_space()
286 #undef show_reg dump_cxl_config_space() macro
294 #define show_reg(name, what) \ dump_afu_descriptor() macro
298 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); dump_afu_descriptor()
299 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); dump_afu_descriptor()
300 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); dump_afu_descriptor()
301 show_reg("req_prog_mode", val & 0xffffULL); dump_afu_descriptor()
305 show_reg("Reserved", val); dump_afu_descriptor()
307 show_reg("Reserved", val); dump_afu_descriptor()
309 show_reg("Reserved", val); dump_afu_descriptor()
312 show_reg("Reserved", (val >> (63-7)) & 0xff); dump_afu_descriptor()
313 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); dump_afu_descriptor()
318 show_reg("AFU_CR_offset", val); dump_afu_descriptor()
321 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); dump_afu_descriptor()
322 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); dump_afu_descriptor()
325 show_reg("PerProcessPSA_offset", val); dump_afu_descriptor()
328 show_reg("Reserved", (val >> (63-7)) & 0xff); dump_afu_descriptor()
329 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); dump_afu_descriptor()
332 show_reg("AFU_EB_offset", val); dump_afu_descriptor()
336 show_reg("CR Vendor", val & 0xffff); dump_afu_descriptor()
337 show_reg("CR Device", (val >> 16) & 0xffff); dump_afu_descriptor()
339 #undef show_reg dump_afu_descriptor() macro
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