Searched refs:seq_state (Results 1 – 5 of 5) sorted by relevance
937 const char *seq_state; in cia_decode_mem_error() local972 seq_state = "Idle"; in cia_decode_mem_error()975 seq_state = "DMA READ or DMA WRITE"; in cia_decode_mem_error()978 seq_state = "READ MISS (or READ MISS MODIFY) with victim"; in cia_decode_mem_error()981 seq_state = "READ MISS (or READ MISS MODIFY) with no victim"; in cia_decode_mem_error()984 seq_state = "Refresh"; in cia_decode_mem_error()987 seq_state = "Idle, waiting for DMA pending read"; in cia_decode_mem_error()990 seq_state = "Idle, ras precharge"; in cia_decode_mem_error()993 seq_state = "Unknown"; in cia_decode_mem_error()1023 printk(KERN_CRIT " Memory sequencer state: %s\n", seq_state); in cia_decode_mem_error()
193 u32 access, stat, seq_state; in boot_core() local218 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK; in boot_core()221 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) in boot_core()
341 u32 seq_state; member
129 writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR); in etm4_enable_hw()482 drvdata->seq_state = 0x0; in reset_store()1493 val = drvdata->seq_state; in seq_state_show()1509 drvdata->seq_state = val; in seq_state_store()1512 static DEVICE_ATTR_RW(seq_state);2504 drvdata->seq_state = 0x0; in etm4_init_default_data()
189 What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state