Searched refs:sdm_cfg1 (Results 1 – 1 of 1) sorted by relevance
144 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; in dsi_pll_28nm_clk_set_rate() local192 sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); in dsi_pll_28nm_clk_set_rate()193 sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; in dsi_pll_28nm_clk_set_rate()197 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( in dsi_pll_28nm_clk_set_rate()205 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0); in dsi_pll_28nm_clk_set_rate()211 DBG("sdm_cfg1=%d", sdm_cfg1); in dsi_pll_28nm_clk_set_rate()224 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate()