| /linux-4.4.14/drivers/clk/spear/ |
| H A D | clk-gpt-synth.c | 38 struct gpt_rate_tbl *rtbl = gpt->rtbl; gpt_calc_rate() local
40 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); gpt_calc_rate()
84 struct gpt_rate_tbl *rtbl = gpt->rtbl; clk_gpt_set_rate() local
97 val |= rtbl[i].mscale & GPT_MSCALE_MASK; clk_gpt_set_rate()
98 val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT; clk_gpt_set_rate()
115 long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 clk_register_gpt()
122 if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { clk_register_gpt()
135 gpt->rtbl = rtbl; clk_register_gpt()
114 clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) clk_register_gpt() argument
|
| H A D | clk-frac-synth.c | 48 struct frac_rate_tbl *rtbl = frac->rtbl; frac_calc_rate() local
52 prate /= (2 * rtbl[index].div); frac_calc_rate()
99 struct frac_rate_tbl *rtbl = frac->rtbl; clk_frac_set_rate() local
110 val |= rtbl[i].div & DIV_FACTOR_MASK; clk_frac_set_rate()
127 struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) clk_register_frac()
133 if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { clk_register_frac()
146 frac->rtbl = rtbl; clk_register_frac()
125 clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) clk_register_frac() argument
|
| H A D | clk-aux-synth.c | 48 struct aux_rate_tbl *rtbl = aux->rtbl; aux_calc_rate() local
49 u8 eq = rtbl[index].eq ? 1 : 2; aux_calc_rate()
51 return (((prate / 10000) * rtbl[index].xscale) / aux_calc_rate()
52 (rtbl[index].yscale * eq)) * 10000; aux_calc_rate()
103 struct aux_rate_tbl *rtbl = aux->rtbl; clk_aux_set_rate() local
115 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << clk_aux_set_rate()
118 val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) << clk_aux_set_rate()
121 val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) << clk_aux_set_rate()
139 struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, clk_register_aux()
146 if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { clk_register_aux()
164 aux->rtbl = rtbl; clk_register_aux()
137 clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) clk_register_aux() argument
|
| H A D | clk-vco-pll.c | 69 static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl, pll_calc_rate() argument
75 mode = rtbl[index].mode ? 256 : 1; pll_calc_rate()
76 rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n)); pll_calc_rate()
79 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; pll_calc_rate()
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, clk_pll_round_rate_index()
148 struct pll_rate_tbl *rtbl = pll->vco->rtbl; clk_pll_set_rate() local
159 val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT; clk_pll_set_rate()
179 return pll_calc_rate(vco->rtbl, prate, index, NULL); vco_calc_rate()
234 struct pll_rate_tbl *rtbl = vco->rtbl; clk_vco_set_rate() local
246 val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT; clk_vco_set_rate()
251 val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT; clk_vco_set_rate()
254 if (rtbl[i].mode) clk_vco_set_rate()
255 val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) << clk_vco_set_rate()
258 val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) << clk_vco_set_rate()
278 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, clk_register_vco_pll()
289 !rtbl || !rtbl_cnt) { clk_register_vco_pll()
309 vco->rtbl = rtbl; clk_register_vco_pll()
275 clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **pll_clk, struct clk **vco_gate_clk) clk_register_vco_pll() argument
|
| H A D | clk.h | 53 struct aux_rate_tbl *rtbl; member in struct:clk_aux
66 struct frac_rate_tbl *rtbl; member in struct:clk_frac
80 struct gpt_rate_tbl *rtbl; member in struct:clk_gpt
97 struct pll_rate_tbl *rtbl; member in struct:clk_vco
115 struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
119 struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
121 long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
126 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
|
| /linux-4.4.14/drivers/power/ |
| H A D | bq25890_charger.c | 330 const struct bq25890_range *rtbl = &bq25890_tables[id].rt; bq25890_find_idx() local
333 rtbl_size = (rtbl->max - rtbl->min) / rtbl->step + 1; bq25890_find_idx()
336 idx < rtbl_size && (idx * rtbl->step + rtbl->min <= value); bq25890_find_idx()
346 const struct bq25890_range *rtbl; bq25890_find_val() local
353 rtbl = &bq25890_tables[id].rt; bq25890_find_val()
355 return (rtbl->min + idx * rtbl->step); bq25890_find_val()
|
| /linux-4.4.14/drivers/clk/st/ |
| H A D | clkgen-fsyn.c | 141 const struct stm_fs *rtbl; member in struct:clkgen_quadfs_data
197 .rtbl = fs216c65_rtbl,
233 .rtbl = fs432c65_rtbl,
269 .rtbl = fs660c32_rtbl,
305 .rtbl = fs660c32_rtbl,
348 .rtbl = fs660c32_rtbl,
391 .rtbl = fs660c32_rtbl,
907 *params = fs->data->rtbl[index]; quadfs_find_best_rate()
910 clk_fs_get_rate(prate, &fs->data->rtbl[index], &rate); quadfs_find_best_rate()
|