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Searched refs:rfHSSIPara2 (Results 1 – 13 of 13) sorted by relevance

/linux-4.4.14/drivers/staging/rtl8188eu/hal/
Drf_cfg.c264 phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, in rf6052_conf_para()
268 phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, in rf6052_conf_para()
Dbb_cfg.c636 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in rtl88e_phy_init_bb_rf_register_definition()
637 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in rtl88e_phy_init_bb_rf_register_definition()
Dphy.c84 tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2, in rf_serial_read()
94 phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2); in rf_serial_read()
/linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/
Dr8190P_rtl8256.c103 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, in rtl92e_config_rf()
105 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, in rtl92e_config_rf()
Dr8192E_phy.c135 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, in _rtl92e_phy_rf_read()
137 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); in _rtl92e_phy_rf_read()
138 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); in _rtl92e_phy_rf_read()
435 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
436 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
437 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
438 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
Dr8190P_def.h123 u32 rfHSSIPara2; member
/linux-4.4.14/drivers/staging/rtl8723au/hal/
Drtl8723a_phycfg.c194 tmplong2 = rtl8723au_read32(Adapter, pPhyReg->rfHSSIPara2); in phy_RFSerialRead()
203 rtl8723au_write32(Adapter, pPhyReg->rfHSSIPara2, tmplong2); in phy_RFSerialRead()
494 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in phy_InitBBRFRegisterDefinition()
496 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in phy_InitBBRFRegisterDefinition()
Drtl8723a_rf6052.c451 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, in phy_RF6052_Config_ParaFile()
455 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, in phy_RF6052_Config_ParaFile()
/linux-4.4.14/drivers/staging/rtl8192u/
Dr8190_rtl8256.c144 …rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-se… in phy_RF8256_Config_ParaFile()
145 …rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-seri… in phy_RF8256_Config_ParaFile()
Dr819xU_phy.c186 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, in rtl8192_phy_RFSerialRead()
189 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); in rtl8192_phy_RFSerialRead()
190 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); in rtl8192_phy_RFSerialRead()
639 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in rtl8192_InitBBRFRegDef()
640 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in rtl8192_InitBBRFRegDef()
641 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; in rtl8192_InitBBRFRegDef()
642 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in rtl8192_InitBBRFRegDef()
Dr8192U.h679 u32 rfHSSIPara2; member
/linux-4.4.14/drivers/staging/rtl8723au/include/
DHal8723APhyCfg.h56 u32 rfHSSIPara2; /* wire parameter control2 : */ member
/linux-4.4.14/drivers/staging/rtl8188eu/include/
DHal8188EPhyCfg.h138 u32 rfHSSIPara2; /* wire parameter control2 : */ member