Searched refs:regw (Results 1 - 7 of 7) sorted by relevance

/linux-4.4.14/drivers/media/platform/davinci/
H A Dvpif.h33 #define regw(value, reg) writel(value, (reg + vpif_base)) macro
139 regw((regr(reg)) | (0x01 << bit), reg); vpif_set_bit()
144 regw(((regr(reg)) & ~(0x01 << bit)), reg); vpif_clr_bit()
221 #define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
225 #define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
229 #define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
233 #define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
274 regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL); enable_channel0()
276 regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL); enable_channel0()
283 regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL); enable_channel1()
285 regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL); enable_channel1()
296 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); channel0_intr_enable()
297 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); channel0_intr_enable()
299 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN); channel0_intr_enable()
300 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), channel0_intr_enable()
303 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN); channel0_intr_enable()
304 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), channel0_intr_enable()
318 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); channel1_intr_enable()
319 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); channel1_intr_enable()
321 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN); channel1_intr_enable()
322 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), channel1_intr_enable()
325 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN); channel1_intr_enable()
326 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), channel1_intr_enable()
338 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); ch0_set_videobuf_addr_yc_nmux()
339 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); ch0_set_videobuf_addr_yc_nmux()
340 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); ch0_set_videobuf_addr_yc_nmux()
341 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); ch0_set_videobuf_addr_yc_nmux()
350 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA); ch0_set_videobuf_addr()
351 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA); ch0_set_videobuf_addr()
352 regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA); ch0_set_videobuf_addr()
353 regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA); ch0_set_videobuf_addr()
362 regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA); ch1_set_videobuf_addr()
363 regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA); ch1_set_videobuf_addr()
364 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA); ch1_set_videobuf_addr()
365 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA); ch1_set_videobuf_addr()
371 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC); ch0_set_vbi_addr()
372 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC); ch0_set_vbi_addr()
378 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC); ch0_set_hbi_addr()
379 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC); ch0_set_hbi_addr()
385 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC); ch1_set_vbi_addr()
386 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC); ch1_set_vbi_addr()
392 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC); ch1_set_hbi_addr()
393 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC); ch1_set_hbi_addr()
429 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); enable_channel2()
430 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL); enable_channel2()
432 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); enable_channel2()
433 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL); enable_channel2()
441 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); enable_channel3()
442 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL); enable_channel3()
444 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); enable_channel3()
445 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL); enable_channel3()
457 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); channel2_intr_enable()
458 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); channel2_intr_enable()
459 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN); channel2_intr_enable()
460 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), channel2_intr_enable()
463 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN); channel2_intr_enable()
464 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), channel2_intr_enable()
478 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); channel3_intr_enable()
479 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); channel3_intr_enable()
481 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN); channel3_intr_enable()
482 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), channel3_intr_enable()
485 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN); channel3_intr_enable()
486 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), channel3_intr_enable()
554 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); ch2_set_videobuf_addr_yc_nmux()
555 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); ch2_set_videobuf_addr_yc_nmux()
556 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); ch2_set_videobuf_addr_yc_nmux()
557 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); ch2_set_videobuf_addr_yc_nmux()
566 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA); ch2_set_videobuf_addr()
567 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA); ch2_set_videobuf_addr()
568 regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA); ch2_set_videobuf_addr()
569 regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA); ch2_set_videobuf_addr()
577 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA); ch3_set_videobuf_addr()
578 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA); ch3_set_videobuf_addr()
579 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA); ch3_set_videobuf_addr()
580 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA); ch3_set_videobuf_addr()
589 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC); ch2_set_vbi_addr()
590 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC); ch2_set_vbi_addr()
598 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC); ch3_set_vbi_addr()
599 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC); ch3_set_vbi_addr()
612 regw(status, VPIF_STATUS_CLR); vpif_intr_status()
H A Ddm644x_ccdc.c109 static inline void regw(u32 val, u32 offset) regw() function
116 regw(flag, CCDC_PCR); ccdc_enable()
123 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG); ccdc_enable_vport()
125 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG); ccdc_enable_vport()
149 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels, ccdc_setwin()
161 regw(val, CCDC_VDINT); ccdc_setwin()
174 regw(val, CCDC_VDINT); ccdc_setwin()
177 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start, ccdc_setwin()
179 regw(vert_nr_lines, CCDC_VERT_LINES); ccdc_setwin()
328 regw(0, i); ccdc_restore_defaults()
329 regw(CCDC_NO_CULLING, CCDC_CULLING); ccdc_restore_defaults()
330 regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW); ccdc_restore_defaults()
399 regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF); ccdc_config_ycbcr()
419 regw(syn_mode, CCDC_SYN_MODE); ccdc_config_ycbcr()
429 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) | ccdc_config_ycbcr()
433 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) | ccdc_config_ycbcr()
440 regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF); ccdc_config_ycbcr()
445 regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST); ccdc_config_ycbcr()
458 regw(val, CCDC_DCSUB); ccdc_config_black_clamp()
460 regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP); ccdc_config_black_clamp()
475 regw(val, CCDC_CLAMP); ccdc_config_black_clamp()
478 regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB); ccdc_config_black_clamp()
493 regw(val, CCDC_BLKCMP); ccdc_config_black_compense()
502 regw(val, CCDC_FPC); ccdc_config_fpc()
508 regw(fpc->fpc_table_addr, CCDC_FPC_ADDR); ccdc_config_fpc()
513 regw(val, CCDC_FPC); ccdc_config_fpc()
518 regw(val, CCDC_FPC); ccdc_config_fpc()
540 regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG); ccdc_config_raw()
563 regw(val, CCDC_ALAW); ccdc_config_raw()
594 regw(val, CCDC_FMTCFG); ccdc_config_raw()
598 regw(CCDC_COLPTN_VAL, CCDC_COLPTN); ccdc_config_raw()
608 regw(val, CCDC_FMT_HORZ); ccdc_config_raw()
620 regw(val, CCDC_FMT_VERT); ccdc_config_raw()
624 dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)..."); ccdc_config_raw()
632 regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) & ccdc_config_raw()
636 regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) + ccdc_config_raw()
644 regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST); ccdc_config_raw()
650 regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST); ccdc_config_raw()
654 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST); ccdc_config_raw()
674 regw(val, CCDC_VP_OUT); ccdc_config_raw()
677 regw(syn_mode, CCDC_SYN_MODE); ccdc_config_raw()
824 regw(addr & 0xffffffe0, CCDC_SDR_ADDR); ccdc_setfbaddr()
889 regw(ccdc_ctx[CCDC_SYN_MODE >> 2], CCDC_SYN_MODE); ccdc_restore_context()
890 regw(ccdc_ctx[CCDC_HD_VD_WID >> 2], CCDC_HD_VD_WID); ccdc_restore_context()
891 regw(ccdc_ctx[CCDC_PIX_LINES >> 2], CCDC_PIX_LINES); ccdc_restore_context()
892 regw(ccdc_ctx[CCDC_HORZ_INFO >> 2], CCDC_HORZ_INFO); ccdc_restore_context()
893 regw(ccdc_ctx[CCDC_VERT_START >> 2], CCDC_VERT_START); ccdc_restore_context()
894 regw(ccdc_ctx[CCDC_VERT_LINES >> 2], CCDC_VERT_LINES); ccdc_restore_context()
895 regw(ccdc_ctx[CCDC_CULLING >> 2], CCDC_CULLING); ccdc_restore_context()
896 regw(ccdc_ctx[CCDC_HSIZE_OFF >> 2], CCDC_HSIZE_OFF); ccdc_restore_context()
897 regw(ccdc_ctx[CCDC_SDOFST >> 2], CCDC_SDOFST); ccdc_restore_context()
898 regw(ccdc_ctx[CCDC_SDR_ADDR >> 2], CCDC_SDR_ADDR); ccdc_restore_context()
899 regw(ccdc_ctx[CCDC_CLAMP >> 2], CCDC_CLAMP); ccdc_restore_context()
900 regw(ccdc_ctx[CCDC_DCSUB >> 2], CCDC_DCSUB); ccdc_restore_context()
901 regw(ccdc_ctx[CCDC_COLPTN >> 2], CCDC_COLPTN); ccdc_restore_context()
902 regw(ccdc_ctx[CCDC_BLKCMP >> 2], CCDC_BLKCMP); ccdc_restore_context()
903 regw(ccdc_ctx[CCDC_FPC >> 2], CCDC_FPC); ccdc_restore_context()
904 regw(ccdc_ctx[CCDC_FPC_ADDR >> 2], CCDC_FPC_ADDR); ccdc_restore_context()
905 regw(ccdc_ctx[CCDC_VDINT >> 2], CCDC_VDINT); ccdc_restore_context()
906 regw(ccdc_ctx[CCDC_ALAW >> 2], CCDC_ALAW); ccdc_restore_context()
907 regw(ccdc_ctx[CCDC_REC656IF >> 2], CCDC_REC656IF); ccdc_restore_context()
908 regw(ccdc_ctx[CCDC_CCDCFG >> 2], CCDC_CCDCFG); ccdc_restore_context()
909 regw(ccdc_ctx[CCDC_FMTCFG >> 2], CCDC_FMTCFG); ccdc_restore_context()
910 regw(ccdc_ctx[CCDC_FMT_HORZ >> 2], CCDC_FMT_HORZ); ccdc_restore_context()
911 regw(ccdc_ctx[CCDC_FMT_VERT >> 2], CCDC_FMT_VERT); ccdc_restore_context()
912 regw(ccdc_ctx[CCDC_FMT_ADDR0 >> 2], CCDC_FMT_ADDR0); ccdc_restore_context()
913 regw(ccdc_ctx[CCDC_FMT_ADDR1 >> 2], CCDC_FMT_ADDR1); ccdc_restore_context()
914 regw(ccdc_ctx[CCDC_FMT_ADDR2 >> 2], CCDC_FMT_ADDR2); ccdc_restore_context()
915 regw(ccdc_ctx[CCDC_FMT_ADDR3 >> 2], CCDC_FMT_ADDR3); ccdc_restore_context()
916 regw(ccdc_ctx[CCDC_FMT_ADDR4 >> 2], CCDC_FMT_ADDR4); ccdc_restore_context()
917 regw(ccdc_ctx[CCDC_FMT_ADDR5 >> 2], CCDC_FMT_ADDR5); ccdc_restore_context()
918 regw(ccdc_ctx[CCDC_FMT_ADDR6 >> 2], CCDC_FMT_ADDR6); ccdc_restore_context()
919 regw(ccdc_ctx[CCDC_FMT_ADDR7 >> 2], CCDC_FMT_ADDR7); ccdc_restore_context()
920 regw(ccdc_ctx[CCDC_PRGEVEN_0 >> 2], CCDC_PRGEVEN_0); ccdc_restore_context()
921 regw(ccdc_ctx[CCDC_PRGEVEN_1 >> 2], CCDC_PRGEVEN_1); ccdc_restore_context()
922 regw(ccdc_ctx[CCDC_PRGODD_0 >> 2], CCDC_PRGODD_0); ccdc_restore_context()
923 regw(ccdc_ctx[CCDC_PRGODD_1 >> 2], CCDC_PRGODD_1); ccdc_restore_context()
924 regw(ccdc_ctx[CCDC_VP_OUT >> 2], CCDC_VP_OUT); ccdc_restore_context()
925 regw(ccdc_ctx[CCDC_PCR >> 2], CCDC_PCR); ccdc_restore_context()
H A Disif.c156 static inline void regw(u32 val, u32 offset) regw() function
166 regw(new_val, offset); reg_modify()
181 regw(0, CLAMPCFG); isif_disable_all_modules()
183 regw(0, DFCCTL); isif_disable_all_modules()
185 regw(0, CSCCTL); isif_disable_all_modules()
187 regw(0, LINCFG0); isif_disable_all_modules()
216 regw(val, CULH); isif_config_culling()
219 regw(cul->vcpat, CULV); isif_config_culling()
243 regw(val, CRGAIN); isif_config_gain_offset()
247 regw(val, CGRGAIN); isif_config_gain_offset()
251 regw(val, CGBGAIN); isif_config_gain_offset()
255 regw(val, CBGAIN); isif_config_gain_offset()
257 regw(gain_off_p->offset, COFSTA); isif_config_gain_offset()
300 regw(horz_start & START_PX_HOR_MASK, SPH); isif_setwin()
301 regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH); isif_setwin()
315 regw(mid_img, VDINT1); isif_setwin()
318 regw(0, VDINT0); isif_setwin()
319 regw(vert_start & START_VER_ONE_MASK, SLV0); isif_setwin()
320 regw(vert_start & START_VER_TWO_MASK, SLV1); isif_setwin()
321 regw(vert_nr_lines & NUM_LINES_VER, LNV); isif_setwin()
332 regw(bc->dc_offset, CLDCOFST); isif_config_bclamp()
340 regw(val, CLAMPCFG); isif_config_bclamp()
361 regw(val, CLHWIN0); isif_config_bclamp()
363 regw(bc->horz.win_start_h_calc, CLHWIN1); isif_config_bclamp()
364 regw(bc->horz.win_start_v_calc, CLHWIN2); isif_config_bclamp()
373 regw(val, CLVWIN0); isif_config_bclamp()
376 regw(bc->vert.ob_start_h, CLVWIN1); isif_config_bclamp()
378 regw(bc->vert.ob_start_v, CLVWIN2); isif_config_bclamp()
380 regw(bc->vert.ob_v_sz_calc, CLVWIN3); isif_config_bclamp()
382 regw(bc->vert_start_sub, CLSV); isif_config_bclamp()
391 regw(0, LINCFG0); isif_config_linearization()
397 regw(val, LINCFG0); isif_config_linearization()
403 regw(val, LINCFG1); isif_config_linearization()
432 regw(val, DFCCTL); isif_config_dfc()
435 regw(vdfc->def_sat_level, VDFSATLV); isif_config_dfc()
437 regw(vdfc->table[0].pos_vert, DFCMEM0); isif_config_dfc()
438 regw(vdfc->table[0].pos_horz, DFCMEM1); isif_config_dfc()
441 regw(vdfc->table[0].level_at_pos, DFCMEM2); isif_config_dfc()
442 regw(vdfc->table[0].level_up_pixels, DFCMEM3); isif_config_dfc()
443 regw(vdfc->table[0].level_low_pixels, DFCMEM4); isif_config_dfc()
448 regw(val, DFCMEMCTL); isif_config_dfc()
460 regw(vdfc->table[i].pos_vert, DFCMEM0); isif_config_dfc()
461 regw(vdfc->table[i].pos_horz, DFCMEM1); isif_config_dfc()
464 regw(vdfc->table[i].level_at_pos, DFCMEM2); isif_config_dfc()
465 regw(vdfc->table[i].level_up_pixels, DFCMEM3); isif_config_dfc()
466 regw(vdfc->table[i].level_low_pixels, DFCMEM4); isif_config_dfc()
472 regw(val, DFCMEMCTL); isif_config_dfc()
486 regw(0, DFCMEM0); isif_config_dfc()
487 regw(0x1FFF, DFCMEM1); isif_config_dfc()
488 regw(1, DFCMEMCTL); isif_config_dfc()
502 regw(0, CSCCTL); isif_config_csc()
519 regw(val2, (CSCM0 + ((i - 1) << 1))); isif_config_csc()
524 regw(df_csc->start_pix, FMTSPH); isif_config_csc()
531 regw(df_csc->num_pixels, FMTLNH); isif_config_csc()
532 regw(df_csc->start_line, FMTSLV); isif_config_csc()
537 regw(df_csc->num_lines, FMTLNV); isif_config_csc()
540 regw(1, CSCCTL); isif_config_csc()
569 regw(val, CCDCFG); isif_config_raw()
591 regw(val, MODESET); isif_config_raw()
605 regw(val, CGAMMAWD); isif_config_raw()
614 regw(val, MISC); isif_config_raw()
628 regw(val, CCOLP); isif_config_raw()
642 regw(val, HSIZE); isif_config_raw()
648 regw(0x4B6D, SDOFST); isif_config_raw()
652 regw(0x0B6D, SDOFST); isif_config_raw()
658 regw(0x4000, SDOFST); isif_config_raw()
662 regw(0x0000, SDOFST); isif_config_raw()
687 regw(module_params->horz_offset, DATAHOFST); isif_config_raw()
688 regw(module_params->vert_offset, DATAVOFST); isif_config_raw()
858 regw((addr >> 21) & 0x07ff, CADU); isif_setfbaddr()
859 regw((addr >> 5) & 0x0ffff, CADL); isif_setfbaddr()
914 regw(3, REC656IF); isif_config_ycbcr()
923 regw(3, REC656IF); isif_config_ycbcr()
933 regw(3, REC656IF); isif_config_ycbcr()
956 regw(modeset, MODESET); isif_config_ycbcr()
961 regw(ccdcfg, CCDCFG); isif_config_ycbcr()
975 regw(((((params->win.width * 2) + 31) & 0xffffffe0) >> 5), HSIZE); isif_config_ycbcr()
981 regw(0x00000249, SDOFST); isif_config_ycbcr()
H A Ddm355_ccdc.c132 static inline void regw(u32 val, u32 offset) regw() function
143 regw(temp, SYNCEN); ccdc_enable()
152 regw(temp, SYNCEN); ccdc_enable_output_to_sdram()
158 regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN); ccdc_config_gain_offset()
159 regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN); ccdc_config_gain_offset()
160 regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN); ccdc_config_gain_offset()
161 regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN); ccdc_config_gain_offset()
163 regw(ccdc_cfg.bayer.ccdc_offset, OFFSET); ccdc_config_gain_offset()
177 regw(0, i); ccdc_restore_defaults()
180 regw(MODESET_DEFAULT, MODESET); ccdc_restore_defaults()
182 regw(CULH_DEFAULT, CULH); ccdc_restore_defaults()
183 regw(CULV_DEFAULT, CULV); ccdc_restore_defaults()
190 regw(OUTCLIP_DEFAULT, OUTCLIP); ccdc_restore_defaults()
191 regw(LSCCFG2_DEFAULT, LSCCFG2); ccdc_restore_defaults()
241 regw(horz_start, SPH); ccdc_setwin()
242 regw(horz_nr_pixels, NPH); ccdc_setwin()
251 regw(vert_start, VDINT0); ccdc_setwin()
258 regw(vert_start, VDINT0); ccdc_setwin()
259 regw(mid_img, VDINT1); ccdc_setwin()
261 regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0); ccdc_setwin()
262 regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1); ccdc_setwin()
263 regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV); ccdc_setwin()
369 regw(CCDC_REC656IF_BT656_EN, REC656IF); ccdc_config_ycbcr()
387 regw(temp, MODESET); ccdc_config_ycbcr()
395 regw(temp, CCDCFG); ccdc_config_ycbcr()
402 regw(((params->win.width * 2 + 31) >> 5), HSIZE); ccdc_config_ycbcr()
407 regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST); ccdc_config_ycbcr()
423 regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB); ccdc_config_black_clamp()
424 regw(0x0000, CLAMP); ccdc_config_black_clamp()
431 regw(val, CLAMP); ccdc_config_black_clamp()
436 regw(val, DCSUB); ccdc_config_black_clamp()
450 regw(val, BLKCMP1); ccdc_config_black_compense()
456 regw(val, BLKCMP0); ccdc_config_black_compense()
469 regw(dfc->dft_corr_vert[index], DFCMEM0); ccdc_write_dfc_entry()
470 regw(dfc->dft_corr_horz[index], DFCMEM1); ccdc_write_dfc_entry()
471 regw(dfc->dft_corr_sub1[index], DFCMEM2); ccdc_write_dfc_entry()
472 regw(dfc->dft_corr_sub2[index], DFCMEM3); ccdc_write_dfc_entry()
473 regw(dfc->dft_corr_sub3[index], DFCMEM4); ccdc_write_dfc_entry()
476 regw(val, DFCMEMCTL); ccdc_write_dfc_entry()
511 regw(val, DFCCTL); ccdc_config_vdfc()
525 regw(val , DFCCTL); ccdc_config_vdfc()
535 regw(val, DFCMEMCTL); ccdc_config_vdfc()
541 regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT); ccdc_config_vdfc()
544 regw(val, DFCCTL); ccdc_config_vdfc()
562 regw(CCDC_CSC_ENABLE, CSCCTL); ccdc_config_csc()
589 regw(val2, (CSCM0 + ((i - 1) << 1))); ccdc_config_csc()
606 regw(val, COLPTN); ccdc_config_color_patterns()
630 regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC | ccdc_config_raw()
665 regw(val , MODESET); ccdc_config_raw()
669 regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT); ccdc_config_raw()
687 regw(val, GAMMAWD); ccdc_config_raw()
720 regw(val, DATAOFST); ccdc_config_raw()
745 regw(val, HSIZE); ccdc_config_raw()
751 regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST); ccdc_config_raw()
756 regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST); ccdc_config_raw()
763 regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST); ccdc_config_raw()
768 regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST); ccdc_config_raw()
915 regw((addr >> 21) & 0x007f, STADRH); ccdc_setfbaddr()
916 regw((addr >> 5) & 0x0ffff, STADRL); ccdc_setfbaddr()
H A Dvpif.c287 regw(value, vpifregs[channel_id].h_cfg); vpif_set_mode_info()
292 regw(value, vpifregs[channel_id].v_cfg_00); vpif_set_mode_info()
297 regw(value, vpifregs[channel_id].v_cfg_01); vpif_set_mode_info()
302 regw(value, vpifregs[channel_id].v_cfg_02); vpif_set_mode_info()
305 regw(value, vpifregs[channel_id].v_cfg); vpif_set_mode_info()
357 regw(value, reg); config_vpif_params()
361 regw((vpifparams->video_params.hpitch), config_vpif_params()
383 regw(0x80, VPIF_REQ_SIZE); vpif_set_video_params()
384 regw(0x01, VPIF_EMULATION_CTRL); vpif_set_video_params()
397 regw(value, vpifregs[channel_id].vanc0_strt); vpif_set_vbi_display_params()
401 regw(value, vpifregs[channel_id].vanc1_strt); vpif_set_vbi_display_params()
405 regw(value, vpifregs[channel_id].vanc0_size); vpif_set_vbi_display_params()
409 regw(value, vpifregs[channel_id].vanc1_size); vpif_set_vbi_display_params()
/linux-4.4.14/drivers/ide/
H A Dsis5513.c461 u16 regw; init_chipset_sis5513() local
466 pci_read_config_word(dev, 0x50, &regw); init_chipset_sis5513()
467 if (regw & 0x08) init_chipset_sis5513()
468 pci_write_config_word(dev, 0x50, regw&0xfff7); init_chipset_sis5513()
469 pci_read_config_word(dev, 0x52, &regw); init_chipset_sis5513()
470 if (regw & 0x08) init_chipset_sis5513()
471 pci_write_config_word(dev, 0x52, regw&0xfff7); init_chipset_sis5513()
539 u16 regw = 0; sis_cable_detect() local
541 pci_read_config_word(pdev, reg_addr, &regw); sis_cable_detect()
542 ata66 = (regw & 0x8000) ? 0 : 1; sis_cable_detect()
/linux-4.4.14/drivers/ata/
H A Dpata_sis.c655 u16 regw; sis_fixup() local
659 pci_read_config_word(pdev, 0x50, &regw); sis_fixup()
660 if (regw & 0x08) sis_fixup()
661 pci_write_config_word(pdev, 0x50, regw & ~0x08); sis_fixup()
662 pci_read_config_word(pdev, 0x52, &regw); sis_fixup()
663 if (regw & 0x08) sis_fixup()
664 pci_write_config_word(pdev, 0x52, regw & ~0x08); sis_fixup()

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